osaca_version: 0.5.0
micro_architecture: Fujitsu A64FX
arch_code: a64fx
isa: AArch64
ROB_size: 48
retired_uOps_per_cycle: 4
scheduler_size: 79
hidden_loads: false 
load_latency: {w: 5.0, x: 5.0, b: 5.0, h: 5.0, s: 5.0, d: 8.0, q: 8.0, v: 8.0, z: 11.0}
#load_throughput_multiplier: {w: 1.0, x: 1.0, b: 1.0, h: 1.0, s: 1.0, d: 1.0, q: 1.0, v: 2.0, z: 2.0}
load_throughput:
- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure:   [[1, '56'], [1, ['5D', '6D']]]}
- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure:  [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]}
- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure:   [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure:  [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure:    [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure:   [[1, '56'], [1, ['5D', '6D']]]}
- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure:     [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure:    [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure:  [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]}
- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure:   [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure:  [[1, '56'], [1, ['5D', '6D']], [1, '3456']]}
load_throughput_default: [[1, '56'], [1, ['5D', '6D']]]
store_throughput: []
store_throughput_default: [[1, '5'], [1, '6']]
p_index_latency: 1
#store_throughput_multiplier: {w: 1.0, x: 1.0, b: 1.0, h: 1.0, s: 1.0, d: 1.0, q: 1.0, v: 2.0, z: 2.0}
ports: ['0', 0DV, '1', '2', '3', '4', '5', 5D, '6', 6D, '7']
port_model_scheme: |
  +---------------------------------------------------------------------------------+
  |                2 * 10 entry RSA0/1, 2 * 20 entry RSE0/1, 19 entry RSBR          |
  +---------------------------------------------------------------------------------+
    0 |FLA    1 |PR      2 |FLB   3 |EXA    4 |EXB     5 |EAGA   6 |EAGB    7 |BR
      \/        \/         \/       \/        \/         \/        \/         \/
   +-------+ +-------+ +-------+ +-------+ +-------+  +-------+ +-------+  +------+
   |INT ALU| |Predic.| |Int ALU| |Int ALU| |Int ALU|  |Int ALU| |Int ALU|  |Branch|
   +-------+ | manip.| +-------+ +-------+ +-------+  +-------+ +-------+  +------+
   +-------+ +-------+ +-------+ +-------+ +-------+  +-------+ +-------+
   | FP ALU|           | FP ALU| |  MUL  | |  DIV  |  |  AGU  | |  AGU  |
   +-------+           +-------+ +-------+ +-------+  +-------+ +-------+
   +-------+           +-------+ +-------+ +-------+  +-------+ +-------+
   |  FMA  |           |  FMA  | | SHIFT | | SHIFT |  |  LOAD | |  LOAD |
   +-------+           +-------+ +-------+ +-------+  +-------+ +-------+
   +-------+           +-------+ +-------+
   | FP DIV|           | SHIFT | | INT ST|
   +-------+           +-------+ +-------+
   +-------+
   | SHIFT |
   +-------+
   +-------+
   | CRYPTO|
   +-------+
   +-------+
   | FP ST |
   +-------+
   +--------+
   |VEC ADDR|
   |  CALC  |
   +--------+
instruction_forms:
- name: add
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: add
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: addvl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: w
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: add
  operands:
  - class: register
    prefix: z
    shape: '*'
    width: '*'
  - class: register
    prefix: z
    shape: '*'
    width: '*'
  - class: immediate
    imd: '*'
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '02']]
- name: add
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: immediate
    imd: '*'
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '02']]
- name: add
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '02']]
- name: addpl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: adds
  operands:
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: adds
  operands:
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: and
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: and
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: and
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: and
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: b
  operands:
  - class: identifier
  throughput: 1.0
  latency: 0.0
  port_pressure: [[1, '7']]
- name: bl
  operands:
  - class: identifier
  throughput: 1.0
  latency: 0.0
  port_pressure: [[1, '7']]
- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, bal, b.al, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq, bge]
  operands:
  - class: identifier
  throughput: 1.0
  latency: 0.0
  port_pressure: [[1, '7']]
- name: bfi
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  throughput: 4.0
  latency: 5.0  # 	4*p34
  port_pressure: [[4, '34']]
- name: sbfiz
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  throughput: 1.0
  latency: 3.0  # 	2*p34
  port_pressure: [[2, '34']]
- name: [cbz, cbnz]
  operands:
  - class: register
    prefix: '*'
  - class: identifier
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: [ccmp, ccmn]
  operands:
  - class: register
    prefix: "*"
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  - class: condition
    ccode: "*"
  throughput: 1.0
  latency: 2.0  # 	2*p3 | 2*p4
  port_pressure: [[2, '34']]
- name: [ccmp, ccmn]
  operands:
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: immediate
    imd: int
  - class: condition
    ccode: "*"
  throughput: 1.0
  latency: 2.0  # 	2*p3 | 2*p4
  port_pressure: [[2, '34']]
- name: [csel, csinc, csinv, csneg]
  operands:
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: condition
    ccode: "*"
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: [cinc, cinv, cneg]
  operands:
  - class: register
    prefix: "*"
  - class: register
    prefix: "*"
  - class: condition
    ccode: "*"
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: [cset, csetm]
  operands:
  - class: register
    prefix: "*"
  - class: condition
    ccode: "*"
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: cmp
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: cmp
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: cmp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: cmp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: dup
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 1.0
  latency: 6.0  # 	1*p0
  port_pressure: [[1, '0']]
- name: dup
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 1.0
  latency: 6.0  # 	1*p0
  port_pressure: [[1, '0']]
- name: fadd
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fadd
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: immediate
    imd: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fadd
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fadda
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: p
  - class: register
    prefix: d
  - class: register
    prefix: z
    shape: d
    width: '512'
  throughput: 18.5
  latency: 72.0  # 	18*p0+19*p02
  port_pressure: [[18, '0'], [19, '02']]
- name: faddv
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: d
    width: '512'
  throughput: 11.5
  latency: 49.0  # 	11*p0+12*p02
  port_pressure: [[9, '0'], [14, '02']]
- name: fadd
  operands:
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fadd
  operands:
  - class: register
    prefix: d
    width: '*'
  - class: register
    prefix: d
    width: '*'
  - class: register
    prefix: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmadd
  operands:
  - class: register
    prefix: d
    width: '*'
  - class: register
    prefix: d
    width: '*'
  - class: register
    prefix: d
    width: '*'
  - class: register
    prefix: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fadd
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fdiv
  operands:
  - class: register
    prefix: v
    shape: s
    width: 128
  - class: register
    prefix: v
    shape: s
    width: 128
  - class: register
    prefix: v
    shape: s
    width: 128
  throughput: 29.0
  latency: 29.0  # 	1*p0+29*p0DV
  port_pressure: [[1, '0'], [29.0, [0DV]]]
- name: fdivr
  operands:
  - class: register
    prefix: v
    shape: s
    width: 128
  - class: register
    prefix: v
    shape: s
    width: 128
  - class: register
    prefix: v
    shape: s
    width: 128
  throughput: 29.0
  latency: 29.0  # 	1*p0+29*p0DV
  port_pressure: [[1, '0'], [29.0, [0DV]]]
- name: fdivr  # JH: educated guess
  operands:
  - class: register
    prefix: z
    shape: d
    width: 128
  - class: register
    prefix: p
    predication: '*'
  - class: register
    prefix: z
    shape: d
    width: 128
  - class: register
    prefix: z
    shape: d
    width: 128
  throughput: 38.0  # JH assuming 38 from ('A64FX','gcc', 'Ofast','pi') results
  latency: 43.0
  port_pressure: [[1, '0'], [38.0, [0DV]]]  
- name: fcmla
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: immediate
    imd: int
  throughput: 2.0
  latency: 16.0  # 	2*p0+1*p02
  port_pressure: [[2, '0'], [1, '02']]
- name: fcadd
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: immediate
    imd: int
  throughput: 1.0
  latency: 15.0  # 	1*p0+1*p2
  port_pressure: [[1, '0'], [1, '2']]
- name: fdiv
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  throughput: 43.0
  latency: 43.0  # 	1*p0+43*p0DV
  port_pressure: [[1, '0'], [43, ['0DV']]]
- name: fdiv
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  throughput: 29.0
  latency: 29.0  # 	1*p0+29*p0DV
  port_pressure: [[1, '0'], [29, ['0DV']]]
- name: fdiv
  operands:
  - class: register
    prefix: h
  - class: register
    prefix: h
  - class: register
    prefix: have
  throughput: 38.0
  latency: 38.0  # 	1*p0+38*p0DV
  port_pressure: [[1, '0'], [38, ['0DV']]]
- name: fdiv
  operands:
  - class: register
    prefix: v
    shape: d
    width: 128
  - class: register
    prefix: v
    shape: d
    width: 128
  - class: register
    prefix: v
    shape: d
    width: 128
  throughput: 43.0
  latency: 43.0  # 	1*p0+43*p0DV
  port_pressure: [[1, '0'], [43.0, [0DV]]]
- name: [fmad, fmla, mla]
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: [fmad, fmla, mla, fmsb, fmls, mls]
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: m
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: [fmad, fmla, fmsb, fmls]
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: m
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: immediate
    imd: 'double'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: [fmla, fmls, mla, mls]
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmov
  operands:
  - {class: register, prefix: s}
  - {class: immediate, imd: double}
  latency: 1  # 	1*p0
  port_pressure: [[1, '0']]
  throughput: 1.0
- name: fmov
  operands:
  - class: register
    prefix: z
    shape: d
  - class: immediate
    imd: double
  latency: 1  # 	1*p0
  port_pressure: [[1, '0']]
  throughput: 1.0
- name: [fmsb, fmls]
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: m
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmul
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmul
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
    predication: m
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmul
  operands:
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmul
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fmul
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fneg
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: frecpe
  operands:
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: frecpe
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fsub
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fsub
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fsub
  operands:
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: s
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: fsub
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: d
    width: '*'
  throughput: 0.5
  latency: 9.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: [incb, incd]
  operands:
  - class: register
    prefix: x
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: index
  operands:
  - class: register
    prefix: z
    shape: d
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  throughput: 1.0
  latency: 1.0  # 	1*p0
  port_pressure: [[1, '0']]
- name: [incb, incd]
  operands:
  - class: register
    prefix: x
  - class: identifier
  - class: identifier
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: ld1d
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1d
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1d
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1w
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1w
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1w
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1h
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1h
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1h
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1b
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1b
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1b
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1sw
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sw
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sw
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1sh
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sh
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sh
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld1sb
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: ~
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sb
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: x
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 8.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ld1sb
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: ~
    index: z
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses
- name: ld2d
  operands:
  - class: register
    prefix: 'z'
    shape: 'd'
  - class: register
    prefix: 'z'
    shape: 'd'
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 11.0  # 	1*p0+1*p3+4*p56+1*p5D6D
  port_pressure: [[2, '56'], [4, ['5D', '6D']]]
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D
  port_pressure: [[2, '56'], [2, ['5D', '6D']]]
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D
  port_pressure: [[2, '56'], [2, ['5D', '6D']]]
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: ~
    index: ~
    scale: 1
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D
  port_pressure: [[2, '56'], [2, ['5D', '6D']]]
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: true
    post_indexed: false
  throughput: 1.0
  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
- name: ldur    # JL: assumed from ldr
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 0.5
  latency: 5.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ldur    # JH: assumed from ldur with q
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 0.5
  latency: 5.0  # 	1*p56+1*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: [ldur, ldursb, ldursw, ldursh]
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ldr     # JL: assumed from manual
  operands:
  - class: register
    prefix: z
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 1.0
  latency: 11.0  # 	1*p5+1*p5D
  port_pressure: [[1, '56'], [2, ['5D','6D']]]
- name: ldr
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 0.5
  latency: 5.0  # 	2*p56+2*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ldr
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 0.5
  latency: 5.0  # 	2*p56+2*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ldrb
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 0.5
  latency: 5.0  # 	2*p56+2*p5D6D
  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
- name: ldrsw
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ldr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ldr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ldr
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ldr
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  throughput: 0.0
  latency: 0.0
  port_pressure: []
- name: ld2
  operands:
  - class: register
    prefix: v
  - class: register
    prefix: v
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 1.0
  latency: 11.0  # 	1*p56+2*p5D6D
  port_pressure: [[1, '56'], [2, ['5D','6D']]]
- name: lsl
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: lsl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: madd
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 2.5
  latency: 6.0  # 	5*p34
  port_pressure: [[5, '34']]
- name: madd
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 2.5
  latency: 6.0  # 	5*p34
  port_pressure: [[5, '34']]
- name: mov
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: mov
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: mov
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: mov
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: mov
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: mov
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: z
    shape: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: mov
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: p
    predication: '*'
  - class: register
    prefix: z
    shape: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: [mov, sel]
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: p
    predication: '*'
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: z
    shape: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: mov
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: mov
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 3.0
  latency: 15.0  # 	3*p0+3*p3
  port_pressure: [[3, '0'], [3, '3']]
- name: movprfx
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: z
    shape: '*'
  throughput: 0.5
  latency: 4.0  # 	1*p02
  port_pressure: [[1, '02']]
- name: mul
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 1.0
  latency: 5.0  # 	1*p1
  port_pressure: [[1, '3']]
- name: mul
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 1.0
  latency: 5.0  # 	1*p3
  port_pressure: [[1, '3']]
- name: orr
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  throughput: 0.25
  latency: 1.0  # 	1*p3456
  port_pressure: [[1, '3456']]
- name: orr
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p3456
  port_pressure: [[1, '3456']]
- name: prfm
  operands:
  - class: prfop
    type: '*'
    target: '*'
    policy: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 0
  port_pressure: [[1, '56']]
- name: prfd
  operands:
  - class: prfop
    type: '*'
    target: '*'
    policy: '*'
  - class: register
    prefix: p
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 0
  port_pressure: [[1, '56']]
- name: prfd
  operands:
  - class: immediate
    imd: int
  - class: register
    prefix: p
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 0.5
  latency: 0
  port_pressure: [[1, '56']]
- name: ptrue
  operands:
  - class: register
    prefix: p
  throughput: 1.0
  latency: 3
  port_pressure: [[1, '1']]
- name: ptrue
  operands:
  - class: register
    prefix: p
    shape: '*'
  - class: identifier
  throughput: 1.0
  latency: 3
  port_pressure: [[1, '1']]
- name: ret
  operands: []
  throughput: 0.5
  latency: ~  #     1*p56
  port_pressure: [[1, '56']]
- name: rdvl
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: smaddl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: x
  throughput: 2.0
  latency: 6.0  # 	2*p3
  port_pressure: [[2, '3']]
- name: stp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0
  port_pressure: [[2, '5'], [2,'6'], [2, '0']]
- name: stp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0+1*0234
  port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']]
- name: stp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0
  port_pressure: [[2, '5'], [2,'6'], [2, '0']]
- name: stp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0+1*0234
  port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']]
- name: stp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0
  port_pressure: [[2, '5'], [2,'6'], [2, '0']]
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: true
    post_indexed: false
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0+1*0234
  port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']]
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0+1*0234
  port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']]
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 2.0
  latency: 0  # 	2*p56+2*p0
  port_pressure: [[2, '5'], [2,'6'], [2, '0']]
- name: stur # JL: assumed from str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: stur # JL: assumed from str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: str
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: str
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: true
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0+1*p0234
  port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']]
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0+1*p0234
  port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']]
- name: str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: 1
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0
  port_pressure: [[1, '5'], [1,'6'], [1, '0']]
- name: str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 0  # 	1*p56+1*p0+1*0234
  port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']]
- name: str
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: true
  throughput: 1.0
  latency: 0  # 	1*p56+1*p3+1*p0234
  port_pressure: [[1, '5'], [1,'6'], [1, '3'], [1, '0234']]
- name: str
  operands:
  - class: register
    prefix: z
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p5+1*p6+1*p0
  port_pressure: [[1, '5'], [1, '6'], [1, '0']]
- name: st1d
  operands:
  - class: register
    prefix: z
    shape: d
  - class: register
    prefix: p
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p5+1*p6+1*p0
  port_pressure: [[1, '5'], [1, '6'], [1, '0']]
- name: st2d
  operands:
  - class: register
    prefix: 'z'
    shape: 'd'
  - class: register
    prefix: 'z'
    shape: 'd'
  - class: register
    prefix: p
    predication: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre_indexed: false
    post_indexed: false
  throughput: 1.0
  latency: 0  # 	1*p5+1*p6+1*p0
  port_pressure: [[1, '5'], [1, '6'], [1, '0']]
- name: st2
  operands:
  - class: register
    prefix: v
  - class: register
    prefix: v
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post_indexed: false
    pre_indexed: false
  throughput: 1.0
  latency: 11.0  # 	1*p56+2*p5D6D
  port_pressure: [[1, '5'], [1, ['6']], [1, '0']]
- name: sub
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: sub
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: subs
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: sub
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.25
  latency: 1.0  # 	1*p0234
  port_pressure: [[1, '0234']]
- name: sub
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: subs
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: sxtw
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  throughput: 0.5
  latency: 1.0  # 	1*p34
  port_pressure: [[1, '34']]
- name: tbl
  operands:
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  - class: register
    prefix: z
    shape: d
    width: '*'
  throughput: 1.0
  latency: 6.0  # 	1*p0
  port_pressure: [[1, '0']]
- name: [whilele, whilelo, whilels, whilelt]
  operands:
  - class: register
    prefix: p
    shape: d
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  throughput: 1.0
  latency: 1.0  # 	1*p1+1*p3
  port_pressure: [[1, '1'], [1, '3']]
- name: [zip1, zip2]
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: z
    shape: '*'
  throughput: 1.0
  latency: 6.0
  port_pressure: [[1, '0']]
- name: scvtf
  operands:
  - class: register
    prefix: z
    shape: '*'
  - class: register
    prefix: p
  - class: register
    prefix: z
    shape: '*'
  throughput: 1.0
  latency: 13.0
  port_pressure: [[1, '0'], [1, '3']]
- name: scvtf
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: w
  throughput: 1.0
  latency: 13.0
  port_pressure: [[1, '0'], [1, '3']]
- name: scvtf
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 1.0
  latency: 9.0
  port_pressure: [[1, '02']]
- name: [sshll, sshll2, sxtl, sxtl2]
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: immediate
    imd: int
  throughput: 1.0
  latency: 6.0
  port_pressure: [[1, '2']]
- name: [sadalp, uadalp]
  operands:
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 3.0
  latency: 14.0
  port_pressure: [[3, '2']]
- name: [smlal, smlal2]
  operands:
  - class: register
    prefix: v
    shape: s
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 8.0
  latency: 18.0
  port_pressure: {0: [[8, '0']], 1: [[8, '2']]}
- name: [smlal, smlal2]
  operands:
  - class: register
    prefix: v
    shape: d
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  - class: register
    prefix: v
    shape: '*'
    width: '*'
  throughput: 3.0
  latency: 15.0
  port_pressure: {0: [[3, '0']], 1: [[3, '2']]}
