osaca_version: 0.4.8
micro_architecture: TaiShan v110 # https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
arch_code: tsv110
isa: AArch64
ROB_size: 128 # https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64SchedTSV110.td#L21
retired_uOps_per_cycle: 4
scheduler_size: ~   # unknown
hidden_loads: false
load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
load_throughput: []
load_throughput_default: [[1, '67']]
store_throughput: []
store_throughput_default: [[1, '7']]
ports: ['0', '1', '2', '3', '4', '5', '6', '7']
port_model_scheme: |
  +--------------------------------------------------------------------------------------------+
  |                                - entries                                                   |
  +--------------------------------------------------------------------------------------------+
    0 |ALU      1 |AB       2 |AB       3 |MDU           4 |FSU1   5 |FSU2    6 |LdSt   7 |LdSt    
      \/          \/          \/          \/               \/        \/         \/        \/
   +---------+ +---------+ +---------+ +-------------+  +-------+ +------ +  +-------+ +-------+ 
   | INT ALU | | INT ALU | | INT ALU | | Multi-Cycle |  |   FP  | |   FP  |  | LD/ST | | LD/ST |
   +---------+ |   BRU   | |   BRU   | +-------------+  | ASIMD | | ASIMD |  +-------+ +-------+ 
               +---------+ +---------+                  +-------+ +-------+ 
instruction_forms:
- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq]
  operands:
  - class: identifier
  throughput: 0.5
  latency: 0.0
  port_pressure: [[1, '12']]
# logical instructions: and (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: and
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: and
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: and
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: and
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: ands
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.5
  latency: 1.0
  port_pressure: [[1, '12']]
  uops: 1
- name: ands
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.5
  latency: 1.0
  port_pressure: [[1, '12']]
  uops: 1
- name: ands
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0
  port_pressure: [[1, '12']]
  uops: 1
- name: ands
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.5
  latency: 1.0
  port_pressure: [[1, '12']]
  uops: 1
# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: orr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: orn (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: orn
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orn
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orn
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: orn
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: eor
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: eor
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: eor
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: eor
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: bic
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: bics (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: bics
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.5
  latency: 1.0
  port_pressure: [[1, '12']]
  uops: 1
# logical instructions: rbit (latency and throughput, port data from AArch64SchedTSV110.td)
- name: rbit
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: rbit
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# logical instructions: rev[16|32] (latency and throughput, port data from AArch64SchedTSV110.td)
- name: [rev, rev16, rev32]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: [rev, rev16, rev32]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: lsl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsl
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsl
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: lsr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: lsr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: asr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: asr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: asr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: asr
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# shift instructions: ror (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: ror
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
- name: ror
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# shift instructions: [s|u]shll (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: [sshll, ushll]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'  
  - class: immediate
    imd: int
  latency: 4.0
  throughput: 1.0
  port_pressure: [[1, '5']]
  uops: 1
# shift instructions: sshll2 (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: sshll2
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'  
  - class: immediate
    imd: int
  latency: 4.0
  throughput: 1.0
  port_pressure: [[1, '5']]
  uops: 1
# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench)
- name: add
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  throughput: 0.3333
  latency: 1.0
  port_pressure: [[1, '012']]
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: w
  latency: 1
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: add
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: add
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: add  
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  throughput: 0.5
  latency: 2.0
  port_pressure: [[1, '45']]
- name: add  
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  throughput: 0.5
  latency: 2.0
  port_pressure: [[1, '45']]
- name: add  
  operands:
  - class: register
    prefix: v
    shape: h
  - class: register
    prefix: v
    shape: h
  - class: register
    prefix: v
    shape: h
  throughput: 0.5
  latency: 2.0
  port_pressure: [[1, '45']]
# arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench)
- name: adds
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: adds
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: adds
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: adds
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: addp (from AArch64SchedTSV110.td)
- name: addp 
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  throughput: 0.5
  latency: 2.0
  port_pressure: [[1, '45']]
# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
- name: adc
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
- name: adc
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench)
- name: sub
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: sub
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: sub
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: sub
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: subs
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: subs
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: sbc (latency and throughput, port data from AArch64SchedTSV110.td)
- name: sbc
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: sbc
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: mul
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 4.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 3.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: v
    shape: s
    lanes: 2
  - class: register
    prefix: v
    shape: s
    lanes: 2
  - class: register
    prefix: v
    shape: s
    lanes: 2
  latency: 4.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: v
    shape: h
    lanes: 4
  - class: register
    prefix: v
    shape: h
    lanes: 4
  - class: register
    prefix: v
    shape: h
    lanes: 4
  latency: 4.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: v
    shape: b
    lanes: 8
  - class: register
    prefix: v
    shape: b
    lanes: 8
  - class: register
    prefix: v
    shape: b
    lanes: 8
  latency: 4.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: v
    shape: s
    lanes: 4
  - class: register
    prefix: v
    shape: s
    lanes: 4
  - class: register
    prefix: v
    shape: s
    lanes: 4
  latency: 7.0
  port_pressure: [[2, '3']]
  throughput: 2.0
  uops: 2
- name: mul
  operands:
  - class: register
    prefix: v
    shape: h
    lanes: 8
  - class: register
    prefix: v
    shape: h
    lanes: 8
  - class: register
    prefix: v
    shape: h
    lanes: 8
  latency: 7.0
  port_pressure: [[2, '3']]
  throughput: 2.0
  uops: 1
- name: mul
  operands:
  - class: register
    prefix: v
    shape: b
    lanes: 16
  - class: register
    prefix: v
    shape: b
    lanes: 16
  - class: register
    prefix: v
    shape: b
    lanes: 16
  latency: 7.0
  port_pressure: [[2, '3']]
  throughput: 2.0
  uops: 1
# arithmetic instructions: [s|u]mulh (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: [smulh, umulh]
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 4.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
# arithmetic instructions: [s|u]mull (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: [smull, umull]
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 3.0
  port_pressure: [[1, '3']]
  throughput: 1.0
  uops: 1
# arithmetic instructions: sdiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: sdiv
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 6.0
  port_pressure: [[5, '3']]
  throughput: 5.0
  uops: 1
- name: sdiv
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 6.0
  port_pressure: [[5, '3']]
  throughput: 5.0
  uops: 1
# arithmetic instructions: udiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: udiv
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 6.0
  port_pressure: [[5, '3']]
  throughput: 5.0
  uops: 1
- name: udiv
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 6.0
  port_pressure: [[5, '3']]
  throughput: 5.0
  uops: 1
# arithmetic instructions: madd (latency and throughput, port data from AArch64SchedTSV110.td)
- name: madd
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 4.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
- name: madd
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 4.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: [smaddl|umaddl] (latency and throughput, port data from AArch64SchedTSV110.td)
- name: [smaddl,umaddl]
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: x
  latency: 3.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: [smsubl|umsubl] (latency and throughput, port data from AArch64SchedTSV110.td)
- name: [smsubl, umsubl]
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: x
  latency: 3.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: msub (latency and throughput, port data from AArch64SchedTSV110.td)
- name: msub
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 4.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
- name: msub
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 4.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: smsubl (latency and throughput, port data from AArch64SchedTSV110.td)
- name: smsubl
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: register
    prefix: x
  latency: 3.0
  port_pressure: [[1, '3'], [1, '012']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: mla
  operands:
  - class: register
    prefix: v
    shape: s
    lanes: 2
  - class: register
    prefix: v
    shape: s
    lanes: 2
  - class: register
    prefix: v
    shape: s
  latency: 4.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
- name: mla
  operands:
  - class: register
    prefix: v
    shape: s
    lanes: 4
  - class: register
    prefix: v
    shape: s
    lanes: 4
  - class: register
    prefix: v
    shape: s
    lanes: 4
  latency: 7.0
  port_pressure: [[2, '4']]
  throughput: 2.0
  uops: 2
- name: mla
  operands:
  - class: register
    prefix: v
    shape: h
    lanes: 4
  - class: register
    prefix: v
    shape: h
    lanes: 4
  - class: register
    prefix: v
    shape: h
    lanes: 4
  latency: 4.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
- name: mla
  operands:
  - class: register
    prefix: v
    shape: h
    lanes: 8
  - class: register
    prefix: v
    shape: h
    lanes: 8
  - class: register
    prefix: v
    shape: h
    lanes: 8
  latency: 7.0
  port_pressure: [[2, '4']]
  throughput: 2.0
  uops: 2
# arithmetic instructions: [s|u]max (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: [smax, umax]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[2, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: [s|u]min (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: [smin, umin]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: [s|u]maxv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: [smaxv, umaxv]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: [s|u]minv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: [sminv, uminv]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: neg (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: neg
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
- name: neg
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
- name: neg
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: neg
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: neg
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: neg
  operands:
  - class: register
    prefix: v
    shape: h
  - class: register
    prefix: v
    shape: h
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: negs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: negs
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 2.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: fadd
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 4.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fadd
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 4.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 1
- name: fadd
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fmadd (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fmadd
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 7.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fmadd
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.50
  uops: 1
# arithmetic instructions: fnmsub (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fnmsub
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 7.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fnmsub
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.50
  uops: 1
# arithmetic instructions: frint[a|m|p|x|z] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: frinta
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: frintm
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fabs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: fabs
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fabs
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fabs
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fabs
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fsub (latency and throughput from ibench and asmbench, port data from AArch64SchedTSV110.td) 
- name: fsub
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fsub
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 4.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fsub
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 4.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 1
- name: fsub
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fneg (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fneg
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fneg
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fneg
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 2.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 2
- name: fneg
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: fmul
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fmul
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 5.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 1
- name: fmul
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 5.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fdiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fdiv
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 6.0
  port_pressure: [[6, '4'], [6, '5']]
  throughput: 6.0
  uops: 1
- name: fdiv
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 6.0
  port_pressure: [[6, '4'], [6, '5']]
  throughput: 6.0
  uops: 1
- name: fdiv
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 16.0
  port_pressure: [[12, '4'], [12, '5']]
  throughput: 12.0
  uops: 1
- name: fdiv
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 16.0
  port_pressure: [[12, '4'], [12, '5']]
  throughput: 12.0
  uops: 1
# arithmetic instructions: fmla (latency and throughput from ibench, uops and port data missed)
- name: fmla
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 4.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fmla
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 5.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 2
# arithmetic instructions: fsqrt (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fsqrt
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 9.0
  port_pressure: [[9, '4'], [9, '5']]
  throughput: 9.0
  uops: 1
- name: fsqrt
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 9.0
  port_pressure: [[9, '4'], [9, '5']]
  throughput: 9.0
  uops: 1
- name: fsqrt
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 22.0
  port_pressure: [[18, '4'], [18, '5']]
  throughput: 18.0
  uops: 1
- name: fsqrt
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 22.0
  port_pressure: [[18, '4'], [18, '5']]
  throughput: 18.0
  uops: 1
# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: frecpe
  operands:
  - class: register
    prefix: v
    shape: d
  - class: register
    prefix: v
    shape: d
  latency: 3.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 1
- name: frecpe
  operands:
  - class: register
    prefix: v
    shape: s
  - class: register
    prefix: v
    shape: s
  latency: 3.0
  port_pressure: [[2, '45']]
  throughput: 1.0
  uops: 1
# arithmetic instructions: fcmp (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: fcmp
  operands:
  - class: register
    prefix: d
  - class: immediate
    imd: float
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fcmp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fcmp
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fcmpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) 
- name: fcmpe
  operands:
  - class: register
    prefix: d
  - class: immediate
    imd: float
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fcmpe
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fcmpe
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 3.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# arithmetic instructions: fcvt[as|pu｜zs|zu] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) 
- name: fcvt
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
- name: fcvtpu
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
- name: fcvtzs
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
- name: fcvtzu
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
# mov instructions: adrp? (latency and throughput from asmbench, from AArch64SchedTSV110.td)
- name: [adr, adrp]
  operands:
  - class: register
    prefix: '*'
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
# mov instructions: mov (assumed free register renaming, register to register moves without conversion)
- name: [mov, mvn]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
- name: [mov, mvn]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# mov instructions: mov[i|k|n|z] (assumed free register renaming, register to register moves without conversion)
- name: [movi, movk, movn, movz]
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
- name: [movi, movk, movn, movz]
  operands:
  - class: register
    prefix: d
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
- name: [movi, movk, movn, movz]
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.333
  uops: 1
- name: [movi, movk, movn, movz]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: immediate
    imd: int
  latency: 3.0
  port_pressure: [[1, '4']]
  throughput: 1
  uops: 1
# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td)
- name: dup
  operands:
  - class: register
    prefix: v
    shape: "*"
  - class: register
    prefix: '*'
  latency: 2.0
  port_pressure: [[1, '4'], [1, '5']]
  throughput: 1.0
  uops: 2
- name: dup
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 2
# miscellaneous instructions: cmn (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
- name: cmn
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmn
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmn
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmn
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td)
- name: cmp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmp
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: cmp
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# miscellaneous instructions: extr (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: extr
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# miscellaneous instructions: sbifz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: sbifz
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# miscellaneous instructions: sbfiz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: sbfiz
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  throughput: 0.333
  latency: 1.0
  port_pressure: [[1, '012']]
  uops: 1
# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: [zip1, zip2, uzip1, uzip2]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# miscellaneous instructions: [scvtf|ucvtf] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions)
- name: [scvtf, ucvtf]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 3.0
  port_pressure: [[1, '4'], [1, '5']]
  throughput: 1.0
  uops: 1
# miscellaneous instructions: [s|u]xt[b|h|w] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td)
- name: [sxtb, sxth, sxtw, uxtb, uxth, uxtw]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# miscellaneous instructions: xtn2? (throughput and latency from asmbench, port data from AArch64SchedTSV110.td)
- name: [xtn, xtn2]
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '4'], [1, '5']]
  throughput: 1.0
  uops: 1
# miscellaneous instructions: [ubfiz|ubfx|ubfm] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td)
- name: [ubfiz, ubfx, ubfm]
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  - class: immediate
    imd: int
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '012']]
  throughput: 0.33333
  uops: 1
# miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion)
- name: fmov
  operands:
  - class: register
    prefix: '*'
  - class: register
    prefix: '*'
  latency: 1.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
- name: fmov
  operands:
  - class: register
    prefix: '*'
  - class: immediate
    imd: float
  latency: 1.0
  port_pressure: [[1, '45']]
  throughput: 0.5
  uops: 1
# test instructions: tst (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: tst
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: tst
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: tst
  operands:
  - class: register
    prefix: w
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
- name: tst
  operands:
  - class: register
    prefix: x
  - class: immediate
    imd: int
  latency: 1.0
  port_pressure: [[1, '12']]
  throughput: 0.5
  uops: 1
# cryptography instructions: sha1[c|m|p] (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: [sha1c, sha1m, sha1p]
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: s
  - class: register
    prefix: v
    shape: '*'
  latency: 5.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
# cryptography instructions: sha1h (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: sha1h
  operands:
  - class: register
    prefix: s
  - class: register
    prefix: s
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
# cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: sha1su0
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
# cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: sha1su0
  operands:
  - class: register
    prefix: v
    shape: '*'
  - class: register
    prefix: v
    shape: '*'
  latency: 2.0
  port_pressure: [[1, '4']]
  throughput: 1.0
  uops: 1
# memory instructions: ldr (data from AArch64SchedTSV110.td)
- name: ldr
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldr
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldr
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldr
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldr
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
# memory instructions: ldrb (data from AArch64SchedTSV110.td)
- name: ldrb
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldrb
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
# memory instructions: ldrh (data from AArch64SchedTSV110.td)
- name: ldrh
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldrh
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 5.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
# memory instructions: ldur (data from AArch64SchedTSV110.td)
- name: ldur
  operands:
  - class: register
    prefix: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post-indexed: false
    pre-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
- name: ldur
  operands:
  - class: register
    prefix: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post-indexed: true
    pre-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67'], [1, '012']]
- name: ldur
  operands:
  - class: register
    prefix: '*'
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    post-indexed: false
    pre-indexed: true
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67'], [1, '012']]
# memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td)
- name: [ldar, ldarb, ldaxr]
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: [ldar, ldarb, ldaxr]
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
  # memory instructions: str (data from AArch64SchedTSV110.td)
- name: str
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: str
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: str
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: str
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2 
# memory instructions: stlb (data from AArch64SchedTSV110.td)
- name: strb
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
# memory instructions: stlr (data from AArch64SchedTSV110.td)
- name: stlr
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
# memory instructions: stlrb (data from AArch64SchedTSV110.td)
- name: stlrb
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
# memory instructions: stur (data from AArch64SchedTSV110.td)
- name: stur
  operands:
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: stur
  operands:
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
# memory instructions: stur[b|h] (data from AArch64SchedTSV110.td)
- name: [sturb, sturh]
  operands:
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
# memory instructions: ldp (data from AArch64SchedTSV110.td)
- name: ldp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67'], [1, '012']]
  uops: 2
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67']]
  uops: 2
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67'], [1, '012']]
  uops: 3
- name: ldp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67'], [1, '012']]
  uops: 3
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67'], [1, '012']]
  uops: 3
- name: ldp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 0.5
  latency: 4.0
  port_pressure: [[1, '67']]
  uops: 1
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67'], [1, '012']]
  uops: 3
- name: ldp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 4.0
  port_pressure: [[2, '67'], [1, '012']]
  uops: 3
# memory instructions: stp (data from AArch64SchedTSV110.td)
- name: stp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: stp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: x
  - class: register
    prefix: x
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7']]
  uops: 1
- name: stp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: w
  - class: register
    prefix: w
  - class: memory
    base: w
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 1.0
  latency: 0
  port_pressure: [[1, '7'], [1, '012']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7'], [1, '012']]
  uops: 3
- name: stp
  operands:
  - class: register
    prefix: d
  - class: register
    prefix: d
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7'], [1, '012']]
  uops: 3
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: false
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7']]
  uops: 2
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: true
    post-indexed: false
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7'], [1, '012']]
  uops: 3
- name: stp
  operands:
  - class: register
    prefix: q
  - class: register
    prefix: q
  - class: memory
    base: x
    offset: '*'
    index: '*'
    scale: '*'
    pre-indexed: false
    post-indexed: true
  throughput: 2.0
  latency: 0
  port_pressure: [[2, '7'], [1, '012']]
  uops: 3
