diff --git a/osaca/data/isa/AArch64.yml b/osaca/data/isa/AArch64.yml
index f5878bf..362caa8 100644
--- a/osaca/data/isa/AArch64.yml
+++ b/osaca/data/isa/AArch64.yml
@@ -115,6 +115,25 @@ instruction_forms:
           post-indexed: true 
           source: true
           destination: false
+    - name: "ldp"
+      operands:
+        - class: "register"
+          prefix: "q"
+          source: false
+          destination: true
+        - class: "register"
+          prefix: "q"
+          source: false
+          destination: true
+        - class: "memory"
+          base: "x"
+          offset: "imd" 
+          index: ~
+          scale: 1
+          pre-indexed: true
+          post-indexed: false 
+          source: true
+          destination: true
     - name: "stp"
       operands:
         - class: "register"
diff --git a/osaca/data/vulcan.yml b/osaca/data/vulcan.yml
index f24fab7..ac96a3a 100644
--- a/osaca/data/vulcan.yml
+++ b/osaca/data/vulcan.yml
@@ -1,5 +1,6 @@
 osaca_version: 0.3.0
-micro_architecture: "Vulcan"
+micro_architecture: "Cavium Vulcan"
+arch_code: "Vulcan"
 isa: "AArch64"
 port_model_scheme: |
     ┌-----------------------------------------------------------┐
@@ -274,7 +275,23 @@ instruction_forms:
           pre-indexed: false
           post-indexed: true
       throughput: 1.0
-      latency: ~  #  0   0DV   1   1DV   2    3    4    5
+      latency: ~    #  0   0DV   1   1DV   2    3    4    5
+      port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 1.0, 0.0]
+    - name: "ldp"
+      operands:
+        - class: "register"
+          prefix: "q"
+        - class: "register"
+          prefix: "q"
+        - class: "memory"
+          base: "x"
+          offset: "imd"
+          index: ~
+          scale: 1
+          pre-indexed: true
+          post-indexed: false
+      throughput: 1.0
+      latency: ~    #  0   0DV   1   1DV   2    3    4    5
       port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 1.0, 0.0]
     - name: "ldr"
       operands:
diff --git a/tests/test_files/kernel-AArch64.s b/tests/test_files/kernel-AArch64.s
index af5d048..6920607 100644
--- a/tests/test_files/kernel-AArch64.s
+++ b/tests/test_files/kernel-AArch64.s
@@ -1,7 +1,7 @@
 .LBB0_32:
     ldp q4, q5, [x9, #-32]
     ldp q6, q7, [x9], #64
-    ldp q16, q17, [x11, #-32]
+    ldp q16, q17, [x11, #-32]!
     ldp q18, q19, [x11], #64
     fmul    v4.2d, v4.2d, v16.2d
     fmul    v5.2d, v5.2d, v17.2d
diff --git a/tests/test_semantics.py b/tests/test_semantics.py
index 6c04562..8cd2365 100755
--- a/tests/test_semantics.py
+++ b/tests/test_semantics.py
@@ -55,6 +55,13 @@ class TestSemanticTools(unittest.TestCase):
     # Tests
     ###########
 
+    def test_creation_by_name(self):
+        try:
+            tmp_mm = MachineModel(arch='CSX')
+            SemanticsAppender(tmp_mm)
+        except ValueError:
+            self.fail()
+
     def test_src_dst_assignment_x86(self):
         for instruction_form in self.kernel_x86:
             with self.subTest(instruction_form=instruction_form):
@@ -115,7 +122,7 @@ class TestSemanticTools(unittest.TestCase):
         self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
         self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=2)), {6, 7})
         self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=3)), {8, 9})
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {6, 7})
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {5, 6, 7})
         self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=5)), {8, 9})
         self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=6)), 12)
         self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=7)), 13)