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RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests

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- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples
This commit is contained in:
Metehan Dundar
2025-06-30 00:28:52 +02:00
parent 1c2be468d9
commit 074118dee0
30 changed files with 762 additions and 1266 deletions
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3
tests/test_base_parser.py
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@@ -28,6 +28,8 @@ class TestBaseParser(unittest.TestCase):
self.x86_code = f.read()
with open(self._find_file("kernel_aarch64.s")) as f:
self.aarch64_code = f.read()
with open(self._find_file("kernel_riscv.s")) as f:
self.riscv_code = f.read()
##################
# Test
@@ -75,6 +77,7 @@ class TestBaseParser(unittest.TestCase):
self.assertEqual(BaseParser.detect_ISA(self.triad_code_arm), ("aarch64", None))
self.assertEqual(BaseParser.detect_ISA(self.x86_code), ("x86", "ATT"))
self.assertEqual(BaseParser.detect_ISA(self.aarch64_code), ("aarch64", None))
self.assertEqual(BaseParser.detect_ISA(self.riscv_code), ("riscv", None))
##################
# Helper functions