Lerking/OSACA
1
0
Fork 0
mirror of https://github.com/RRZE-HPC/OSACA.git synced 2025-12-16 00:50:06 +01:00
Code Issues Packages Projects Releases Wiki Activity

Validation (#71)

Browse Source 
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels.

build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release.

For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz

The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb

Quite a few changes on OSACA included:

Feature: register change tracking via semantic understanding of operations
Feature: recording LCD latency along path and exposing this to frontend
Feature: support for memory reference aliases
Feature: store throughput scaling (similar to load throughput scaling)
Fix: model importer works with latest uops.info export
Fix: immediate type tracking on ARM now preserves type in internal representaion
Removed unused KerncraftAPI
This commit is contained in:
Julian
2021-04-15 14:42:37 +02:00
committed by GitHub
parent 25a0e0607d
commit 08440ed5e1
44 changed files with 72388 additions and 149982 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
tests/test_frontend.py
View File

@@ -63,14 +63,15 @@ class TestFrontend(unittest.TestCase):
Frontend(arch="zen1")
def test_frontend_x86(self):
dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx)
dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx, self.semantics_csx)
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml"))
fe.throughput_analysis(self.kernel_x86, show_cmnts=False)
fe.latency_analysis(dg.get_critical_path())
# TODO compare output with checked string
def test_frontend_AArch64(self):
dg = KernelDG(self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2)
dg = KernelDG(
self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2, self.semantics_tx2)
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "tx2.yml"))
fe.full_analysis(self.kernel_AArch64, dg, verbose=True)
# TODO compare output with checked string