From 09679fc8d9451f850ec3090159b4d1beb8e6dc0e Mon Sep 17 00:00:00 2001
From: Jan Laukemann <ol68umur@stud.informatik.uni-erlangen.de>
Date: Sun, 2 Sep 2018 14:11:24 +0200
Subject: [PATCH] changes for 0.2 upgrade

---
 osaca/__init__.py       | 3 ++-
 osaca/data/skl_data.csv | 6 +++---
 osaca/eu_sched.py       | 3 ++-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/osaca/__init__.py b/osaca/__init__.py
index b650ceb..3d9fc2c 100644
--- a/osaca/__init__.py
+++ b/osaca/__init__.py
@@ -1 +1,2 @@
-__version__ = '0.2'
+name = "osaca"
+__version__ = '0.2.0'
diff --git a/osaca/data/skl_data.csv b/osaca/data/skl_data.csv
index 124e188..06a623e 100644
--- a/osaca/data/skl_data.csv
+++ b/osaca/data/skl_data.csv
@@ -110,7 +110,7 @@ vfmadd213ps-xmm_xmm_xmm,0.5,4.0,"(0.5, 0, 0.5, 0, 0, 0, 0, 0, 0)"
 vfmadd213sd,0.5,5.0,"(-1,)"
 vfmadd213ss,0.5,5.0,"(-1,)"
 vinsertf128-ymm_ymm_imd,1.0,3.0,"(-1,)"
-vmovapd-mem_ymm,1.0,-1.0,"(0, 0, 0, 0, 0, 1.0, 0, 0, 0)"
+vmovapd-mem_ymm,1.0,-1.0,"(0, 0, 0, 0.5, 0.5, 1.0, 0, 0, 0)"
 vmovapd-ymm_mem,0.5,-1.0,"(0, 0, 0, 0.5, 0.5, 0, 0, 0, 0)"
 vmovaps-mem_xmm,1.0,3.0,"(0, 0, 0, 0.5, 0.5, 1.0, 0, 0, 0)"
 vmovaps-xmm_mem,0.5,2.0,"(0, 0, 0, 0.5, 0.5, 0, 0, 0, 0)"
@@ -130,7 +130,7 @@ vsubpd-ymm_ymm_mem,0.5,4.0,"(-1,)"
 vsubsd-xmm_xmm_mem,0.5,4.0,"(-1,)"
 vsubsd-xmm_xmm_xmm,0.5,4.0,"(-1,)"
 vsubss-xmm_xmm_xmm,0.5,4.0,"(-1,)"
-vxorps-xmm_xmm_xmm,0.3333333333333333,1.0,"(0.33, 0,0.33,0,0,0,0.33,0,0)"
+vxorps-xmm_xmm_xmm,0.25,1.0,"(0.25, 0,0.25,0,0,0,0.25,0.25,0)"
 xor-r32_r32,0.25,1.0,"(0.25, 0,0.25,0,0,0,0.25,0.25,0)"
 cmpl-r32_imd,0.25,1.0,"(0.25, 0, 0.25,0,0,0,0.25,0.25,0)"
 vaddpd-xmm_xmm_xmm,0.5,4,"(0.5, 0, 0.5, 0, 0, 0, 0, 0, 0)"
@@ -146,7 +146,7 @@ vmulpd-xmm_xmm_xmm,0.5,4,"(0.5, 0, 0.5, 0, 0, 0, 0, 0, 0)"
 vpaddd-xmm_xmm_xmm,0.3333333333333333,1,"(0.33, 0, 0.33, 0, 0, 0, 0.33, 0, 0)"
 vpaddd-ymm_ymm_ymm,0.3333333333333333,1,"(0.33, 0, 0.33, 0, 0, 0, 0.33, 0, 0)"
 vpshufd-xmm_xmm_imd,1.0,1,"(0, 0, 0, 0, 0, 0, 1.0, 0, 0)"
-vxorpd-xmm_xmm_xmm,0.3333333333333333,1,"(0.33, 0, 0.33, 0, 0, 0, 0.33, 0, 0)"
+vxorpd-xmm_xmm_xmm,0.25,1,"(0.25, 0, 0.25, 0, 0, 0, 0.25, 0.25, 0)"
 vdivpd-ymm_ymm_ymm,8.0,14.0,"(1.0, 8.0, 0, 0, 0, 0, 0, 0, 0)"
 vdivps-ymm_ymm_ymm,5.0,11.0,"(1.0, 5.0, 0, 0, 0, 0, 0, 0, 0)"
 vdivpd-xmm_xmm_xmm,4.0,13,"(1.0, 4.0, 0, 0, 0, 0, 0, 0, 0)"
diff --git a/osaca/eu_sched.py b/osaca/eu_sched.py
index 05ae5f5..ed66d32 100755
--- a/osaca/eu_sched.py
+++ b/osaca/eu_sched.py
@@ -35,7 +35,7 @@ class Scheduler(object):
         # check for parallel ld/st in a cycle
         if(arch == 'ZEN'):
             self.en_par_ldst = True
-            self.ld_ports = [8, 9]
+            self.ld_ports = [9, 10]
         # check for DV port
         try:
             self.dv_port = self.dv_port_dict[arch]
@@ -102,6 +102,7 @@ class Scheduler(object):
                         par_ldst -= 1
                         p_flg = 'P '
                         for port in self.ld_ports:
+                            tmp_port_add = 1 if(self.dv_port != -1 and self.dv_port < port) else 0
                             occ_ports[i][port] = '(' + str(occ_ports[i][port]) + ')'
             # Write schedule line
             if(len(p_flg) > 0):