mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-15 16:40:05 +01:00
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
This commit is contained in:
stefandesouza
@@ -9,24 +9,24 @@ from io import StringIO
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import osaca.db_interface as dbi
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from osaca.db_interface import sanity_check
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from osaca.semantics import MachineModel
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from osaca.parser import InstructionForm
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser import instructionForm
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from osaca.parser.memory import memoryOperand
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from osaca.parser.register import registerOperand
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import copy
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class TestDBInterface(unittest.TestCase):
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@classmethod
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def setUpClass(self):
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sample_entry = InstructionForm(
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INSTRUCTION_ID="DoItRightAndDoItFast",
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OPERANDS_ID=[
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MemoryOperand(OFFSET_ID="imd", BASE_ID="gpr", INDEX_ID="gpr", SCALE_ID=8),
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RegisterOperand(NAME_ID="xmm"),
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sample_entry = instructionForm(
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instruction_id="DoItRightAndDoItFast",
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operands_id=[
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memoryOperand(offset_ID="imd", base_id="gpr", index_id="gpr", scale_id=8),
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registerOperand(name_id="xmm"),
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],
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THROUGHPUT=1.25,
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LATENCY=125,
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UOPS=6,
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throughput=1.25,
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latency=125,
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uops=6,
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)
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self.entry_csx = copy.copy(sample_entry)
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@@ -61,7 +61,7 @@ class TestDBInterface(unittest.TestCase):
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mm_csx.set_instruction_entry(self.entry_csx)
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mm_tx2.set_instruction_entry(self.entry_tx2)
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mm_zen1.set_instruction_entry(InstructionForm(INSTRUCTION_ID="empty_operation"))
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mm_zen1.set_instruction_entry(instructionForm(instruction_id="empty_operation"))
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num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx
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num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2
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@@ -72,7 +72,7 @@ class TestDBInterface(unittest.TestCase):
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self.assertEqual(num_entries_zen1, 1)
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def test_invalid_add(self):
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entry = InstructionForm()
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entry = instructionForm()
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# with self.assertRaises(KeyError):
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# MachineModel("csx").set_instruction_entry(entry)
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with self.assertRaises(TypeError):
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@@ -8,12 +8,12 @@ import unittest
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from pyparsing import ParseException
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from osaca.parser import ParserAArch64, InstructionForm
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from osaca.parser import ParserAArch64, instructionForm
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from osaca.parser.operand import Operand
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from osaca.parser.directive import DirectiveOperand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.directive import directiveOperand
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from osaca.parser.memory import memoryOperand
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from osaca.parser.register import registerOperand
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from osaca.parser.immediate import immediateOperand
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class TestParserAArch64(unittest.TestCase):
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@@ -181,140 +181,140 @@ class TestParserAArch64(unittest.TestCase):
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line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90"
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line_conditions = "ccmn x11, #1, #3, eq"
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instruction_form_1 = InstructionForm(
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INSTRUCTION_ID=None,
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OPERANDS_ID=[],
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DIRECTIVE_ID=None,
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COMMENT_ID="-- Begin main",
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LABEL_ID=None,
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LINE="// -- Begin main",
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LINE_NUMBER=1,
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instruction_form_1 = instructionForm(
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instruction_id=None,
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operands_id=[],
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directive_id=None,
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comment_id="-- Begin main",
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label_id=None,
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line="// -- Begin main",
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line_number=1,
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)
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instruction_form_2 = InstructionForm(
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INSTRUCTION_ID=None,
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OPERANDS_ID=[],
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DIRECTIVE_ID=None,
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COMMENT_ID="=>This Inner Loop Header: Depth=1",
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LABEL_ID=".LBB0_1",
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LINE=".LBB0_1: // =>This Inner Loop Header: Depth=1",
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LINE_NUMBER=2,
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instruction_form_2 = instructionForm(
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instruction_id=None,
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operands_id=[],
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directive_id=None,
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comment_id="=>This Inner Loop Header: Depth=1",
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label_id=".LBB0_1",
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line=".LBB0_1: // =>This Inner Loop Header: Depth=1",
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line_number=2,
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)
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instruction_form_3 = InstructionForm(
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INSTRUCTION_ID=None,
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OPERANDS_ID=[],
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DIRECTIVE_ID=DirectiveOperand(NAME_ID="cfi_def_cfa", PARAMETER_ID=["w29", "-16"]),
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COMMENT_ID=None,
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LABEL_ID=None,
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LINE=".cfi_def_cfa w29, -16",
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LINE_NUMBER=3,
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instruction_form_3 = instructionForm(
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instruction_id=None,
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operands_id=[],
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directive_id=directiveOperand(name_id="cfi_def_cfa", parameter_id=["w29", "-16"]),
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comment_id=None,
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label_id=None,
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line=".cfi_def_cfa w29, -16",
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line_number=3,
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)
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instruction_form_4 = InstructionForm(
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INSTRUCTION_ID="ldr",
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OPERANDS_ID=[
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RegisterOperand(PREFIX_ID="s", NAME_ID="0"),
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MemoryOperand(
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OFFSET_ID=None,
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BASE_ID=RegisterOperand(PREFIX_ID="x", NAME_ID="11"),
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INDEX_ID={
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instruction_form_4 = instructionForm(
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instruction_id="ldr",
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operands_id=[
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registerOperand(prefix_id="s", name_id="0"),
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memoryOperand(
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offset_ID=None,
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base_id=registerOperand(prefix_id="x", name_id="11"),
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index_id={
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"prefix": "w",
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"name": "10",
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"shift_op": "sxtw",
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"immediate": {"value": "2"},
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"shift": [{"value": "2"}],
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},
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SCALE_ID=4,
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scale_id=4,
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),
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],
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DIRECTIVE_ID=None,
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COMMENT_ID="= <<2",
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LABEL_ID=None,
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LINE="ldr s0, [x11, w10, sxtw #2] // = <<2",
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LINE_NUMBER=4,
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directive_id=None,
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comment_id="= <<2",
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label_id=None,
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line="ldr s0, [x11, w10, sxtw #2] // = <<2",
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line_number=4,
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)
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instruction_form_5 = InstructionForm(
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INSTRUCTION_ID="prfm",
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OPERANDS_ID=[
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instruction_form_5 = instructionForm(
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instruction_id="prfm",
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operands_id=[
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{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
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MemoryOperand(
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OFFSET_ID={"value": 2048},
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BASE_ID=RegisterOperand(PREFIX_ID="x", NAME_ID="26"),
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INDEX_ID=None,
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SCALE_ID=1,
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memoryOperand(
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offset_ID={"value": 2048},
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base_id=registerOperand(prefix_id="x", name_id="26"),
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index_id=None,
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scale_id=1,
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),
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],
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DIRECTIVE_ID=None,
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COMMENT_ID="HPL",
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LABEL_ID=None,
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LINE="prfm pldl1keep, [x26, #2048] //HPL",
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LINE_NUMBER=5,
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directive_id=None,
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comment_id="HPL",
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label_id=None,
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line="prfm pldl1keep, [x26, #2048] //HPL",
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line_number=5,
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)
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instruction_form_6 = InstructionForm(
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INSTRUCTION_ID="stp",
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OPERANDS_ID=[
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RegisterOperand(PREFIX_ID="x", NAME_ID="29"),
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RegisterOperand(PREFIX_ID="x", NAME_ID="30"),
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MemoryOperand(
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OFFSET_ID={"value": -16},
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BASE_ID=RegisterOperand(NAME_ID="sp", PREFIX_ID="x"),
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INDEX_ID=None,
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SCALE_ID=1,
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PRE_INDEXED=True,
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instruction_form_6 = instructionForm(
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instruction_id="stp",
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operands_id=[
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registerOperand(prefix_id="x", name_id="29"),
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registerOperand(prefix_id="x", name_id="30"),
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memoryOperand(
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offset_ID={"value": -16},
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base_id=registerOperand(name_id="sp", prefix_id="x"),
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index_id=None,
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scale_id=1,
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pre_indexed=True,
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),
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],
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DIRECTIVE_ID=None,
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COMMENT_ID=None,
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LABEL_ID=None,
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LINE="stp x29, x30, [sp, #-16]!",
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LINE_NUMBER=6,
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directive_id=None,
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comment_id=None,
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label_id=None,
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line="stp x29, x30, [sp, #-16]!",
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line_number=6,
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)
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instruction_form_7 = InstructionForm(
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INSTRUCTION_ID="ldp",
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OPERANDS_ID=[
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RegisterOperand(PREFIX_ID="q", NAME_ID="2"),
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RegisterOperand(PREFIX_ID="q", NAME_ID="3"),
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MemoryOperand(
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OFFSET_ID=None,
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BASE_ID=RegisterOperand(NAME_ID="11", PREFIX_ID="x"),
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INDEX_ID=None,
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SCALE_ID=1,
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POST_INDEXED={"value": 64},
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instruction_form_7 = instructionForm(
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instruction_id="ldp",
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operands_id=[
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registerOperand(prefix_id="q", name_id="2"),
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registerOperand(prefix_id="q", name_id="3"),
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memoryOperand(
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offset_ID=None,
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base_id=registerOperand(name_id="11", prefix_id="x"),
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index_id=None,
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scale_id=1,
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post_indexed={"value": 64},
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),
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],
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DIRECTIVE_ID=None,
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COMMENT_ID=None,
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LABEL_ID=None,
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LINE="ldp q2, q3, [x11], #64",
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LINE_NUMBER=7,
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directive_id=None,
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comment_id=None,
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label_id=None,
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line="ldp q2, q3, [x11], #64",
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line_number=7,
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)
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instruction_form_8 = InstructionForm(
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INSTRUCTION_ID="fcmla",
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OPERANDS_ID=[
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RegisterOperand(PREFIX_ID="z", NAME_ID="26", SHAPE="d"),
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RegisterOperand(PREFIX_ID="p", NAME_ID="0", PREDICATION="m"),
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RegisterOperand(PREFIX_ID="z", NAME_ID="29", SHAPE="d"),
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RegisterOperand(PREFIX_ID="z", NAME_ID="21", SHAPE="d"),
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ImmediateOperand(VALUE_ID=90, TYPE_ID="int"),
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instruction_form_8 = instructionForm(
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instruction_id="fcmla",
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operands_id=[
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registerOperand(prefix_id="z", name_id="26", shape="d"),
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registerOperand(prefix_id="p", name_id="0", predication="m"),
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registerOperand(prefix_id="z", name_id="29", shape="d"),
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registerOperand(prefix_id="z", name_id="21", shape="d"),
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immediateOperand(value_id=90, type_id="int"),
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],
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DIRECTIVE_ID=None,
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COMMENT_ID=None,
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LABEL_ID=None,
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LINE="fcmla z26.d, p0/m, z29.d, z21.d, #90",
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LINE_NUMBER=8,
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directive_id=None,
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comment_id=None,
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label_id=None,
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line="fcmla z26.d, p0/m, z29.d, z21.d, #90",
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line_number=8,
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)
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instruction_form_9 = InstructionForm(
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INSTRUCTION_ID="ccmn",
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OPERANDS_ID=[
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RegisterOperand(PREFIX_ID="x", NAME_ID="11"),
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ImmediateOperand(VALUE_ID=1, TYPE_ID="int"),
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ImmediateOperand(VALUE_ID=3, TYPE_ID="int"),
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instruction_form_9 = instructionForm(
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instruction_id="ccmn",
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operands_id=[
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registerOperand(prefix_id="x", name_id="11"),
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immediateOperand(value_id=1, type_id="int"),
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immediateOperand(value_id=3, type_id="int"),
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{"condition": "EQ"},
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],
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DIRECTIVE_ID=None,
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COMMENT_ID=None,
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LABEL_ID=None,
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LINE="ccmn x11, #1, #3, eq",
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LINE_NUMBER=9,
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directive_id=None,
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comment_id=None,
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label_id=None,
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line="ccmn x11, #1, #3, eq",
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line_number=9,
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)
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parsed_1 = self.parser.parse_line(line_comment, 1)
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@@ -372,17 +372,17 @@ class TestParserAArch64(unittest.TestCase):
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instr_list_with_index = "ld4 {v0.S, v1.S, v2.S, v3.S}[2]"
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instr_range_single = "dummy { z1.d }"
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reg_list = [
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RegisterOperand(PREFIX_ID="x", NAME_ID="5"),
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RegisterOperand(PREFIX_ID="x", NAME_ID="6"),
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RegisterOperand(PREFIX_ID="x", NAME_ID="7"),
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registerOperand(prefix_id="x", name_id="5"),
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registerOperand(prefix_id="x", name_id="6"),
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registerOperand(prefix_id="x", name_id="7"),
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]
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reg_list_idx = [
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RegisterOperand(PREFIX_ID="v", NAME_ID="0", SHAPE="S", INDEX=2),
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RegisterOperand(PREFIX_ID="v", NAME_ID="1", SHAPE="S", INDEX=2),
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RegisterOperand(PREFIX_ID="v", NAME_ID="2", SHAPE="S", INDEX=2),
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RegisterOperand(PREFIX_ID="v", NAME_ID="3", SHAPE="S", INDEX=2),
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registerOperand(prefix_id="v", name_id="0", shape="S", index=2),
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registerOperand(prefix_id="v", name_id="1", shape="S", index=2),
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registerOperand(prefix_id="v", name_id="2", shape="S", index=2),
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registerOperand(prefix_id="v", name_id="3", shape="S", index=2),
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]
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reg_list_single = [RegisterOperand(PREFIX_ID="z", NAME_ID="1", SHAPE="d")]
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reg_list_single = [registerOperand(prefix_id="z", name_id="1", shape="d")]
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prange = self.parser.parse_line(instr_range)
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plist = self.parser.parse_line(instr_list)
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@@ -397,22 +397,22 @@ class TestParserAArch64(unittest.TestCase):
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# self.assertEqual(p_single.operands, reg_list_single)
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def test_reg_dependency(self):
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reg_1_1 = RegisterOperand(PREFIX_ID="b", NAME_ID="1")
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reg_1_2 = RegisterOperand(PREFIX_ID="h", NAME_ID="1")
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reg_1_3 = RegisterOperand(PREFIX_ID="s", NAME_ID="1")
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reg_1_4 = RegisterOperand(PREFIX_ID="d", NAME_ID="1")
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reg_1_4 = RegisterOperand(PREFIX_ID="q", NAME_ID="1")
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reg_2_1 = RegisterOperand(PREFIX_ID="w", NAME_ID="2")
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reg_2_2 = RegisterOperand(PREFIX_ID="x", NAME_ID="2")
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reg_v1_1 = RegisterOperand(PREFIX_ID="v", NAME_ID="11", LANES="16", SHAPE="b")
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reg_v1_2 = RegisterOperand(PREFIX_ID="v", NAME_ID="11", LANES="8", SHAPE="h")
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reg_v1_3 = RegisterOperand(PREFIX_ID="v", NAME_ID="11", LANES="4", SHAPE="s")
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reg_v1_4 = RegisterOperand(PREFIX_ID="v", NAME_ID="11", LANES="2", SHAPE="d")
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reg_1_1 = registerOperand(prefix_id="b", name_id="1")
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reg_1_2 = registerOperand(prefix_id="h", name_id="1")
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reg_1_3 = registerOperand(prefix_id="s", name_id="1")
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reg_1_4 = registerOperand(prefix_id="d", name_id="1")
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reg_1_4 = registerOperand(prefix_id="q", name_id="1")
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reg_2_1 = registerOperand(prefix_id="w", name_id="2")
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reg_2_2 = registerOperand(prefix_id="x", name_id="2")
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reg_v1_1 = registerOperand(prefix_id="v", name_id="11", lanes="16", shape="b")
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reg_v1_2 = registerOperand(prefix_id="v", name_id="11", lanes="8", shape="h")
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reg_v1_3 = registerOperand(prefix_id="v", name_id="11", lanes="4", shape="s")
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reg_v1_4 = registerOperand(prefix_id="v", name_id="11", lanes="2", shape="d")
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reg_b5 = RegisterOperand(PREFIX_ID="b", NAME_ID="5")
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reg_q15 = RegisterOperand(PREFIX_ID="q", NAME_ID="15")
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reg_v10 = RegisterOperand(PREFIX_ID="v", NAME_ID="10", LANES="2", SHAPE="s")
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reg_v20 = RegisterOperand(PREFIX_ID="v", NAME_ID="20", LANES="2", SHAPE="d")
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reg_b5 = registerOperand(prefix_id="b", name_id="5")
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reg_q15 = registerOperand(prefix_id="q", name_id="15")
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reg_v10 = registerOperand(prefix_id="v", name_id="10", lanes="2", shape="s")
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reg_v20 = registerOperand(prefix_id="v", name_id="20", lanes="2", shape="d")
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reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
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reg_2 = [reg_2_1, reg_2_2]
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@@ -8,8 +8,8 @@ import unittest
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from pyparsing import ParseException
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from osaca.parser import ParserX86ATT, InstructionForm
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from osaca.parser.register import RegisterOperand
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from osaca.parser import ParserX86ATT, instructionForm
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from osaca.parser.register import registerOperand
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class TestParserX86ATT(unittest.TestCase):
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@@ -165,36 +165,36 @@ class TestParserX86ATT(unittest.TestCase):
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line_directive = ".quad .2.3_2__kmpc_loc_pack.2 #qed"
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line_instruction = "lea 2(%rax,%rax), %ecx #12.9"
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||||
|
||||
instruction_form_1 = InstructionForm(
|
||||
INSTRUCTION_ID=None,
|
||||
OPERANDS_ID=[],
|
||||
DIRECTIVE_ID=None,
|
||||
COMMENT_ID="-- Begin main",
|
||||
LABEL_ID=None,
|
||||
LINE="# -- Begin main",
|
||||
LINE_NUMBER=1,
|
||||
instruction_form_1 = instructionForm(
|
||||
instruction_id=None,
|
||||
operands_id=[],
|
||||
directive_id=None,
|
||||
comment_id="-- Begin main",
|
||||
label_id=None,
|
||||
line="# -- Begin main",
|
||||
line_number=1,
|
||||
)
|
||||
instruction_form_2 = InstructionForm(
|
||||
INSTRUCTION_ID=None,
|
||||
OPERANDS_ID=[],
|
||||
DIRECTIVE_ID=None,
|
||||
COMMENT_ID="Preds ..B1.6",
|
||||
LABEL_ID="..B1.7",
|
||||
LINE="..B1.7: # Preds ..B1.6",
|
||||
LINE_NUMBER=2,
|
||||
instruction_form_2 = instructionForm(
|
||||
instruction_id=None,
|
||||
operands_id=[],
|
||||
directive_id=None,
|
||||
comment_id="Preds ..B1.6",
|
||||
label_id="..B1.7",
|
||||
line="..B1.7: # Preds ..B1.6",
|
||||
line_number=2,
|
||||
)
|
||||
instruction_form_3 = InstructionForm(
|
||||
INSTRUCTION_ID=None,
|
||||
OPERANDS_ID=[],
|
||||
DIRECTIVE_ID={"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]},
|
||||
COMMENT_ID="qed",
|
||||
LABEL_ID=None,
|
||||
LINE=".quad .2.3_2__kmpc_loc_pack.2 #qed",
|
||||
LINE_NUMBER=3,
|
||||
instruction_form_3 = instructionForm(
|
||||
instruction_id=None,
|
||||
operands_id=[],
|
||||
directive_id={"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]},
|
||||
comment_id="qed",
|
||||
label_id=None,
|
||||
line=".quad .2.3_2__kmpc_loc_pack.2 #qed",
|
||||
line_number=3,
|
||||
)
|
||||
instruction_form_4 = InstructionForm(
|
||||
INSTRUCTION_ID="lea",
|
||||
OPERANDS_ID=[
|
||||
instruction_form_4 = instructionForm(
|
||||
instruction_id="lea",
|
||||
operands_id=[
|
||||
{
|
||||
"memory": {
|
||||
"offset": {"value": 2},
|
||||
@@ -205,11 +205,11 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
},
|
||||
{"register": {"name": "ecx"}},
|
||||
],
|
||||
DIRECTIVE_ID=None,
|
||||
COMMENT_ID="12.9",
|
||||
LABEL_ID=None,
|
||||
LINE="lea 2(%rax,%rax), %ecx #12.9",
|
||||
LINE_NUMBER=4,
|
||||
directive_id=None,
|
||||
comment_id="12.9",
|
||||
label_id=None,
|
||||
line="lea 2(%rax,%rax), %ecx #12.9",
|
||||
line_number=4,
|
||||
)
|
||||
|
||||
parsed_1 = self.parser.parse_line(line_comment, 1)
|
||||
@@ -233,10 +233,10 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
register_str_3 = "%xmm1"
|
||||
register_str_4 = "%rip"
|
||||
|
||||
parsed_reg_1 = RegisterOperand(NAME_ID="rax")
|
||||
parsed_reg_2 = RegisterOperand(NAME_ID="r9")
|
||||
parsed_reg_3 = RegisterOperand(NAME_ID="xmm1")
|
||||
parsed_reg_4 = RegisterOperand(NAME_ID="rip")
|
||||
parsed_reg_1 = registerOperand(name_id="rax")
|
||||
parsed_reg_2 = registerOperand(name_id="r9")
|
||||
parsed_reg_3 = registerOperand(name_id="xmm1")
|
||||
parsed_reg_4 = registerOperand(name_id="rip")
|
||||
|
||||
self.assertEqual(self.parser.parse_register(register_str_1), parsed_reg_1)
|
||||
self.assertEqual(self.parser.parse_register(register_str_2), parsed_reg_2)
|
||||
@@ -259,22 +259,22 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
)
|
||||
|
||||
def test_reg_dependency(self):
|
||||
reg_a1 = RegisterOperand(NAME_ID="rax")
|
||||
reg_a2 = RegisterOperand(NAME_ID="eax")
|
||||
reg_a3 = RegisterOperand(NAME_ID="ax")
|
||||
reg_a4 = RegisterOperand(NAME_ID="al")
|
||||
reg_r11 = RegisterOperand(NAME_ID="r11")
|
||||
reg_r11b = RegisterOperand(NAME_ID="r11b")
|
||||
reg_r11d = RegisterOperand(NAME_ID="r11d")
|
||||
reg_r11w = RegisterOperand(NAME_ID="r11w")
|
||||
reg_xmm1 = RegisterOperand(NAME_ID="xmm1")
|
||||
reg_ymm1 = RegisterOperand(NAME_ID="ymm1")
|
||||
reg_zmm1 = RegisterOperand(NAME_ID="zmm1")
|
||||
reg_a1 = registerOperand(name_id="rax")
|
||||
reg_a2 = registerOperand(name_id="eax")
|
||||
reg_a3 = registerOperand(name_id="ax")
|
||||
reg_a4 = registerOperand(name_id="al")
|
||||
reg_r11 = registerOperand(name_id="r11")
|
||||
reg_r11b = registerOperand(name_id="r11b")
|
||||
reg_r11d = registerOperand(name_id="r11d")
|
||||
reg_r11w = registerOperand(name_id="r11w")
|
||||
reg_xmm1 = registerOperand(name_id="xmm1")
|
||||
reg_ymm1 = registerOperand(name_id="ymm1")
|
||||
reg_zmm1 = registerOperand(name_id="zmm1")
|
||||
|
||||
reg_b1 = RegisterOperand(NAME_ID="rbx")
|
||||
reg_r15 = RegisterOperand(NAME_ID="r15")
|
||||
reg_xmm2 = RegisterOperand(NAME_ID="xmm2")
|
||||
reg_ymm3 = RegisterOperand(NAME_ID="ymm3")
|
||||
reg_b1 = registerOperand(name_id="rbx")
|
||||
reg_r15 = registerOperand(name_id="r15")
|
||||
reg_xmm2 = registerOperand(name_id="xmm2")
|
||||
reg_ymm3 = registerOperand(name_id="ymm3")
|
||||
|
||||
reg_a = [reg_a1, reg_a2, reg_a3, reg_a4]
|
||||
reg_r = [reg_r11, reg_r11b, reg_r11d, reg_r11w]
|
||||
|
||||
@@ -12,16 +12,16 @@ import networkx as nx
|
||||
from osaca.osaca import get_unmatched_instruction_ratio
|
||||
from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT
|
||||
from osaca.semantics import (
|
||||
INSTR_FLAGS,
|
||||
INSTR_flags,
|
||||
ArchSemantics,
|
||||
ISASemantics,
|
||||
KernelDG,
|
||||
MachineModel,
|
||||
reduce_to_section,
|
||||
)
|
||||
from osaca.parser.register import RegisterOperand
|
||||
from osaca.parser.memory import MemoryOperand
|
||||
from osaca.parser.identifier import IdentifierOperand
|
||||
from osaca.parser.register import registerOperand
|
||||
from osaca.parser.memory import memoryOperand
|
||||
from osaca.parser.identifier import identifierOperand
|
||||
|
||||
|
||||
class TestSemanticTools(unittest.TestCase):
|
||||
@@ -148,31 +148,31 @@ class TestSemanticTools(unittest.TestCase):
|
||||
self.assertIsNone(test_mm_arm.get_instruction("NOT_IN_DB", []))
|
||||
name_x86_1 = "vaddpd"
|
||||
operands_x86_1 = [
|
||||
RegisterOperand(NAME_ID="xmm"),
|
||||
RegisterOperand(NAME_ID="xmm"),
|
||||
RegisterOperand(NAME_ID="xmm"),
|
||||
registerOperand(name_id="xmm"),
|
||||
registerOperand(name_id="xmm"),
|
||||
registerOperand(name_id="xmm"),
|
||||
]
|
||||
instr_form_x86_1 = test_mm_x86.get_instruction(name_x86_1, operands_x86_1)
|
||||
self.assertEqual(instr_form_x86_1, test_mm_x86.get_instruction(name_x86_1, operands_x86_1))
|
||||
self.assertEqual(
|
||||
test_mm_x86.get_instruction("jg", [IdentifierOperand()]),
|
||||
test_mm_x86.get_instruction("jg", [IdentifierOperand()]),
|
||||
test_mm_x86.get_instruction("jg", [identifierOperand()]),
|
||||
test_mm_x86.get_instruction("jg", [identifierOperand()]),
|
||||
)
|
||||
name_arm_1 = "fadd"
|
||||
operands_arm_1 = [
|
||||
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
|
||||
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
|
||||
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
|
||||
registerOperand(prefix_id="v", shape="s"),
|
||||
registerOperand(prefix_id="v", shape="s"),
|
||||
registerOperand(prefix_id="v", shape="s"),
|
||||
]
|
||||
instr_form_arm_1 = test_mm_arm.get_instruction(name_arm_1, operands_arm_1)
|
||||
self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1))
|
||||
self.assertEqual(
|
||||
test_mm_arm.get_instruction("b.ne", [IdentifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.ne", [IdentifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.ne", [identifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.ne", [identifierOperand()]),
|
||||
)
|
||||
self.assertEqual(
|
||||
test_mm_arm.get_instruction("b.someNameThatDoesNotExist", [IdentifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.someOtherName", [IdentifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.someNameThatDoesNotExist", [identifierOperand()]),
|
||||
test_mm_arm.get_instruction("b.someOtherName", [identifierOperand()]),
|
||||
)
|
||||
|
||||
# test full instruction name
|
||||
@@ -189,8 +189,8 @@ class TestSemanticTools(unittest.TestCase):
|
||||
# test get_store_tp
|
||||
self.assertEqual(
|
||||
test_mm_x86.get_store_throughput(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
|
||||
memoryOperand(
|
||||
base_id=registerOperand(name_id="x"), offset_ID=None, index_id=None, scale_id=1
|
||||
)
|
||||
)[0].port_pressure,
|
||||
[[2, "237"], [2, "4"]],
|
||||
@@ -198,11 +198,11 @@ class TestSemanticTools(unittest.TestCase):
|
||||
|
||||
self.assertEqual(
|
||||
test_mm_x86.get_store_throughput(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"),
|
||||
OFFSET_ID=None,
|
||||
INDEX_ID="NOT_NONE",
|
||||
SCALE_ID=1,
|
||||
memoryOperand(
|
||||
base_id=registerOperand(prefix_id="NOT_IN_DB"),
|
||||
offset_ID=None,
|
||||
index_id="NOT_NONE",
|
||||
scale_id=1,
|
||||
)
|
||||
)[0].port_pressure,
|
||||
[[1, "23"], [1, "4"]],
|
||||
@@ -210,11 +210,11 @@ class TestSemanticTools(unittest.TestCase):
|
||||
|
||||
self.assertEqual(
|
||||
test_mm_arm.get_store_throughput(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(PREFIX_ID="x"),
|
||||
OFFSET_ID=None,
|
||||
INDEX_ID=None,
|
||||
SCALE_ID=1,
|
||||
memoryOperand(
|
||||
base_id=registerOperand(prefix_id="x"),
|
||||
offset_ID=None,
|
||||
index_id=None,
|
||||
scale_id=1,
|
||||
)
|
||||
)[0].port_pressure,
|
||||
[[2, "34"], [2, "5"]],
|
||||
@@ -222,11 +222,11 @@ class TestSemanticTools(unittest.TestCase):
|
||||
|
||||
self.assertEqual(
|
||||
test_mm_arm.get_store_throughput(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"),
|
||||
OFFSET_ID=None,
|
||||
INDEX_ID=None,
|
||||
SCALE_ID=1,
|
||||
memoryOperand(
|
||||
base_id=registerOperand(prefix_id="NOT_IN_DB"),
|
||||
offset_ID=None,
|
||||
index_id=None,
|
||||
scale_id=1,
|
||||
)
|
||||
)[0].port_pressure,
|
||||
[[1, "34"], [1, "5"]],
|
||||
@@ -234,19 +234,19 @@ class TestSemanticTools(unittest.TestCase):
|
||||
# test get_store_lt
|
||||
self.assertEqual(
|
||||
test_mm_x86.get_store_latency(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
|
||||
memoryOperand(
|
||||
base_id=registerOperand(name_id="x"), offset_ID=None, index_id=None, scale_id=1
|
||||
)
|
||||
),
|
||||
0,
|
||||
)
|
||||
self.assertEqual(
|
||||
test_mm_arm.get_store_latency(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(PREFIX_ID="x"),
|
||||
OFFSET_ID=None,
|
||||
INDEX_ID=None,
|
||||
SCALE_ID=1,
|
||||
memoryOperand(
|
||||
base_id=registerOperand(prefix_id="x"),
|
||||
offset_ID=None,
|
||||
index_id=None,
|
||||
scale_id=1,
|
||||
)
|
||||
),
|
||||
0,
|
||||
@@ -258,8 +258,8 @@ class TestSemanticTools(unittest.TestCase):
|
||||
# test default load tp
|
||||
self.assertEqual(
|
||||
test_mm_x86.get_load_throughput(
|
||||
MemoryOperand(
|
||||
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
|
||||
memoryOperand(
|
||||
base_id=registerOperand(name_id="x"), offset_ID=None, index_id=None, scale_id=1
|
||||
)
|
||||
)[0].port_pressure,
|
||||
[[1, "23"], [1, ["2D", "3D"]]],
|
||||
@@ -389,7 +389,7 @@ class TestSemanticTools(unittest.TestCase):
|
||||
dg.get_dependent_instruction_forms()
|
||||
# test dot creation
|
||||
dg.export_graph(filepath="/dev/null")
|
||||
|
||||
|
||||
def test_kernelDG_AArch64(self):
|
||||
dg = KernelDG(
|
||||
self.kernel_AArch64,
|
||||
@@ -421,7 +421,6 @@ class TestSemanticTools(unittest.TestCase):
|
||||
# test dot creation
|
||||
dg.export_graph(filepath="/dev/null")
|
||||
|
||||
|
||||
def test_kernelDG_SVE(self):
|
||||
KernelDG(
|
||||
self.kernel_aarch64_SVE,
|
||||
@@ -446,9 +445,9 @@ class TestSemanticTools(unittest.TestCase):
|
||||
semantics_hld.add_semantics(kernel_hld_2)
|
||||
semantics_hld.add_semantics(kernel_hld_3)
|
||||
|
||||
num_hidden_loads = len([x for x in kernel_hld if INSTR_FLAGS.HIDDEN_LD in x.flags])
|
||||
num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_FLAGS.HIDDEN_LD in x.flags])
|
||||
num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_FLAGS.HIDDEN_LD in x.flags])
|
||||
num_hidden_loads = len([x for x in kernel_hld if INSTR_flags.HIDDEN_LD in x.flags])
|
||||
num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_flags.HIDDEN_LD in x.flags])
|
||||
num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_flags.HIDDEN_LD in x.flags])
|
||||
self.assertEqual(num_hidden_loads, 1)
|
||||
self.assertEqual(num_hidden_loads_2, 0)
|
||||
self.assertEqual(num_hidden_loads_3, 1)
|
||||
@@ -463,7 +462,6 @@ class TestSemanticTools(unittest.TestCase):
|
||||
with self.assertRaises(NotImplementedError):
|
||||
dg.get_loopcarried_dependencies()
|
||||
|
||||
|
||||
def test_loop_carried_dependency_aarch64(self):
|
||||
dg = KernelDG(
|
||||
self.kernel_aarch64_memdep,
|
||||
@@ -513,7 +511,6 @@ class TestSemanticTools(unittest.TestCase):
|
||||
[(4, 1.0), (5, 1.0), (10, 1.0), (11, 1.0), (12, 1.0)],
|
||||
)
|
||||
|
||||
|
||||
def test_loop_carried_dependency_x86(self):
|
||||
lcd_id = "8"
|
||||
lcd_id2 = "5"
|
||||
@@ -571,8 +568,8 @@ class TestSemanticTools(unittest.TestCase):
|
||||
def test_is_read_is_written_x86(self):
|
||||
# independent form HW model
|
||||
dag = KernelDG(self.kernel_x86, self.parser_x86, None, None)
|
||||
reg_rcx = RegisterOperand(NAME_ID="rcx")
|
||||
reg_ymm1 = RegisterOperand(NAME_ID="ymm1")
|
||||
reg_rcx = registerOperand(name_id="rcx")
|
||||
reg_ymm1 = registerOperand(name_id="ymm1")
|
||||
|
||||
instr_form_r_c = self.parser_x86.parse_line("vmovsd %xmm0, (%r15,%rcx,8)")
|
||||
self.semantics_csx.assign_src_dst(instr_form_r_c)
|
||||
@@ -602,11 +599,11 @@ class TestSemanticTools(unittest.TestCase):
|
||||
def test_is_read_is_written_AArch64(self):
|
||||
# independent form HW model
|
||||
dag = KernelDG(self.kernel_AArch64, self.parser_AArch64, None, None)
|
||||
reg_x1 = RegisterOperand(PREFIX_ID="x", NAME_ID="1")
|
||||
reg_w1 = RegisterOperand(PREFIX_ID="w", NAME_ID="1")
|
||||
reg_d1 = RegisterOperand(PREFIX_ID="d", NAME_ID="1")
|
||||
reg_q1 = RegisterOperand(PREFIX_ID="q", NAME_ID="1")
|
||||
reg_v1 = RegisterOperand(PREFIX_ID="v", NAME_ID="1", LANES="2", SHAPE="d")
|
||||
reg_x1 = registerOperand(prefix_id="x", name_id="1")
|
||||
reg_w1 = registerOperand(prefix_id="w", name_id="1")
|
||||
reg_d1 = registerOperand(prefix_id="d", name_id="1")
|
||||
reg_q1 = registerOperand(prefix_id="q", name_id="1")
|
||||
reg_v1 = registerOperand(prefix_id="v", name_id="1", lanes="2", shape="d")
|
||||
regs = [reg_d1, reg_q1, reg_v1]
|
||||
regs_gp = [reg_w1, reg_x1]
|
||||
|
||||
@@ -671,11 +668,11 @@ class TestSemanticTools(unittest.TestCase):
|
||||
|
||||
def test_MachineModel_getter(self):
|
||||
sample_operands = [
|
||||
MemoryOperand(
|
||||
OFFSET_ID=None,
|
||||
BASE_ID=RegisterOperand(NAME_ID="r12"),
|
||||
INDEX_ID=RegisterOperand(NAME_ID="rcx"),
|
||||
SCALE_ID=8,
|
||||
memoryOperand(
|
||||
offset_ID=None,
|
||||
base_id=registerOperand(name_id="r12"),
|
||||
index_id=registerOperand(name_id="rcx"),
|
||||
scale_id=8,
|
||||
)
|
||||
]
|
||||
self.assertIsNone(self.machine_model_csx.get_instruction("GETRESULT", sample_operands))
|
||||
|
||||
Reference in New Issue
Block a user