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https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-04 18:20:09 +01:00
Changed style to conform to PEP-8 conventions; Added source and destination attributes to parent Operand class
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@@ -9,24 +9,24 @@ from io import StringIO
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import osaca.db_interface as dbi
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from osaca.db_interface import sanity_check
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from osaca.semantics import MachineModel
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from osaca.parser import InstructionForm
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser import instructionForm
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from osaca.parser.memory import memoryOperand
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from osaca.parser.register import registerOperand
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import copy
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class TestDBInterface(unittest.TestCase):
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@classmethod
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def setUpClass(self):
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sample_entry = InstructionForm(
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INSTRUCTION_ID="DoItRightAndDoItFast",
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OPERANDS_ID=[
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MemoryOperand(OFFSET_ID="imd", BASE_ID="gpr", INDEX_ID="gpr", SCALE_ID=8),
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RegisterOperand(NAME_ID="xmm"),
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sample_entry = instructionForm(
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instruction_id="DoItRightAndDoItFast",
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operands_id=[
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memoryOperand(offset_ID="imd", base_id="gpr", index_id="gpr", scale_id=8),
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registerOperand(name_id="xmm"),
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],
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THROUGHPUT=1.25,
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LATENCY=125,
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UOPS=6,
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throughput=1.25,
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latency=125,
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uops=6,
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)
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self.entry_csx = copy.copy(sample_entry)
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@@ -61,7 +61,7 @@ class TestDBInterface(unittest.TestCase):
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mm_csx.set_instruction_entry(self.entry_csx)
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mm_tx2.set_instruction_entry(self.entry_tx2)
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mm_zen1.set_instruction_entry(InstructionForm(INSTRUCTION_ID="empty_operation"))
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mm_zen1.set_instruction_entry(instructionForm(instruction_id="empty_operation"))
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num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx
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num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2
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@@ -72,7 +72,7 @@ class TestDBInterface(unittest.TestCase):
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self.assertEqual(num_entries_zen1, 1)
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def test_invalid_add(self):
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entry = InstructionForm()
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entry = instructionForm()
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# with self.assertRaises(KeyError):
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# MachineModel("csx").set_instruction_entry(entry)
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with self.assertRaises(TypeError):
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