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Refactor: RISC-V parser, code formatting, and flake8 compliance

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- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand.
- Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility.
- Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase.
- Improved docstrings and split long lines for better readability.
- Fixed test failures related to ImmediateOperand instantiation and attribute errors.
- Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64.
- Updated .gitignore and documentation as needed.
- Renamed example files for consistency (rv6 -> rv64).
This commit is contained in:
Metehan Dundar
2025-07-04 23:21:06 +02:00
parent 61b52dbf28
commit 1ceac6e9f3
47 changed files with 2368 additions and 787 deletions
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42
osaca/semantics/isa_semantics.py
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@@ -53,7 +53,11 @@ class ISASemantics(object):
instruction_form.check_normalized()
# if the instruction form doesn't have operands or is None, there's nothing to do
if instruction_form.operands is None or instruction_form.mnemonic is None:
instruction_form.semantic_operands = {"source": [], "destination": [], "src_dst": []}
instruction_form.semantic_operands = {
"source": [],
"destination": [],
"src_dst": [],
}
return
# check if instruction form is in ISA yaml, otherwise apply standard operand assignment
# (one dest, others source)
@@ -82,7 +86,9 @@ class ISASemantics(object):
if assign_default:
# no irregular operand structure, apply default
op_dict["source"] = self._parser.get_regular_source_operands(instruction_form)
op_dict["source"] = self._parser.get_regular_source_operands(
instruction_form
)
op_dict["destination"] = self._parser.get_regular_destination_operands(
instruction_form
)
@@ -105,7 +111,9 @@ class ISASemantics(object):
op_dict["src_dst"].append(reg)
# post-process pre- and post-indexing for aarch64 memory operands
if self._parser.isa() == "aarch64":
for operand in [op for op in op_dict["source"] if isinstance(op, MemoryOperand)]:
for operand in [
op for op in op_dict["source"] if isinstance(op, MemoryOperand)
]:
post_indexed = operand.post_indexed
pre_indexed = operand.pre_indexed
if (
@@ -117,7 +125,9 @@ class ISASemantics(object):
new_op.pre_indexed = pre_indexed
new_op.post_indexed = post_indexed
op_dict["src_dst"].append(new_op)
for operand in [op for op in op_dict["destination"] if isinstance(op, MemoryOperand)]:
for operand in [
op for op in op_dict["destination"] if isinstance(op, MemoryOperand)
]:
post_indexed = operand.post_indexed
pre_indexed = operand.pre_indexed
if (
@@ -170,7 +180,9 @@ class ISASemantics(object):
and o.base is not None
and isinstance(o.post_indexed, dict)
):
base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name
base_name = (
o.base.prefix if o.base.prefix is not None else ""
) + o.base.name
return {
base_name: {
"name": (o.base.prefix if o.base.prefix is not None else "")
@@ -181,7 +193,9 @@ class ISASemantics(object):
return {}
reg_operand_names = {} # e.g., {'rax': 'op1'}
operand_state = {} # e.g., {'op1': {'name': 'rax', 'value': 0}} 0 means unchanged
operand_state = (
{}
) # e.g., {'op1': {'name': 'rax', 'value': 0}} 0 means unchanged
for o in instruction_form.operands:
if isinstance(o, MemoryOperand) and o.pre_indexed:
@@ -192,10 +206,14 @@ class ISASemantics(object):
"This is currently not supprted.".format(instruction_form.line)
)
base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name
base_name = (
o.base.prefix if o.base.prefix is not None else ""
) + o.base.name
reg_operand_names = {base_name: "op1"}
if o.offset:
operand_state = {"op1": {"name": base_name, "value": o.offset.value}}
operand_state = {
"op1": {"name": base_name, "value": o.offset.value}
}
else:
# no offset (e.g., with Arm9 memops) -> base is updated
operand_state = {"op1": None}
@@ -239,7 +257,10 @@ class ISASemantics(object):
op_dict["src_dst"] = []
# handle dependency breaking instructions
if isa_data.breaks_dependency_on_equal_operands and operands[1:] == operands[:-1]:
if (
isa_data.breaks_dependency_on_equal_operands
and operands[1:] == operands[:-1]
):
op_dict["destination"] += operands
if isa_data.hidden_operands != []:
op_dict["destination"] += [hop for hop in isa_data.hidden_operands]
@@ -301,7 +322,8 @@ class ISASemantics(object):
def substitute_mem_address(self, operands):
"""Create memory wildcard for all memory operands"""
return [
self._create_reg_wildcard() if isinstance(op, MemoryOperand) else op for op in operands
self._create_reg_wildcard() if isinstance(op, MemoryOperand) else op
for op in operands
]
def _create_reg_wildcard(self):