diff --git a/osaca/data/a72/mapping_pmevo.json b/osaca/data/a72/mapping_pmevo.json
new file mode 100644
index 0000000..f1f97c4
--- /dev/null
+++ b/osaca/data/a72/mapping_pmevo.json
@@ -0,0 +1,401 @@
+{
+  "kind": "Mapping3",
+  "arch": {
+    "kind": "Architecture",
+    "ports": ["0", "1", "2", "3", "4", "5", "6"],
+    "name": "A72",
+    "insns": ["_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4", "_add_((REG:W:G:64)),_((REG:R:G:64)),_8", "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40", "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2", "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16", "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_clz_((REG:W:G:64)),_((REG:R:G:64))", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0", "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0", "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0", "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmn_((REG:R:G:64)),_#1", "_cmn_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3", "_cmp_((REG:R:G:64)),_624", "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))", "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]", "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4", "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49", "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fabs_((REG:W:F:32)),_((REG:R:F:32))", "_fabs_((REG:W:F:64)),_((REG:R:F:64))", "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmp_((REG:R:F:32)),_#0.0", "_fcmp_((REG:R:F:32)),_((REG:R:F:32))", "_fcmp_((REG:R:F:64)),_#0.0", "_fcmp_((REG:R:F:64)),_((REG:R:F:64))", "_fcmpe_((REG:R:F:32)),_#0.0", "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))", "_fcmpe_((REG:R:F:64)),_#0.0", "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))", "_fcvt_((REG:W:F:32)),_((REG:R:F:64))", "_fcvt_((REG:W:F:64)),_((REG:R:F:32))", "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s", "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))", "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmov_((REG:W:F:32)),_((REG:R:F:32))", "_fmov_((REG:W:F:32)),_2.0e+1", "_fmov_((REG:W:F:64)),_((REG:R:F:64))", "_fmov_((REG:W:F:64)),_((REG:W:G:64))", "_fmov_((REG:W:F:64)),_1.0e+1", "_fmov_((REG:W:F:VEC)).2d,_1.0e+0", "_fmov_((REG:W:F:VEC)).4s,_1.0e+0", "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]", "_fneg_((REG:W:F:32)),_((REG:R:F:32))", "_fneg_((REG:W:F:64)),_((REG:R:F:64))", "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_frinta_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:32)),_((REG:R:F:32))", "_frintm_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_frintp_((REG:W:F:32)),_((REG:R:F:32))", "_frintp_((REG:W:F:64)),_((REG:R:F:64))", "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_frintx_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:32)),_((REG:R:F:32))", "_frintz_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))", "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))", "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]", "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32", "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_mov_((REG:W:G:64)),_((REG:R:G:64))", "_mov_((REG:W:G:64)),_2147483647", "_movi_((REG:W:F:64)),_-256", "_movi_((REG:W:F:VEC)).16b,_0xdf", "_movi_((REG:W:F:VEC)).4s,_0", "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8", "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).8h,_0x53", "_movk_((REG:W:G:64)),_0x6c07,_lsl_16", "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6", "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8", "_mvni_((REG:W:F:VEC)).4s,_0", "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8", "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24", "_mvni_((REG:W:F:VEC)).8h,_0x40", "_neg_((REG:W:F:64)),_((REG:R:F:64))", "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_neg_((REG:W:G:64)),_((REG:R:G:64))", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2", "_negs_((REG:W:G:64)),_((REG:R:G:64))", "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296", "_rev_((REG:W:G:64)),_((REG:R:G:64))", "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14", "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32", "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32", "_scvtf_((REG:W:F:32)),_((REG:W:G:64))", "_scvtf_((REG:W:F:64)),_((REG:W:G:64))", "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3", "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3", "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10", "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5", "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b", "_tst_((REG:W:G:64)),_((REG:R:G:64))", "_tst_((REG:W:G:64)),_-3", "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6", "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2", "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63", "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19", "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h", "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h", "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h"]
+  },
+  "assignment": {
+    "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]],
+    "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]],
+    "_mov_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]],
+    "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4": [["2"]],
+    "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]],
+    "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2": [["0", "5"]],
+    "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]": [["4", "5"]],
+    "_frintm_((REG:W:F:64)),_((REG:R:F:64))": [["4"]],
+    "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]],
+    "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4", "5"]],
+    "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]],
+    "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]],
+    "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8": [["5"]],
+    "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24": [["5"]],
+    "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]],
+    "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3": [["2"]],
+    "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]],
+    "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]],
+    "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]],
+    "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824": [["0", "5"]],
+    "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_fabs_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_frintz_((REG:W:F:32)),_((REG:R:F:32))": [["4"]],
+    "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6": [["2"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3": [["2"]],
+    "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]],
+    "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]": [["4", "5"]],
+    "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7": [["0", "5"]],
+    "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["5"]],
+    "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["6"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_8": [["0", "5"]],
+    "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]],
+    "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]],
+    "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fneg_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_negs_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_rev_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0": [["5"]],
+    "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8": [["5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]],
+    "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2": [["2"]],
+    "_fcmp_((REG:R:F:32)),_((REG:R:F:32))": [["6"]],
+    "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]],
+    "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]],
+    "_fcvt_((REG:W:F:64)),_((REG:R:F:32))": [["4"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]],
+    "_fcmpe_((REG:R:F:32)),_#0.0": [["6"]],
+    "_fmov_((REG:W:G:64)),_((REG:W:F:64))": [["1"]],
+    "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9": [["2"]],
+    "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3": [["2"]],
+    "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]],
+    "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296": [["0", "5"]],
+    "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]],
+    "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]],
+    "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]],
+    "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]],
+    "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]],
+    "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]],
+    "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb": [["2"]],
+    "_tst_((REG:W:G:64)),_-3": [["0", "5"]],
+    "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4"]],
+    "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3": [["2"]],
+    "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]],
+    "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3": [["2"]],
+    "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmp_((REG:R:G:64)),_624": [["0", "5"]],
+    "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0": [["4", "5"]],
+    "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fmov_((REG:W:F:32)),_2.0e+1": [["4", "5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2": [["2"]],
+    "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]],
+    "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]],
+    "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]],
+    "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))": [["4"], ["4"], ["4"]],
+    "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]],
+    "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_movi_((REG:W:F:64)),_-256": [["4", "5"]],
+    "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h": [["5"]],
+    "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]],
+    "_fmov_((REG:W:F:64)),_((REG:W:G:64))": [["1"]],
+    "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10": [["6"]],
+    "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["4"]],
+    "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_movk_((REG:W:G:64)),_0x6c07,_lsl_16": [["0", "5"]],
+    "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]],
+    "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]],
+    "_mvni_((REG:W:F:VEC)).4s,_0": [["5"]],
+    "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2": [["2"]],
+    "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40": [["0", "5"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]],
+    "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_neg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s": [["4", "5"]],
+    "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]],
+    "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]],
+    "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_movi_((REG:W:F:VEC)).16b,_0xdf": [["5"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]],
+    "_fabs_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))": [["4"]],
+    "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["6"]],
+    "_neg_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5": [["2"]],
+    "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]],
+    "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]],
+    "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))": [["4"]],
+    "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]],
+    "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0": [["5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]],
+    "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["2"], ["2"], ["2"], ["2"]],
+    "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]],
+    "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]],
+    "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]],
+    "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32": [["0", "5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]],
+    "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18": [["2"]],
+    "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]],
+    "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]],
+    "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))": [["5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]],
+    "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]],
+    "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]],
+    "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fmov_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19": [["6"]],
+    "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]],
+    "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]],
+    "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fmov_((REG:W:F:VEC)).4s,_1.0e+0": [["5"]],
+    "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2": [["2"]],
+    "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))": [["4"]],
+    "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]],
+    "_fcmp_((REG:R:F:32)),_#0.0": [["6"]],
+    "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s": [["4", "5"]],
+    "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]],
+    "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]],
+    "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]],
+    "_mvn_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]],
+    "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4", "5"]],
+    "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_frintx_((REG:W:F:64)),_((REG:R:F:64))": [["4"]],
+    "_frintm_((REG:W:F:32)),_((REG:R:F:32))": [["4"]],
+    "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]],
+    "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]],
+    "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8": [["5"]],
+    "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4"]],
+    "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]],
+    "_frintp_((REG:W:F:64)),_((REG:R:F:64))": [["4"]],
+    "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]],
+    "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32": [["0", "5"]],
+    "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]],
+    "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["0"], ["0"], ["0"]],
+    "_fcmp_((REG:R:F:64)),_((REG:R:F:64))": [["6"]],
+    "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]],
+    "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"], ["6"]],
+    "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]],
+    "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8": [["2"]],
+    "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["0"], ["0"]],
+    "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]],
+    "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmn_((REG:R:G:64)),_#1": [["0", "5"]],
+    "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d": [["4", "5"]],
+    "_movi_((REG:W:F:VEC)).4s,_0": [["5"]],
+    "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]],
+    "_fcvt_((REG:W:F:32)),_((REG:R:F:64))": [["4"]],
+    "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30": [["2"]],
+    "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8": [["5"]],
+    "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]],
+    "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]],
+    "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]],
+    "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]],
+    "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]],
+    "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]],
+    "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]],
+    "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]],
+    "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]],
+    "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]],
+    "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2": [["0", "5"]],
+    "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h": [["4", "5"]],
+    "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]],
+    "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_scvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]],
+    "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]],
+    "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]],
+    "_fmov_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]],
+    "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16": [["2"]],
+    "_fcmp_((REG:R:F:64)),_#0.0": [["6"]],
+    "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]],
+    "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]],
+    "_movi_((REG:W:F:VEC)).8h,_0x53": [["5"]],
+    "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]": [["5"]],
+    "_fmov_((REG:W:F:64)),_1.0e+1": [["4", "5"]],
+    "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14": [["0", "5"]],
+    "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"], ["6"]],
+    "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b": [["0"], ["0"]],
+    "_scvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]],
+    "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]],
+    "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))": [["6"]],
+    "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]],
+    "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]": [["5"]],
+    "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]],
+    "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]],
+    "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]],
+    "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]],
+    "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h": [["4", "5"]],
+    "_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"]],
+    "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s": [["4"]],
+    "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6": [["0", "5"]],
+    "_fmov_((REG:W:F:VEC)).2d,_1.0e+0": [["5"]],
+    "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8": [["4", "5"]],
+    "_mvni_((REG:W:F:VEC)).8h,_0x40": [["5"]],
+    "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]],
+    "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]],
+    "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))": [["4"], ["4"], ["4"], ["4"], ["4"]],
+    "_frinta_((REG:W:F:64)),_((REG:R:F:64))": [["4"]],
+    "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648": [["0", "5"]],
+    "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]],
+    "_fneg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]],
+    "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]],
+    "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]],
+    "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63": [["6"]],
+    "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]],
+    "_cmn_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11": [["2"]],
+    "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32": [["0", "5"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3": [["2"]],
+    "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]],
+    "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]],
+    "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_fcmpe_((REG:R:F:64)),_#0.0": [["6"]],
+    "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_frintz_((REG:W:F:64)),_((REG:R:F:64))": [["4"]],
+    "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]],
+    "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0": [["4", "5"]],
+    "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]],
+    "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]],
+    "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["1"]],
+    "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]],
+    "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]],
+    "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49": [["2"]],
+    "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]],
+    "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]],
+    "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_frintp_((REG:W:F:32)),_((REG:R:F:32))": [["4"]],
+    "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]],
+    "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]],
+    "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]],
+    "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]],
+    "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]],
+    "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]],
+    "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4", "5"]],
+    "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1": [["0", "5"]],
+    "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]],
+    "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]],
+    "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]],
+    "_tst_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]],
+    "_mov_((REG:W:G:64)),_2147483647": [["0", "5"]],
+    "_clz_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]],
+    "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]],
+    "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]],
+    "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]],
+    "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))": [["6"]]
+  }
+}
diff --git a/osaca/data/a72/template.yml b/osaca/data/a72/template.yml
new file mode 100644
index 0000000..8a47f1e
--- /dev/null
+++ b/osaca/data/a72/template.yml
@@ -0,0 +1,808 @@
+osaca_version: 0.3.11
+micro_architecture: Cortex A-72
+arch_code: a72
+isa: aarch64
+hidden_loads: false
+ports: ['0', '1', '2', '3', '4', '5', '6', '7']
+port_model_scheme: |
+  +-------------------------------------------------------------------------------------+
+  |                                      scheduler                                      |
+  +-------------------------------------------------------------------------------------+
+    0 |I      1 |L       2 |M     3 |S        4 |F1       5 |I       6 |F0      7 |B
+      \/        \/         \/       \/          \/          \/         \/         \/
+   +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+
+   |INT ALU| |  LOAD | |  MUL  | | STORE | |   ASIMD   | |INT ALU| |  ASIMD  | | Branch|
+   +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+
+   +-------+           +-------+           +-----------+ +-------+ +---------+
+   |  AGU  |           |  DIV  |           |   FP ALU  | |  AGU  | |ASIMD MUL|
+   +-------+           +-------+           +-----------+ +-------+ +---------+
+                       +-------+           +-----------+           +---------+
+                       | SHIFT |           |   FP MUL  |           |  FP ALU |
+                       +-------+           +-----------+           +---------+
+                       +-------+           +-----------+           +---------+
+                       |  CRC  |           |   FP DIV  |           |  FP MUL |
+                       +-------+           +-----------+           +---------+
+                       +-------+           +-----------+           +---------+
+                       |  USAD |           |  FP SQRT  |           |  FP DIV |
+                       +-------+           +-----------+           +---------+
+                                           +-----------+           +---------+
+                                           |ASIMD SHIFT|           | FP CONV |
+                                           +-----------+           +---------+
+                                                                   +---------+
+                                                                   |  CRYPTO |
+                                                                   +---------+
+# The port pressues do not always correctly match this schema, because most
+# instructions are imported from an experimentally determined mapping, which
+# is not always correct.
+load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0}
+load_throughput: []
+load_throughput_default: [[1, '1']]
+store_throughput: []
+store_throughput_default: [[2, '3']]
+instruction_forms:
+
+# Branch
+- name: b
+  operands:
+  - class: identifier
+  latency: 1.0
+  port_pressure: [[1, '7']]
+  throughput: 1.0
+- name: bne
+  operands:
+  - class: identifier
+  latency: 1.0
+  port_pressure: [[1, '7']]
+  throughput: 1.0
+- name: b.ne
+  operands:
+  - class: identifier
+  latency: 1.0
+  port_pressure: [[1, '7']]
+  throughput: 1.0
+- name: br
+  operands:
+  - class: register
+    prefix: x
+  latency: 1.0
+  port_pressure: [[1, '7']]
+  throughput: 1.0
+- name: ret
+  operands:
+  - class: register
+    prefix: x
+  latency: 1.0
+  port_pressure: [[1, '7']]
+  throughput: 1.0
+- name: bl
+  operands:
+  - class: identifier
+  latency: 1.0
+  port_pressure: [[1, '05'], [1, '7']]
+  throughput: 1.0
+- name: blr
+  operands:
+  - class: register
+    prefix: x
+  latency: 1.0
+  port_pressure: [[1, '05'], [1, '7']]
+  throughput: 1.0
+
+# Load GPR
+- name: ldr
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 5.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 5.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+
+# Load FP d
+- name: ldr
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 5.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 5.0
+  port_pressure: [[1, '1'], [2, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 5.0
+  port_pressure: [[1, '1'], [2, '05']]
+  throughput: 1.0
+
+# Load FP q
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: false
+    pre-indexed: false
+  latency: 5.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: true
+    pre-indexed: false
+  latency: 5.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: false
+    pre-indexed: true
+  latency: 5.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 6.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 6.0
+  port_pressure: [[1, '1'], [2, '05']]
+  throughput: 1.0
+- name: ldr
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 6.0
+  port_pressure: [[1, '1'], [2, '05']]
+  throughput: 1.0
+
+# Store GPR
+- name: str
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 1.0
+  port_pressure: [[1, '3']]
+  throughput: 1.0
+- name: str
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 1.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+- name: str
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 1.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+
+# Store FP d
+- name: str
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 1.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+- name: str
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 1.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+- name: str
+  operands:
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 1.0
+  port_pressure: [[1, '3'], [1, '05']]
+  throughput: 1.0
+
+# Store FP q
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: false
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[2, '3']]
+  throughput: 2.0
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: true
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[2, '3'], [1, '05']]
+  throughput: 2.0
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: 1
+    post-indexed: false
+    pre-indexed: true
+  latency: 2.0
+  port_pressure: [[2, '3'], [1, '05']]
+  throughput: 2.0
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[2, '3'], [1, '05']]
+  throughput: 2.0
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[2, '3'], [2, '05']]
+  throughput: 2.0
+- name: str
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 4.0
+  port_pressure: [[2, '3'], [2, '05']]
+  throughput: 2.0
+
+# Load unscaled GPR
+- name: ldur
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: '*'
+    pre-indexed: '*'
+  latency: 4.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+
+# Load unscaled FP q
+- name: ldur
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: '*'
+    pre-indexed: '*'
+  latency: 5.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+
+# Store unscaled GPR
+- name: stur
+  operands:
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: '*'
+    pre-indexed: '*'
+  latency: 1.0
+  port_pressure: [[1, '3']]
+  throughput: 1.0
+
+# Store unscaled FP q
+- name: stur
+  operands:
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: '*'
+    pre-indexed: '*'
+  latency: 2.0
+  port_pressure: [[2, '3']]
+  throughput: 2.0
+
+# Load pair GPR
+- name: ldp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[1, '1']]
+  throughput: 1.0
+- name: ldp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+- name: ldp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 4.0
+  port_pressure: [[1, '1'], [1, '05']]
+  throughput: 1.0
+
+# Load pair FP q
+- name: ldp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 6.0
+  port_pressure: [[2, '1']]
+  throughput: 2.0
+- name: ldp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 6.0
+  port_pressure: [[2, '1'], [1, '05']]
+  throughput: 2.0
+- name: ldp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 6.0
+  port_pressure: [[2, '1'], [1, '05']]
+  throughput: 2.0
+
+# Store pair GPR
+- name: stp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 2.0
+  port_pressure: [[2, '3']]
+  throughput: 2.0
+- name: stp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 2.0
+  port_pressure: [[2, '3'], [1, '05']]
+  throughput: 2.0
+- name: stp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 2.0
+  port_pressure: [[2, '3'], [1, '05']]
+  throughput: 2.0
+
+# Store pair FP q
+- name: stp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[4, '3'], [1, '05']]
+  throughput: 4.0
+- name: stp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: true
+    pre-indexed: false
+  latency: 4.0
+  port_pressure: [[4, '3'], [1, '05']]
+  throughput: 4.0
+- name: stp
+  operands:
+  - class: register
+    prefix: q
+  - class: register
+    prefix: q
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: true
+  latency: 4.0
+  port_pressure: [[4, '3'], [1, '05']]
+  throughput: 4.0
+
+# Fast-forward (measures 4 cycles, but can be 3)
+# Lower bound is used in order to ensure no over-estimates are possible.
+# Ports do not match documentation, but "fixing" requires also "fixing" almost
+# the entire rest of the model.
+- name: fadd
+  operands:
+  - class: register
+    prefix: s
+  - class: register
+    prefix: s
+  - class: register
+    prefix: s
+  latency: 3.0
+  port_pressure: [[1, '45']]
+  throughput: 0.5
+- name: fadd
+  operands:
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  latency: 3.0
+  port_pressure: [[1, '45']]
+  throughput: 0.5
+- name: fadd
+  operands:
+  - class: register
+    prefix: v
+    shape: s
+  - class: register
+    prefix: v
+    shape: s
+  - class: register
+    prefix: v
+    shape: s
+  latency: 3.0
+  port_pressure: [[1, '5']]
+  throughput: 1.0
+- name: fadd
+  operands:
+  - class: register
+    prefix: v
+    shape: d
+  - class: register
+    prefix: v
+    shape: d
+  - class: register
+    prefix: v
+    shape: d
+  latency: 3.0
+  port_pressure: [[1, '5']]
+  throughput: 1.0
+- name: fsub
+  operands:
+  - class: register
+    prefix: s
+  - class: register
+    prefix: s
+  - class: register
+    prefix: s
+  latency: 3.0
+  port_pressure: [[1, '45']]
+  throughput: 0.5
+- name: fsub
+  operands:
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  latency: 3.0
+  port_pressure: [[1, '45']]
+  throughput: 0.5
+- name: fsub
+  operands:
+  - class: register
+    prefix: v
+    shape: s
+  - class: register
+    prefix: v
+    shape: s
+  - class: register
+    prefix: v
+    shape: s
+  latency: 3.0
+  port_pressure: [[1, '5']]
+  throughput: 1.0
+- name: fsub
+  operands:
+  - class: register
+    prefix: v
+    shape: d
+  - class: register
+    prefix: v
+    shape: d
+  - class: register
+    prefix: v
+    shape: d
+  latency: 3.0
+  port_pressure: [[1, '5']]
+  throughput: 1.0
+
+# Automatically generated instructions