From dc250bcedcff15a0fb090eff3abd398696c1f5fa Mon Sep 17 00:00:00 2001 From: JanLJL Date: Thu, 28 Sep 2023 10:04:15 +0200 Subject: [PATCH 1/3] initial commit of M1 model (not complete) --- osaca/data/m1.yml | 1951 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1951 insertions(+) create mode 100644 osaca/data/m1.yml diff --git a/osaca/data/m1.yml b/osaca/data/m1.yml new file mode 100644 index 0000000..c551e0a --- /dev/null +++ b/osaca/data/m1.yml @@ -0,0 +1,1951 @@ +osaca_version: 0.5.2 +micro_architecture: Apple M1 Firestorm +arch_code: m1 +isa: AArch64 +ROB_size: 623 #https://dougallj.github.io/applecpu/firestorm.html +retired_uOps_per_cycle: 8 +scheduler_size: 326 #https://dougallj.github.io/applecpu/firestorm.html +hidden_loads: false +load_latency: {w: 3.0, x: 3.0, b: 3.0, h: 3.0, s: 3.0, d: 3.0, q: 3.0, v: 3.0} +p_index_latency: 1 +load_throughput: +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '467']]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} +load_throughput_default: [[1, '467']] +store_throughput: +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '45']]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} +store_throughput_default: [[1, '45']] +ports: ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13'] +port_model_scheme: | + +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ + | 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 | + +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ + 0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5 + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ + | ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | + +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ + +------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ + | MUL | | MUL | | MUL | | MUL | | ST | | AGU | | AGU | | AGU | | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT| + +------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ + +------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ + | FMA | | FMA | | FMA | | FMA | | AGU | | BR | | BR | | FLAGS| |MOV FP| | MUL | | MUL | + +------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ + +------+ +------+ +------+ +------+ +------+ +------+ + | FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA | + +------+ +------+ +------+ +------+ +------+ +------+ + +------+ +------+ + | 2INT | | 2INT | + +------+ +------+ + +------+ + | RCP | + +------+ + +------+ + | SHA | + +------+ +instruction_forms: +- name: [adc, adcs] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: adds + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: adds + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: adr + operands: + - class: register + prefix: '*' + - class: identifier + throughput: 0.5 + latency: ~ # 1*p89 + port_pressure: [[1, '89']] +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: asr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [asr, asrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: asr + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, bal, b.al, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq] + operands: + - class: identifier + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '89']] +- name: [bfi, bfm] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 1.0 + latency: 1.0 # 1*p13 + port_pressure: [[1, ['13']]] +- name: bic + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: bics + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: bic + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: bics + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [cls, clz] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [cls, clz] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: cmp + operands: + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: cmp + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.3333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [eon, eor] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [eon, eor] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: eor + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: [lsl, lslv, lsr, lsrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [lsl, lslv, lsr, lsrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: madd # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 1.0 + latency: 3.0 # 1*,13 NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! + port_pressure: [[1, ['13']]] +- name: [msub, mneg] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: mul + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: neg + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: neg + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [negs, ngc, ngcs] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [orn, orr] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [orn, orr] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [orn, orr] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [orn, orr] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [rbit, rev, rev16, rev32] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [rbit, rev, rev16, rev32] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: ror + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [ror, rorv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: [sbc, sbcs] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [sbfiz, sbfm, sbfx] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: sdiv + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 7.0 + latency: 2.0 # 2*p12DV + port_pressure: [[2, ['12']]] +- name: [smaddl, smsubl, umaddl, umsubl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: x + throughput: 1.0 + latency: 3.0 # 1*p13 + port_pressure: [[1, ['13']]] +- name: [smnegl, umnegl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: [smull, smulh, umulh, umull] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: subs + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: subs + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: sxtb + operands: + - class: register + prefix: x + - class: register + prefix: w + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [uxtb, uxth] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] + + + + +- name: + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0. + latency: 1.0 # 1*p0123 + port_pressure: [[1, '0123']] + + +- name: fadd + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fadd + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fdiv + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 1.0 + latency: 10.0 # 1*p3 + port_pressure: [[1, '3']] +- name: fdiv + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 1.0 + latency: 10.0 # 1*p3 + port_pressure: [[1, '3']] +- name: fdiv + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 1.0 + latency: 8.0 # 1*p3 + port_pressure: [[1, '3']] +- name: fdiv + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + throughput: 1.0 + latency: 8.0 # 1*p3 + port_pressure: [[1, '3']] +- name: fmla + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] +- name: fmla + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] +- name: fmov + operands: + - {class: register, prefix: s} + - {class: immediate, imd: double} + latency: ~ # 1*p45 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: fmul + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.5 + latency: 3.0 # 1*p45 + port_pressure: [[1, '45']] +- name: fmul + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.5 + latency: 3.0 # 1*p45 + port_pressure: [[1, '45']] +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.5 + latency: 3.0 # 1*p45 + port_pressure: [[1, '45']] +- name: frecpe + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 2.0 + latency: 4.0 # 1*p4 + port_pressure: [[2, '4']] +- name: frecpe + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 1.0 + latency: 3.0 # 1*p4 + port_pressure: [[1, '4']] +- name: fsub + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] +- name: fsub + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] +- name: mov + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p45 + port_pressure: [[1, '45']] + + From c5ef5f74322bc03ece56aad2c52d173f101fe0e6 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Tue, 12 Dec 2023 18:32:43 +0100 Subject: [PATCH 2/3] bugfixes for SP reg and ccodes --- osaca/data/isa/aarch64.yml | 4 ++-- osaca/parser/parser_AArch64.py | 10 +++++++--- osaca/semantics/hw_model.py | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/osaca/data/isa/aarch64.yml b/osaca/data/isa/aarch64.yml index 73c6223..7cd82a3 100644 --- a/osaca/data/isa/aarch64.yml +++ b/osaca/data/isa/aarch64.yml @@ -850,7 +850,7 @@ instruction_forms: shape: "*" source: true destination: false - - name: ldp + - name: [ldp, ldnp] operands: - class: register prefix: "*" @@ -895,7 +895,7 @@ instruction_forms: source: true destination: false operation: "op1['name'] = op2['name']; op1['value'] = op2['value']" - - name: stp + - name: [stp, stnp] operands: - class: register prefix: "*" diff --git a/osaca/parser/parser_AArch64.py b/osaca/parser/parser_AArch64.py index 30dd9d6..9464443 100755 --- a/osaca/parser/parser_AArch64.py +++ b/osaca/parser/parser_AArch64.py @@ -382,7 +382,7 @@ class ParserAArch64(BaseParser): ): # resolve ranges and lists return self.resolve_range_list(self.process_register_list(operand[self.REGISTER_ID])) - if self.REGISTER_ID in operand and operand[self.REGISTER_ID]["name"] == "sp": + if self.REGISTER_ID in operand and operand[self.REGISTER_ID]["name"].lower() == "sp": return self.process_sp_register(operand[self.REGISTER_ID]) # add value attribute to floating point immediates without exponent if self.IMMEDIATE_ID in operand: @@ -404,9 +404,13 @@ class ParserAArch64(BaseParser): base = memory_address.get("base", None) index = memory_address.get("index", None) scale = 1 - if base is not None and "name" in base and base["name"] == "sp": + if base is not None and "name" in base and base["name"].lower() == "sp": base["prefix"] = "x" - if index is not None and "name" in index and index["name"] == "sp": + if index is not None and "name" in index and index["name"].lower() == "sp": + index["prefix"] = "x" + if base is not None and "name" in base and base["name"].lower() == "zr": + base["prefix"] = "x" + if index is not None and "name" in index and index["name"].lower() == "zr": index["prefix"] = "x" valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"] if "index" in memory_address: diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index 6b84538..e03db3c 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -589,7 +589,7 @@ class MachineModel(object): return i_operand["class"] == "prfop" # condition if "condition" in operand: - if i_operand["ccode"] == self.WILDCARD: + if i_operand["class"] == "condition" and i_operand["ccode"] == self.WILDCARD: return True return i_operand["class"] == "condition" and ( operand.get("condition", None) == i_operand.get("ccode", None).upper() From f3b50b93f590c82b24497b2ab575255e257a362a Mon Sep 17 00:00:00 2001 From: JanLJL Date: Tue, 12 Dec 2023 18:33:24 +0100 Subject: [PATCH 3/3] added M1 arch --- README.rst | 2 +- osaca/data/m1.yml | 2293 ++++++++++++++++++++++++++++++++--- osaca/osaca.py | 3 +- osaca/semantics/hw_model.py | 1 + 4 files changed, 2146 insertions(+), 153 deletions(-) diff --git a/README.rst b/README.rst index d0ff0e6..080c392 100644 --- a/README.rst +++ b/README.rst @@ -101,7 +101,7 @@ The usage of OSACA can be listed as: --arch ARCH needs to be replaced with the target architecture abbreviation. Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures. - Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, and ``A64FX`` for Fujitsu's HPC ARM architecture are available. + Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available. If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64. --fixed Run the throughput analysis with fixed port utilization for all suitable ports per instruction. diff --git a/osaca/data/m1.yml b/osaca/data/m1.yml index c551e0a..229737b 100644 --- a/osaca/data/m1.yml +++ b/osaca/data/m1.yml @@ -18,7 +18,7 @@ store_throughput: - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} store_throughput_default: [[1, '45']] -ports: ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13'] +ports: ['0', '1', '2', '3', '3DV', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13'] port_model_scheme: | +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ | 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 | @@ -143,7 +143,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: asr +- name: and operands: - class: register prefix: x @@ -151,9 +151,9 @@ instruction_forms: prefix: x - class: immediate imd: int - throughput: 0.16666666 - latency: 1.0 # 1*p89,10,11,12,13 - port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: and operands: - class: register @@ -165,6 +165,50 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.2 + latency: 1.0 # 1*p89,10,12,13 + port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: ands + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.3333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: ands + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.3333333 + latency: 1.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: asr operands: - class: register @@ -204,6 +248,17 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '89']] +- name: bfc + operands: + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 1.0 + latency: 1.0 # 1*p13 + port_pressure: [[1, ['13']]] - name: [bfi, bfm] operands: - class: register @@ -807,6 +862,520 @@ instruction_forms: throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 3.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p467 + port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [lsl, lslv, lsr, lsrv] operands: - class: register @@ -829,7 +1398,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: madd # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! +- name: [madd, msub] # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! operands: - class: register prefix: '*' @@ -842,7 +1411,7 @@ instruction_forms: throughput: 1.0 latency: 3.0 # 1*,13 NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! port_pressure: [[1, ['13']]] -- name: [msub, mneg] +- name: mneg operands: - class: register prefix: '*' @@ -911,6 +1480,15 @@ instruction_forms: throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] +- name: mvn + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: neg operands: - class: register @@ -938,6 +1516,11 @@ instruction_forms: throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] +- name: nop + operands: [] + throughput: 0.16666666 + latency: ~ # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [orn, orr] operands: - class: register @@ -988,8 +1571,6 @@ instruction_forms: prefix: x - class: register prefix: x - - class: register - prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] @@ -999,11 +1580,27 @@ instruction_forms: prefix: w - class: register prefix: w - - class: register - prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] +- name: ret + operands: [] + throughput: 0.0 + latency: ~ + port_pressure: [] +- name: ret + operands: + - class: immediate + imd: int + throughput: 0.0 + latency: ~ + port_pressure: [] +- name: ret + operands: + - class: identifier + throughput: 0.0 + latency: ~ + port_pressure: [] - name: ror operands: - class: register @@ -1021,6 +1618,8 @@ instruction_forms: prefix: '*' - class: register prefix: '*' + - class: register + prefix: '*' throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] @@ -1048,6 +1647,46 @@ instruction_forms: throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: s + - class: register + prefix: w + throughput: 0.33333333 + latency: 4.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d + - class: register + prefix: x + throughput: 0.33333333 + latency: 4.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.33333333 + latency: 4.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: s + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.33333333 + latency: 4.0 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] - name: sdiv operands: - class: register @@ -1083,7 +1722,18 @@ instruction_forms: throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] -- name: [smull, smulh, umulh, umull] +- name: [smulh, umulh] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 3.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: [smull, umull] operands: - class: register prefix: x @@ -1562,6 +2212,522 @@ instruction_forms: throughput: 0.5 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 2*p45 + port_pressure: [[2, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 2*p467 + port_pressure: [[2, '467'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45']] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p45 + port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: sub operands: - class: register @@ -1659,6 +2825,30 @@ instruction_forms: throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [ubfiz, ubfm, ubfx] + operands: + - class: register + prefix: "*" + - class: register + prefix: "*" + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: udiv + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 7.0 + latency: 2.0 # 2*p12DV + port_pressure: [[2, ['12']]] - name: [uxtb, uxth] operands: - class: register @@ -1668,24 +2858,571 @@ instruction_forms: throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - - - - -- name: +- name: fabs operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 1.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fabs + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fadd + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcmp, fcmpe] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 1.0 + latency: 1.0 # 1*p3 + port_pressure: [[1, '3']] +- name: [fccmp, fccmpe] # LT assumed from fcmp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: immediate + imd: int + - class: condition + ccode: "*" + throughput: 1.0 + latency: 1.0 # 1*p3 + port_pressure: [[1, '3']] +- name: fcvt + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: h + - class: register + prefix: h + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: s + - class: register + prefix: s + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.5 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtzs, fcvtzu] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.5 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fdiv + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 1.0 + latency: 10.0 # 1*p3 + port_pressure: [[1, '3'], [1, ['3DV']]] +- name: fdiv + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 1.0 + latency: 10.0 # 1*p3 + port_pressure: [[1, '3'], [1, ['3DV']]] +- name: fdiv + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 1.0 + latency: 8.0 # 1*p3 + port_pressure: [[1, '3'], [1, ['3DV']]] +- name: fdiv + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + throughput: 1.0 + latency: 8.0 # 1*p3 + port_pressure: [[1, '3'], [1, ['3DV']]] +- name: [fmadd, fnmadd] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fmax, fmaxnm, fmin, fminnm] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fmov + operands: + - class: register + prefix: '*' + - class: immediate + imd: '*' + latency: ~ # 1*p0123 + port_pressure: [[1, '0123']] + throughput: 0.25 +- name: fmov + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 2.5 # 1*p23 + port_pressure: [[1, '23']] + throughput: 0.5 +- name: fmov + operands: + - class: register + prefix: w + - class: register + prefix: s + latency: 2.5 # 1*p23 + port_pressure: [[1, '23']] + throughput: 0.5 +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 2.5 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] + throughput: 0.33333333 +- name: fmov + operands: + - class: register + prefix: s + - class: register + prefix: w + latency: 2.5 # 1*p89,10 + port_pressure: [[1, ['8', '9', '10']]] + throughput: 0.33333333 +- name: fmov + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] + throughput: 0.25 +- name: [fmsub, fnmsub] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] + throughput: 0.25 +- name: [fmul, fnmul] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fneg + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fsqrt + operands: + - class: register + prefix: s + - class: register + prefix: s + throughput: 2 + latency: 10.0 # 1*p3+2*p3DV + port_pressure: [[1, '3'], [2, ['3DV']]] +- name: fsqrt + operands: + - class: register + prefix: d + - class: register + prefix: d + throughput: 2 + latency: 13.0 # 1*p3+2*p3DV + port_pressure: [[1, '3'], [2, ['3DV']]] +- name: fsub + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: abs + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: add + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: addp + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: and + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: bic + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: bic + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [bif, bit, bsl] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p23 + port_pressure: [[1, '23']] +- name: [cls, clz] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] + operands: + - class: register + prefix: v + shape: '*' + width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int - throughput: 0. - latency: 1.0 # 1*p0123 + throughput: 0.25 + latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - - -- name: fadd +- name: cnt + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: eor + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: dup + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: dup # LT from scvt + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: x + throughput: 0.33333333 + latency: 4.0 # 1*p0123+1*p89,10 + port_pressure: [[1, '0123'], [1, ['8', '9', '10']]] +- name: ext + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fabd operands: - class: register prefix: v @@ -1700,167 +3437,292 @@ instruction_forms: shape: '*' width: '*' throughput: 0.25 - latency: 3.0 # 1*p0123 + latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] -- name: fadd +- name: fabs operands: - class: register - prefix: '*' + prefix: v + shape: '*' + width: '*' - class: register - prefix: '*' - - class: register - prefix: '*' + prefix: v + shape: '*' + width: '*' throughput: 0.25 - latency: 3.0 # 1*p0123 + latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] -- name: fdiv +- name: [facge, facgt] operands: - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - throughput: 1.0 - latency: 10.0 # 1*p3 - port_pressure: [[1, '3']] -- name: fdiv - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: register - prefix: d - throughput: 1.0 - latency: 10.0 # 1*p3 - port_pressure: [[1, '3']] -- name: fdiv + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: faddp operands: - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - throughput: 1.0 - latency: 8.0 # 1*p3 - port_pressure: [[1, '3']] -- name: fdiv - operands: - - class: register - prefix: s - - class: register - prefix: s - - class: register - prefix: s - throughput: 1.0 - latency: 8.0 # 1*p3 - port_pressure: [[1, '3']] -- name: fmla + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fcadd operands: - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fcmla + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] -- name: fmla + latency: 4.0 # 1*p0123 + port_pressure: [[1, '23']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - - class: register - prefix: v - shape: d - width: '*' - throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] -- name: fmov - operands: - - {class: register, prefix: s} - - {class: immediate, imd: double} - latency: ~ # 1*p45 - port_pressure: [[1, '45']] - throughput: 0.5 -- name: fmul + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - - class: register - prefix: v - shape: s - width: '*' - throughput: 0.5 - latency: 3.0 # 1*p45 - port_pressure: [[1, '45']] -- name: fmul + - class: immediate + imd: int + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fmax, fmaxnm, fmaxnmp, fmaxp] operands: - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - throughput: 0.5 - latency: 3.0 # 1*p45 - port_pressure: [[1, '45']] -- name: fmul + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fmin, fminnm, fminnmp, fminp] operands: - class: register - prefix: d + prefix: v + shape: '*' + width: '*' - class: register - prefix: d + prefix: v + shape: '*' + width: '*' - class: register - prefix: d - throughput: 0.5 - latency: 3.0 # 1*p45 - port_pressure: [[1, '45']] + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fmla, fmls] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [fmul, fmulx] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fneg + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] - name: frecpe operands: - class: register prefix: v - shape: s + shape: '*' width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 1.0 + latency: 3.0 # 1*p3 + port_pressure: [[1, '3']] +- name: frecps + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 2.0 + latency: 13.0 # 1*p3+2*p3DV + port_pressure: [[1, '3'], [2, ['3DV']]] +- name: fsqrt + operands: - class: register prefix: v shape: s @@ -1870,82 +3732,211 @@ instruction_forms: shape: s width: '*' throughput: 2.0 - latency: 4.0 # 1*p4 - port_pressure: [[2, '4']] -- name: frecpe + latency: 10.0 # 1*p3+2*p3DV + port_pressure: [[1, '3'], [2, ['3DV']]] +- name: frsqrte operands: - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d - width: '*' - - class: register - prefix: v - shape: d + shape: '*' width: '*' throughput: 1.0 - latency: 3.0 # 1*p4 - port_pressure: [[1, '4']] -- name: fsub + latency: 3.0 # 1*p3 + port_pressure: [[1, '3']] +- name: frsqrts operands: - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - class: register prefix: v - shape: s + shape: '*' width: '*' - throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] -- name: fsub + throughput: 0.25 + latency: 4.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [mla, mls] operands: - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] - name: mov operands: - class: register prefix: v - shape: b + shape: '*' width: '*' - class: register prefix: v - shape: b + shape: '*' width: '*' - throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] -- name: dup + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: mul operands: - class: register - prefix: d + prefix: v + shape: '*' + width: '*' - class: register prefix: v - shape: d + shape: '*' width: '*' - throughput: 0.5 - latency: 2.0 # 1*p45 - port_pressure: [[1, '45']] - - + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: mvn + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: neg + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: not + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [orn, orr] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: pmul + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: rbit + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: [rev16, rev32, rev64] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: rev64 + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: saba + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p0123 + port_pressure: [[1, '0123']] diff --git a/osaca/osaca.py b/osaca/osaca.py index 51d46b6..60f7b58 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -38,6 +38,7 @@ SUPPORTED_ARCHS = [ "A64FX", "TSV110", "A72", + "M1", ] DEFAULT_ARCHS = { "aarch64": "A64FX", @@ -101,7 +102,7 @@ def create_parser(parser=None): "--arch", type=str, help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, " - "A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", + "A64FX, TSV110, A72, M1). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", ) parser.add_argument( "--fixed", diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index e03db3c..19b0230 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -281,6 +281,7 @@ class MachineModel(object): "a72": "aarch64", "tx2": "aarch64", "n1": "aarch64", + "m1": "aarch64", "zen1": "x86", "zen+": "x86", "zen2": "x86",