diff --git a/.github/workflows/test-n-publish.yml b/.github/workflows/test-n-publish.yml index 77783e6..808852b 100644 --- a/.github/workflows/test-n-publish.yml +++ b/.github/workflows/test-n-publish.yml @@ -22,7 +22,8 @@ jobs: python -m pip install bs4 sudo apt-get -y install graphviz libgraphviz-dev pkg-config python -m pip install pygraphviz - python -m pip install kerncraft + #python -m pip install kerncraft + python -m pip install git+https://github.com/RRZE-HPC/kerncraft.git@InstrucForm python -m pip install -e . - name: Test run: | diff --git a/osaca/__init__.py b/osaca/__init__.py index 3c345c8..ec58fc2 100644 --- a/osaca/__init__.py +++ b/osaca/__init__.py @@ -1,4 +1,5 @@ """Open Source Architecture Code Analyzer""" + name = "osaca" __version__ = "0.5.3" diff --git a/osaca/data/a64fx.yml b/osaca/data/a64fx.yml index fb56507..8fdac0b 100644 --- a/osaca/data/a64fx.yml +++ b/osaca/data/a64fx.yml @@ -9,19 +9,19 @@ hidden_loads: false load_latency: {w: 5.0, x: 5.0, b: 5.0, h: 5.0, s: 5.0, d: 8.0, q: 8.0, v: 8.0, z: 11.0} #load_throughput_multiplier: {w: 1.0, x: 1.0, b: 1.0, h: 1.0, s: 1.0, d: 1.0, q: 1.0, v: 2.0, z: 2.0} load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']]]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '56'], [1, ['5D', '6D']], [1, '3456']]} load_throughput_default: [[1, '56'], [1, ['5D', '6D']]] store_throughput: [] store_throughput_default: [[1, '5'], [1, '6']] @@ -1072,8 +1072,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1090,8 +1090,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1108,8 +1108,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1126,8 +1126,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1144,8 +1144,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1162,8 +1162,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1180,8 +1180,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1198,8 +1198,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1216,8 +1216,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1234,8 +1234,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1252,8 +1252,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1270,8 +1270,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1288,8 +1288,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1306,8 +1306,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1324,8 +1324,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1342,8 +1342,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1360,8 +1360,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1378,8 +1378,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1396,8 +1396,8 @@ instruction_forms: offset: '*' index: ~ scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1414,8 +1414,8 @@ instruction_forms: offset: '*' index: x scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 8.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1432,8 +1432,8 @@ instruction_forms: offset: ~ index: z scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[1, '0'],[1, '3'],[4, '56'], [4, ['5D', '6D']]] # not sure if we also have 4 data accesses @@ -1453,8 +1453,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 11.0 # 1*p0+1*p3+4*p56+1*p5D6D port_pressure: [[2, '56'], [4, ['5D', '6D']]] @@ -1469,8 +1469,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D port_pressure: [[2, '56'], [2, ['5D', '6D']]] @@ -1485,8 +1485,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1501,8 +1501,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1517,8 +1517,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D port_pressure: [[2, '56'], [2, ['5D', '6D']]] @@ -1533,8 +1533,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1549,8 +1549,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1565,8 +1565,8 @@ instruction_forms: offset: ~ index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1581,8 +1581,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D port_pressure: [[2, '56'], [2, ['5D', '6D']]] @@ -1597,8 +1597,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 8.0 # 2*p56+2*p5D6D+1*p0234 port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']] @@ -1611,8 +1611,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1625,8 +1625,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p56+1*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1648,8 +1648,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 1.0 latency: 11.0 # 1*p5+1*p5D port_pressure: [[1, '56'], [2, ['5D','6D']]] @@ -1662,8 +1662,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 2*p56+2*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1676,8 +1676,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 2*p56+2*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1690,8 +1690,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 2*p56+2*p5D6D port_pressure: [[1, '56'], [1, ['5D', '6D']]] @@ -1751,8 +1751,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 1.0 latency: 11.0 # 1*p56+2*p5D6D port_pressure: [[1, '56'], [2, ['5D','6D']]] @@ -1982,8 +1982,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 port_pressure: [[1, '56']] @@ -2000,8 +2000,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 port_pressure: [[1, '56']] @@ -2016,8 +2016,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 port_pressure: [[1, '56']] @@ -2075,8 +2075,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p56+2*p0 port_pressure: [[2, '5'], [2,'6'], [2, '0']] @@ -2091,8 +2091,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 # 2*p56+2*p0+1*0234 port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']] @@ -2107,8 +2107,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p56+2*p0 port_pressure: [[2, '5'], [2,'6'], [2, '0']] @@ -2123,8 +2123,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 # 2*p56+2*p0+1*0234 port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']] @@ -2139,8 +2139,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p56+2*p0 port_pressure: [[2, '5'], [2,'6'], [2, '0']] @@ -2155,8 +2155,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 2.0 latency: 0 # 2*p56+2*p0+1*0234 port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']] @@ -2171,8 +2171,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 # 2*p56+2*p0+1*0234 port_pressure: [[2, '5'], [2,'6'], [2, '0'], [1, '0234']] @@ -2187,8 +2187,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p56+2*p0 port_pressure: [[2, '5'], [2,'6'], [2, '0']] @@ -2201,8 +2201,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2215,8 +2215,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2229,8 +2229,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2243,8 +2243,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2257,8 +2257,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2271,8 +2271,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0+1*p0234 port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']] @@ -2285,8 +2285,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p56+1*p0+1*p0234 port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']] @@ -2299,8 +2299,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p56+1*p0 port_pressure: [[1, '5'], [1,'6'], [1, '0']] @@ -2313,8 +2313,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p56+1*p0+1*0234 port_pressure: [[1, '5'], [1,'6'], [1, '0'], [1, '0234']] @@ -2327,8 +2327,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p56+1*p3+1*p0234 port_pressure: [[1, '5'], [1,'6'], [1, '3'], [1, '0234']] @@ -2341,8 +2341,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p5+1*p6+1*p0 port_pressure: [[1, '5'], [1, '6'], [1, '0']] @@ -2358,8 +2358,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p5+1*p6+1*p0 port_pressure: [[1, '5'], [1, '6'], [1, '0']] @@ -2379,8 +2379,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p5+1*p6+1*p0 port_pressure: [[1, '5'], [1, '6'], [1, '0']] @@ -2395,8 +2395,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 1.0 latency: 11.0 # 1*p56+2*p5D6D port_pressure: [[1, '5'], [1, ['6']], [1, '0']] diff --git a/osaca/data/a72.yml b/osaca/data/a72.yml index caef68c..274f721 100644 --- a/osaca/data/a72.yml +++ b/osaca/data/a72.yml @@ -95,8 +95,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -109,8 +109,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -123,8 +123,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -139,8 +139,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -153,8 +153,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -167,8 +167,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -183,8 +183,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -197,8 +197,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -211,8 +211,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -225,8 +225,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 6.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -239,8 +239,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 6.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -253,8 +253,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 6.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -269,8 +269,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '3']] throughput: 1.0 @@ -283,8 +283,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -297,8 +297,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -313,8 +313,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -327,8 +327,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -341,8 +341,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -357,8 +357,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -371,8 +371,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -385,8 +385,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -399,8 +399,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -413,8 +413,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [2, '05']] throughput: 2.0 @@ -427,8 +427,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[2, '3'], [2, '05']] throughput: 2.0 @@ -443,8 +443,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -459,8 +459,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -475,8 +475,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 1.0 port_pressure: [[1, '3']] throughput: 1.0 @@ -491,8 +491,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 2.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -509,8 +509,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -525,8 +525,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -541,8 +541,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -559,8 +559,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 6.0 port_pressure: [[2, '1']] throughput: 2.0 @@ -575,8 +575,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 6.0 port_pressure: [[2, '1'], [1, '05']] throughput: 2.0 @@ -591,8 +591,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 6.0 port_pressure: [[2, '1'], [1, '05']] throughput: 2.0 @@ -609,8 +609,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 2.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -625,8 +625,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -641,8 +641,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -659,8 +659,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 @@ -675,8 +675,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 @@ -691,8 +691,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 @@ -2564,8 +2564,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -2579,8 +2579,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -2594,8 +2594,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -2609,8 +2609,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -3495,8 +3495,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 2.0 port_pressure: [[2, '3']] throughput: 2.0 diff --git a/osaca/data/a72/mapping_pmevo.json b/osaca/data/a72/mapping_pmevo.json index f1f97c4..30cf194 100644 --- a/osaca/data/a72/mapping_pmevo.json +++ b/osaca/data/a72/mapping_pmevo.json @@ -1,401 +1,401 @@ { - "kind": "Mapping3", - "arch": { - "kind": "Architecture", - "ports": ["0", "1", "2", "3", "4", "5", "6"], - "name": "A72", - "insns": ["_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4", "_add_((REG:W:G:64)),_((REG:R:G:64)),_8", "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40", "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2", "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16", "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_clz_((REG:W:G:64)),_((REG:R:G:64))", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0", "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0", "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0", "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmn_((REG:R:G:64)),_#1", "_cmn_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3", "_cmp_((REG:R:G:64)),_624", "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))", "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]", "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4", "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49", "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fabs_((REG:W:F:32)),_((REG:R:F:32))", "_fabs_((REG:W:F:64)),_((REG:R:F:64))", "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmp_((REG:R:F:32)),_#0.0", "_fcmp_((REG:R:F:32)),_((REG:R:F:32))", "_fcmp_((REG:R:F:64)),_#0.0", "_fcmp_((REG:R:F:64)),_((REG:R:F:64))", "_fcmpe_((REG:R:F:32)),_#0.0", "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))", "_fcmpe_((REG:R:F:64)),_#0.0", "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))", "_fcvt_((REG:W:F:32)),_((REG:R:F:64))", "_fcvt_((REG:W:F:64)),_((REG:R:F:32))", "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s", "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))", "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmov_((REG:W:F:32)),_((REG:R:F:32))", "_fmov_((REG:W:F:32)),_2.0e+1", "_fmov_((REG:W:F:64)),_((REG:R:F:64))", "_fmov_((REG:W:F:64)),_((REG:W:G:64))", "_fmov_((REG:W:F:64)),_1.0e+1", "_fmov_((REG:W:F:VEC)).2d,_1.0e+0", "_fmov_((REG:W:F:VEC)).4s,_1.0e+0", "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]", "_fneg_((REG:W:F:32)),_((REG:R:F:32))", "_fneg_((REG:W:F:64)),_((REG:R:F:64))", "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_frinta_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:32)),_((REG:R:F:32))", "_frintm_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_frintp_((REG:W:F:32)),_((REG:R:F:32))", "_frintp_((REG:W:F:64)),_((REG:R:F:64))", "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_frintx_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:32)),_((REG:R:F:32))", "_frintz_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))", "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))", "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]", "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32", "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_mov_((REG:W:G:64)),_((REG:R:G:64))", "_mov_((REG:W:G:64)),_2147483647", "_movi_((REG:W:F:64)),_-256", "_movi_((REG:W:F:VEC)).16b,_0xdf", "_movi_((REG:W:F:VEC)).4s,_0", "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8", "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).8h,_0x53", "_movk_((REG:W:G:64)),_0x6c07,_lsl_16", "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6", "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8", "_mvni_((REG:W:F:VEC)).4s,_0", "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8", "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24", "_mvni_((REG:W:F:VEC)).8h,_0x40", "_neg_((REG:W:F:64)),_((REG:R:F:64))", "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_neg_((REG:W:G:64)),_((REG:R:G:64))", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2", "_negs_((REG:W:G:64)),_((REG:R:G:64))", "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296", "_rev_((REG:W:G:64)),_((REG:R:G:64))", "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14", "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32", "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32", "_scvtf_((REG:W:F:32)),_((REG:W:G:64))", "_scvtf_((REG:W:F:64)),_((REG:W:G:64))", "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3", "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3", "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10", "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5", "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b", "_tst_((REG:W:G:64)),_((REG:R:G:64))", "_tst_((REG:W:G:64)),_-3", "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6", "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2", "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63", "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19", "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h", "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h", "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h"] - }, - "assignment": { - "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], - "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], - "_mov_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], - "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], - "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4": [["2"]], - "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], - "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2": [["0", "5"]], - "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]": [["4", "5"]], - "_frintm_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], - "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], - "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4", "5"]], - "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], - "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], - "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], - "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], - "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8": [["5"]], - "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24": [["5"]], - "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], - "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3": [["2"]], - "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], - "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], - "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], - "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], - "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824": [["0", "5"]], - "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], - "_fabs_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_frintz_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], - "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6": [["2"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3": [["2"]], - "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], - "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]": [["4", "5"]], - "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7": [["0", "5"]], - "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["5"]], - "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["6"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_8": [["0", "5"]], - "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], - "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]], - "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_fneg_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_negs_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_rev_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0": [["5"]], - "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8": [["5"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], - "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], - "_fcmp_((REG:R:F:32)),_((REG:R:F:32))": [["6"]], - "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]], - "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]], - "_fcvt_((REG:W:F:64)),_((REG:R:F:32))": [["4"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], - "_fcmpe_((REG:R:F:32)),_#0.0": [["6"]], - "_fmov_((REG:W:G:64)),_((REG:W:F:64))": [["1"]], - "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9": [["2"]], - "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3": [["2"]], - "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]], - "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296": [["0", "5"]], - "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]], - "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], - "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], - "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]], - "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], - "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], - "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], - "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb": [["2"]], - "_tst_((REG:W:G:64)),_-3": [["0", "5"]], - "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4"]], - "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3": [["2"]], - "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], - "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3": [["2"]], - "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_cmp_((REG:R:G:64)),_624": [["0", "5"]], - "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0": [["4", "5"]], - "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_fmov_((REG:W:F:32)),_2.0e+1": [["4", "5"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], - "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], - "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], - "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], - "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))": [["4"], ["4"], ["4"]], - "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]], - "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_movi_((REG:W:F:64)),_-256": [["4", "5"]], - "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h": [["5"]], - "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], - "_fmov_((REG:W:F:64)),_((REG:W:G:64))": [["1"]], - "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10": [["6"]], - "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["4"]], - "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], - "_movk_((REG:W:G:64)),_0x6c07,_lsl_16": [["0", "5"]], - "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], - "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], - "_mvni_((REG:W:F:VEC)).4s,_0": [["5"]], - "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2": [["2"]], - "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40": [["0", "5"]], - "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], - "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_neg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s": [["4", "5"]], - "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], - "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]], - "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], - "_movi_((REG:W:F:VEC)).16b,_0xdf": [["5"]], - "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]], - "_fabs_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], - "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], - "_neg_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], - "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5": [["2"]], - "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], - "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], - "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], - "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], - "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0": [["5"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], - "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["2"], ["2"], ["2"], ["2"]], - "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]], - "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]], - "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], - "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]], - "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32": [["0", "5"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]], - "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18": [["2"]], - "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], - "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], - "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))": [["5"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], - "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], - "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], - "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], - "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_fmov_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], - "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19": [["6"]], - "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - 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"_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_frintz_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], - "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], - "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0": [["4", "5"]], - "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], - "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]], - "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["1"]], - "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], - "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], - "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49": [["2"]], - "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], - "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], - "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_frintp_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], - "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], - "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], - "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], - "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], - "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], - "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], - "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4", "5"]], - "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1": [["0", "5"]], - "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], - "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], - "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], - "_tst_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]], - "_mov_((REG:W:G:64)),_2147483647": [["0", "5"]], - "_clz_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], - "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], - "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]], - "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], - "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))": [["6"]] - } -} + "kind": "Mapping3", + "arch": { + "kind": "Architecture", + "ports": ["0", "1", "2", "3", "4", "5", "6"], + "name": "A72", + "insns": ["_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4", "_add_((REG:W:G:64)),_((REG:R:G:64)),_8", "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40", "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2", "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16", "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_clz_((REG:W:G:64)),_((REG:R:G:64))", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0", "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0", "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0", "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmn_((REG:R:G:64)),_#1", "_cmn_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3", "_cmp_((REG:R:G:64)),_624", "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))", "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]", "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4", "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49", "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fabs_((REG:W:F:32)),_((REG:R:F:32))", "_fabs_((REG:W:F:64)),_((REG:R:F:64))", "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmp_((REG:R:F:32)),_#0.0", "_fcmp_((REG:R:F:32)),_((REG:R:F:32))", "_fcmp_((REG:R:F:64)),_#0.0", "_fcmp_((REG:R:F:64)),_((REG:R:F:64))", "_fcmpe_((REG:R:F:32)),_#0.0", "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))", "_fcmpe_((REG:R:F:64)),_#0.0", "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))", "_fcvt_((REG:W:F:32)),_((REG:R:F:64))", "_fcvt_((REG:W:F:64)),_((REG:R:F:32))", "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s", "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))", "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmov_((REG:W:F:32)),_((REG:R:F:32))", "_fmov_((REG:W:F:32)),_2.0e+1", "_fmov_((REG:W:F:64)),_((REG:R:F:64))", "_fmov_((REG:W:F:64)),_((REG:W:G:64))", "_fmov_((REG:W:F:64)),_1.0e+1", "_fmov_((REG:W:F:VEC)).2d,_1.0e+0", "_fmov_((REG:W:F:VEC)).4s,_1.0e+0", "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]", "_fneg_((REG:W:F:32)),_((REG:R:F:32))", "_fneg_((REG:W:F:64)),_((REG:R:F:64))", "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_frinta_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:32)),_((REG:R:F:32))", "_frintm_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_frintp_((REG:W:F:32)),_((REG:R:F:32))", "_frintp_((REG:W:F:64)),_((REG:R:F:64))", "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_frintx_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:32)),_((REG:R:F:32))", "_frintz_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))", "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))", "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]", "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32", "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_mov_((REG:W:G:64)),_((REG:R:G:64))", "_mov_((REG:W:G:64)),_2147483647", "_movi_((REG:W:F:64)),_-256", "_movi_((REG:W:F:VEC)).16b,_0xdf", "_movi_((REG:W:F:VEC)).4s,_0", "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8", "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).8h,_0x53", "_movk_((REG:W:G:64)),_0x6c07,_lsl_16", "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6", "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8", "_mvni_((REG:W:F:VEC)).4s,_0", "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8", "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24", "_mvni_((REG:W:F:VEC)).8h,_0x40", "_neg_((REG:W:F:64)),_((REG:R:F:64))", "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_neg_((REG:W:G:64)),_((REG:R:G:64))", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2", "_negs_((REG:W:G:64)),_((REG:R:G:64))", "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296", "_rev_((REG:W:G:64)),_((REG:R:G:64))", "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14", "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32", "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32", "_scvtf_((REG:W:F:32)),_((REG:W:G:64))", "_scvtf_((REG:W:F:64)),_((REG:W:G:64))", "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3", "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3", "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10", "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5", "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b", "_tst_((REG:W:G:64)),_((REG:R:G:64))", "_tst_((REG:W:G:64)),_-3", "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6", "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2", "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63", "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19", "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h", "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h", "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h"] + }, + "assignment": { + "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], + "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_mov_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4": [["2"]], + "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2": [["0", "5"]], + "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]": [["4", "5"]], + "_frintm_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4", "5"]], + "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8": [["5"]], + "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24": [["5"]], + "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], + "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3": [["2"]], + "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], + "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824": [["0", "5"]], + "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_fabs_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_frintz_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3": [["2"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]": [["4", "5"]], + "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7": [["0", "5"]], + "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["5"]], + "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_8": [["0", "5"]], + "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], + "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]], + "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fneg_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_negs_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_rev_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0": [["5"]], + "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], + "_fcmp_((REG:R:F:32)),_((REG:R:F:32))": [["6"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]], + "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]], + "_fcvt_((REG:W:F:64)),_((REG:R:F:32))": [["4"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_fcmpe_((REG:R:F:32)),_#0.0": [["6"]], + "_fmov_((REG:W:G:64)),_((REG:W:F:64))": [["1"]], + "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9": [["2"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3": [["2"]], + "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]], + "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296": [["0", "5"]], + "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]], + "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], + "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]], + "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], + "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb": [["2"]], + "_tst_((REG:W:G:64)),_-3": [["0", "5"]], + "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4"]], + "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3": [["2"]], + "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3": [["2"]], + "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_624": [["0", "5"]], + "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0": [["4", "5"]], + "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:32)),_2.0e+1": [["4", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], + "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], + "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))": [["4"], ["4"], ["4"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]], + "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_movi_((REG:W:F:64)),_-256": [["4", "5"]], + "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h": [["5"]], + "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_fmov_((REG:W:F:64)),_((REG:W:G:64))": [["1"]], + "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10": [["6"]], + "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["4"]], + "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_movk_((REG:W:G:64)),_0x6c07,_lsl_16": [["0", "5"]], + "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], + "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], + "_mvni_((REG:W:F:VEC)).4s,_0": [["5"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2": [["2"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], + "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_neg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s": [["4", "5"]], + "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], + "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]], + "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_movi_((REG:W:F:VEC)).16b,_0xdf": [["5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]], + "_fabs_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5": [["2"]], + "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["2"], ["2"], ["2"], ["2"]], + "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]], + "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]], + "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]], + "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32": [["0", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]], + "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18": [["2"]], + "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], + "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19": [["6"]], + "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["5"]], + "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:VEC)).4s,_1.0e+0": [["5"]], + "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2": [["2"]], + "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_fcmp_((REG:R:F:32)),_#0.0": [["6"]], + "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s": [["4", "5"]], + "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]], + "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_mvn_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4", "5"]], + "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintx_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_frintm_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]], + "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]], + "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8": [["5"]], + "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4"]], + "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]], + "_frintp_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]], + "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32": [["0", "5"]], + "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]], + "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["0"], ["0"], ["0"]], + "_fcmp_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]], + "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"], ["6"]], + "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8": [["2"]], + "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["0"], ["0"]], + "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmn_((REG:R:G:64)),_#1": [["0", "5"]], + "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d": [["4", "5"]], + "_movi_((REG:W:F:VEC)).4s,_0": [["5"]], + "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fcvt_((REG:W:F:32)),_((REG:R:F:64))": [["4"]], + "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30": [["2"]], + "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8": [["5"]], + "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]], + "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]], + "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2": [["0", "5"]], + "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h": [["4", "5"]], + "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]], + "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_scvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]], + "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]], + "_fmov_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16": [["2"]], + "_fcmp_((REG:R:F:64)),_#0.0": [["6"]], + "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]], + "_movi_((REG:W:F:VEC)).8h,_0x53": [["5"]], + "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]": [["5"]], + "_fmov_((REG:W:F:64)),_1.0e+1": [["4", "5"]], + "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14": [["0", "5"]], + "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"], ["6"]], + "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b": [["0"], ["0"]], + "_scvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]], + "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]], + "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]": [["5"]], + "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h": [["4", "5"]], + "_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"]], + "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s": [["4"]], + "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6": [["0", "5"]], + "_fmov_((REG:W:F:VEC)).2d,_1.0e+0": [["5"]], + "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8": [["4", "5"]], + "_mvni_((REG:W:F:VEC)).8h,_0x40": [["5"]], + "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]], + "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]], + "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))": [["4"], ["4"], ["4"], ["4"], ["4"]], + "_frinta_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648": [["0", "5"]], + "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_fneg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63": [["6"]], + "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmn_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11": [["2"]], + "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32": [["0", "5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3": [["2"]], + "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]], + "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_fcmpe_((REG:R:F:64)),_#0.0": [["6"]], + "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintz_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0": [["4", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]], + "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], + "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49": [["2"]], + "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], + "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintp_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4", "5"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1": [["0", "5"]], + "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_tst_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]], + "_mov_((REG:W:G:64)),_2147483647": [["0", "5"]], + "_clz_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))": [["6"]] + } + } \ No newline at end of file diff --git a/osaca/data/a72/template.yml b/osaca/data/a72/template.yml index 8a47f1e..dbfd7ba 100644 --- a/osaca/data/a72/template.yml +++ b/osaca/data/a72/template.yml @@ -98,8 +98,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -112,8 +112,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -126,8 +126,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -142,8 +142,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -156,8 +156,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -170,8 +170,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -186,8 +186,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -200,8 +200,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -214,8 +214,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 5.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -228,8 +228,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 6.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -242,8 +242,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 6.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -256,8 +256,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 6.0 port_pressure: [[1, '1'], [2, '05']] throughput: 1.0 @@ -272,8 +272,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '3']] throughput: 1.0 @@ -286,8 +286,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -300,8 +300,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -316,8 +316,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -330,8 +330,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -344,8 +344,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 1.0 port_pressure: [[1, '3'], [1, '05']] throughput: 1.0 @@ -360,8 +360,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -374,8 +374,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -388,8 +388,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -402,8 +402,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -416,8 +416,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[2, '3'], [2, '05']] throughput: 2.0 @@ -430,8 +430,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[2, '3'], [2, '05']] throughput: 2.0 @@ -446,8 +446,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -462,8 +462,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 5.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -478,8 +478,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 1.0 port_pressure: [[1, '3']] throughput: 1.0 @@ -494,8 +494,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: '*' - pre-indexed: '*' + post_indexed: '*' + pre_indexed: '*' latency: 2.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -512,8 +512,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[1, '1']] throughput: 1.0 @@ -528,8 +528,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -544,8 +544,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[1, '1'], [1, '05']] throughput: 1.0 @@ -562,8 +562,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 6.0 port_pressure: [[2, '1']] throughput: 2.0 @@ -578,8 +578,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 6.0 port_pressure: [[2, '1'], [1, '05']] throughput: 2.0 @@ -594,8 +594,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 6.0 port_pressure: [[2, '1'], [1, '05']] throughput: 2.0 @@ -612,8 +612,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 2.0 port_pressure: [[2, '3']] throughput: 2.0 @@ -628,8 +628,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -644,8 +644,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 2.0 port_pressure: [[2, '3'], [1, '05']] throughput: 2.0 @@ -662,8 +662,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 @@ -678,8 +678,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 @@ -694,8 +694,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true latency: 4.0 port_pressure: [[4, '3'], [1, '05']] throughput: 4.0 diff --git a/osaca/data/create_db_entry.py b/osaca/data/create_db_entry.py old mode 100755 new mode 100644 diff --git a/osaca/data/generate_mov_entries.py b/osaca/data/generate_mov_entries.py old mode 100755 new mode 100644 diff --git a/osaca/data/isa/aarch64.yml b/osaca/data/isa/aarch64.yml index 7cd82a3..53ed2fd 100644 --- a/osaca/data/isa/aarch64.yml +++ b/osaca/data/isa/aarch64.yml @@ -865,8 +865,8 @@ instruction_forms: offset: "*" index: "*" scale: "*" - pre-indexed: "*" - post-indexed: "*" + pre_indexed: "*" + post_indexed: "*" source: true destination: false - name: [ldr, ldur, ldrb, ldrh, ldrsb, ldrsh, ldrsw] @@ -880,8 +880,8 @@ instruction_forms: offset: "*" index: "*" scale: "*" - pre-indexed: "*" - post-indexed: "*" + pre_indexed: "*" + post_indexed: "*" source: true destination: false - name: mov @@ -910,8 +910,8 @@ instruction_forms: offset: "*" index: "*" scale: "*" - pre-indexed: "*" - post-indexed: "*" + pre_indexed: "*" + post_indexed: "*" source: false destination: true - name: [str, stur] @@ -925,8 +925,8 @@ instruction_forms: offset: "*" index: "*" scale: "*" - pre-indexed: "*" - post-indexed: "*" + pre_indexed: "*" + post_indexed: "*" source: false destination: true - name: cmp diff --git a/osaca/data/m1.yml b/osaca/data/m1.yml index a2667a1..e36903b 100644 --- a/osaca/data/m1.yml +++ b/osaca/data/m1.yml @@ -9,14 +9,14 @@ hidden_loads: false load_latency: {w: 3.0, x: 3.0, b: 3.0, h: 3.0, s: 3.0, d: 3.0, q: 3.0, v: 3.0} p_index_latency: 1 load_throughput: -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '467']]} -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: false, post_indexed: false, port_pressure: [[1, '467']]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: false, post_indexed: true, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: true, post_indexed: false, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} load_throughput_default: [[1, '467']] store_throughput: -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '45']]} -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} -- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: false, post_indexed: false, port_pressure: [[1, '45']]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: false, post_indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre_indexed: true, post_indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} store_throughput_default: [[1, '45']] ports: ['0', '1', '2', '3', '3DV', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13'] port_model_scheme: | @@ -405,8 +405,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -419,8 +419,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -433,8 +433,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -447,8 +447,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -461,8 +461,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -475,8 +475,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -491,8 +491,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -507,8 +507,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -523,8 +523,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -539,8 +539,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -555,8 +555,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -571,8 +571,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -587,8 +587,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -603,8 +603,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -619,8 +619,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -635,8 +635,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -651,8 +651,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -667,8 +667,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -683,8 +683,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -699,8 +699,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -715,8 +715,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -731,8 +731,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -747,8 +747,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -763,8 +763,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -779,8 +779,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467']] @@ -795,8 +795,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467']] @@ -811,8 +811,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -827,8 +827,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -843,8 +843,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -857,8 +857,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -873,8 +873,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -889,8 +889,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -905,8 +905,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -921,8 +921,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -937,8 +937,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -953,8 +953,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -963,8 +963,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -973,8 +973,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -983,8 +983,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -993,8 +993,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1003,8 +1003,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1013,8 +1013,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1025,8 +1025,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -1037,8 +1037,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -1049,8 +1049,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1061,8 +1061,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1073,8 +1073,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1085,8 +1085,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1097,8 +1097,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -1109,8 +1109,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -1121,8 +1121,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1133,8 +1133,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1145,8 +1145,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1157,8 +1157,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1169,8 +1169,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -1181,8 +1181,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -1193,8 +1193,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1205,8 +1205,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1217,8 +1217,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1229,8 +1229,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1241,8 +1241,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467']] @@ -1253,8 +1253,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467']] @@ -1265,8 +1265,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -1277,8 +1277,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -1289,8 +1289,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -1299,8 +1299,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -1311,8 +1311,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] @@ -1323,8 +1323,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] @@ -1335,8 +1335,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1347,8 +1347,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1359,8 +1359,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1371,8 +1371,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] @@ -1753,8 +1753,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1767,8 +1767,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1781,8 +1781,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1795,8 +1795,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1809,8 +1809,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1823,8 +1823,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1839,8 +1839,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1855,8 +1855,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1871,8 +1871,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1887,8 +1887,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1903,8 +1903,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1919,8 +1919,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1935,8 +1935,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1951,8 +1951,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -1967,8 +1967,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1983,8 +1983,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -1999,8 +1999,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2015,8 +2015,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2031,8 +2031,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2047,8 +2047,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2063,8 +2063,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2079,8 +2079,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2095,8 +2095,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2111,8 +2111,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2127,8 +2127,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] @@ -2143,8 +2143,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] @@ -2159,8 +2159,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2175,8 +2175,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2191,8 +2191,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2207,8 +2207,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -2223,8 +2223,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2239,8 +2239,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2255,8 +2255,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2271,8 +2271,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2287,8 +2287,8 @@ instruction_forms: offset: '*' index: ~ scale: ~ - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2297,8 +2297,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2307,8 +2307,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2317,8 +2317,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2327,8 +2327,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2337,8 +2337,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2347,8 +2347,8 @@ instruction_forms: - class: register prefix: "*" - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2359,8 +2359,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2371,8 +2371,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2383,8 +2383,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2395,8 +2395,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2407,8 +2407,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2419,8 +2419,8 @@ instruction_forms: - class: register prefix: x - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2431,8 +2431,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2443,8 +2443,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2455,8 +2455,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2467,8 +2467,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2479,8 +2479,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2491,8 +2491,8 @@ instruction_forms: - class: register prefix: w - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2503,8 +2503,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2515,8 +2515,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2527,8 +2527,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2539,8 +2539,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2551,8 +2551,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2563,8 +2563,8 @@ instruction_forms: - class: register prefix: d - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2575,8 +2575,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] @@ -2587,8 +2587,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] @@ -2599,8 +2599,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2611,8 +2611,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2623,8 +2623,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] @@ -2635,8 +2635,8 @@ instruction_forms: - class: register prefix: q - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] @@ -2647,8 +2647,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2659,8 +2659,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] @@ -2671,8 +2671,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2683,8 +2683,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2695,8 +2695,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2707,8 +2707,8 @@ instruction_forms: - class: register prefix: s - class: identifier - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] @@ -2723,8 +2723,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] diff --git a/osaca/data/model_importer.py b/osaca/data/model_importer.py old mode 100755 new mode 100644 diff --git a/osaca/data/n1.yml b/osaca/data/n1.yml index c15be0c..7a3f145 100644 --- a/osaca/data/n1.yml +++ b/osaca/data/n1.yml @@ -9,19 +9,19 @@ hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 5.0, q: 6.0, v: 5.0, z: 4.0} p_index_latency: 1 load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} load_throughput_default: [[1, '67']] store_throughput: [] store_throughput_default: [[1, '56'], [1, '67']] @@ -379,8 +379,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 5.0 # 2*p67, from n1 opt guide port_pressure: [[2, '67']] @@ -395,8 +395,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 5.0 # 2*p67+1*p123, from n1 opt guide port_pressure: [[2, '67'], [1, '123']] @@ -411,8 +411,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67, from n1 opt guide port_pressure: [[2, '67']] @@ -427,8 +427,8 @@ instruction_forms: offset: ~ index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 7.0 # 2*p67+1*p123, from n1 opt guide port_pressure: [[2, '56'], [1, '123']] @@ -443,8 +443,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67 port_pressure: [[2, '67']] @@ -459,8 +459,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67+1*p123 port_pressure: [[2, '67'], [1, '123']] @@ -475,8 +475,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 5.0 # 2*p67+1*p123 port_pressure: [[2, '67'], [1, '123']] @@ -489,8 +489,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 6.0 # 1*p67 port_pressure: [[1, '67']] @@ -503,8 +503,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 6.0 # 1*p67 port_pressure: [[1, '67']] @@ -517,8 +517,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] @@ -531,8 +531,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] @@ -545,8 +545,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] @@ -610,8 +610,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p45+1*p67 port_pressure: [[2, '45'], [1, '67']] @@ -626,8 +626,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 2*p45+2*p67+1*123 port_pressure: [[2, '45'], [2, '67'], [1, '123']] @@ -642,8 +642,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p45+2*p67 port_pressure: [[2, '45'], [2, '67']] @@ -656,8 +656,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p23 port_pressure: [[1, '56'], [1, '23']] @@ -670,8 +670,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p67+1*p45 port_pressure: [[2, '67'], [1, '45']] @@ -684,8 +684,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p23 port_pressure: [[1, '56'], [1, '23']] @@ -698,8 +698,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p45 port_pressure: [[1, '67'], [1, '45']] @@ -712,8 +712,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 0 # 1*p67+1*p45+1*p123 port_pressure: [[1, '67'], [1, '45'], [1, '123']] @@ -726,8 +726,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p67+1*p45 port_pressure: [[1, '67'], [1, '45']] @@ -740,8 +740,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p67+1*p45+1*123 port_pressure: [[1, '67'], [1, '45'], [1, '123']] @@ -754,8 +754,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p67+1*p23+1*p123 port_pressure: [[1, '67'], [1, '23'], [1, '123']] diff --git a/osaca/data/pmevo_importer.py b/osaca/data/pmevo_importer.py old mode 100755 new mode 100644 diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index d0b1af9..58b52c0 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -2345,8 +2345,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2360,8 +2360,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2375,8 +2375,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2390,8 +2390,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67']] @@ -2405,8 +2405,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2420,8 +2420,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2435,8 +2435,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2450,8 +2450,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2465,8 +2465,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2480,8 +2480,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2495,8 +2495,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2510,8 +2510,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2526,8 +2526,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2541,8 +2541,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2557,8 +2557,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2572,8 +2572,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 5.0 port_pressure: [[1, '67'], [1, '012']] @@ -2588,8 +2588,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2602,8 +2602,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: true - pre-indexed: false + post_indexed: true + pre_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -2616,8 +2616,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: true + post_indexed: false + pre_indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -2631,8 +2631,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2646,8 +2646,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2662,8 +2662,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2677,8 +2677,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2692,8 +2692,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2707,8 +2707,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2722,8 +2722,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2737,8 +2737,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2752,8 +2752,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2767,8 +2767,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2782,8 +2782,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2797,8 +2797,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2812,8 +2812,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2827,8 +2827,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -2843,8 +2843,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2859,8 +2859,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2875,8 +2875,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2891,8 +2891,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2906,8 +2906,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2922,8 +2922,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -2940,8 +2940,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -2957,8 +2957,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -2974,8 +2974,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -2991,8 +2991,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 port_pressure: [[2, '67']] @@ -3008,8 +3008,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 4.0 port_pressure: [[2, '67'], [1, '012']] @@ -3025,8 +3025,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 port_pressure: [[2, '67'], [1, '012']] @@ -3042,8 +3042,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 port_pressure: [[2, '67'], [1, '012']] @@ -3059,8 +3059,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] @@ -3076,8 +3076,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 4.0 port_pressure: [[2, '67'], [1, '012']] @@ -3093,8 +3093,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 port_pressure: [[2, '67'], [1, '012']] @@ -3111,8 +3111,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -3128,8 +3128,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -3145,8 +3145,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -3162,8 +3162,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7']] @@ -3179,8 +3179,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -3196,8 +3196,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 port_pressure: [[1, '7'], [1, '012']] @@ -3213,8 +3213,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 port_pressure: [[2, '7']] @@ -3230,8 +3230,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 2.0 latency: 0 port_pressure: [[2, '7'], [1, '012']] @@ -3247,8 +3247,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 port_pressure: [[2, '7'], [1, '012']] @@ -3264,8 +3264,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 port_pressure: [[2, '7']] @@ -3281,8 +3281,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 2.0 latency: 0 port_pressure: [[2, '7'], [1, '012']] @@ -3298,8 +3298,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 port_pressure: [[2, '7'], [1, '012']] diff --git a/osaca/data/tx2.yml b/osaca/data/tx2.yml index cf35893..4c88e8d 100644 --- a/osaca/data/tx2.yml +++ b/osaca/data/tx2.yml @@ -9,19 +9,19 @@ hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} p_index_latency: 1 load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} load_throughput_default: [[1, '34'], [1, '012']] store_throughput: [] store_throughput_default: [[1, '34'], [1, '5']] @@ -539,8 +539,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[1, '012'], [2.0, '34']] @@ -555,8 +555,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -571,8 +571,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[1, '012'], [2.0, '34']] @@ -587,8 +587,8 @@ instruction_forms: offset: ~ index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -603,8 +603,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[1, '012'], [2.0, '34']] @@ -619,8 +619,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[1, '012'], [2.0, '34']] @@ -635,8 +635,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -651,8 +651,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -665,8 +665,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -679,8 +679,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -693,8 +693,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -707,8 +707,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -721,8 +721,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -735,8 +735,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1, '012'], [1.0, '34']] @@ -834,8 +834,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: ~ latency: ~ port_pressure: [] @@ -855,8 +855,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p34+1*p5 port_pressure: [[2, '34'], [1, '5']] @@ -871,8 +871,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 2*p34+1*p5 port_pressure: [[2, '34'], [1, '5']] @@ -887,8 +887,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p34+2*p5 port_pressure: [[2.0, '34'], [2.0, '5']] @@ -903,8 +903,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 # 2*p34+2*p5+1*012 port_pressure: [[2.0, '34'], [2.0, '5'], [1, '012']] @@ -919,8 +919,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p34+2*p5 port_pressure: [[2.0, '34'], [2.0, '5']] @@ -933,8 +933,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -947,8 +947,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -961,8 +961,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -975,8 +975,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -989,8 +989,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -1003,8 +1003,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] @@ -1017,8 +1017,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] @@ -1031,8 +1031,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -1045,8 +1045,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] @@ -1059,8 +1059,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] diff --git a/osaca/db_interface.py b/osaca/db_interface.py old mode 100755 new mode 100644 index 950834f..4107670 --- a/osaca/db_interface.py +++ b/osaca/db_interface.py @@ -10,6 +10,10 @@ from collections import OrderedDict import ruamel.yaml from osaca.semantics import MachineModel +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand +from osaca.parser.instruction_form import InstructionForm def sanity_check(arch: str, verbose=False, internet_check=False, output_file=sys.stdout): @@ -141,17 +145,17 @@ def _get_asmbench_output(input_data, isa): break else: i_form = input_data[i].strip() - mnemonic = i_form.split("-")[0] + mnemonic_parsed = i_form.split("-")[0] operands = i_form.split("-")[1].split("_") operands = [_create_db_operand(op, isa) for op in operands] - entry = { - "name": mnemonic, - "operands": operands, - "throughput": _validate_measurement(float(input_data[i + 2].split()[1]), "tp"), - "latency": _validate_measurement(float(input_data[i + 1].split()[1]), "lt"), - "port_pressure": None, - } - if not entry["throughput"] or not entry["latency"]: + entry = InstructionForm( + mnemonic=mnemonic_parsed, + operands=operands, + throughput=_validate_measurement(float(input_data[i + 2].split()[1]), "tp"), + latency=_validate_measurement(float(input_data[i + 1].split()[1]), "lt"), + port_pressure=None, + ) + if not entry.throughput or not entry.latency: warnings.warn( "Your measurement for {} looks suspicious".format(i_form) + " and was not added. Please inspect your benchmark." @@ -172,28 +176,28 @@ def _get_ibench_output(input_data, isa): # add only TP/LT value entry = db_entries[key] else: - mnemonic = instruction.split("-")[0] + mnemonic_parsed = instruction.split("-")[0] operands = instruction.split("-")[1].split("_") operands = [_create_db_operand(op, isa) for op in operands] - entry = { - "name": mnemonic, - "operands": operands, - "throughput": None, - "latency": None, - "port_pressure": None, - } + entry = InstructionForm( + mnemonic=mnemonic_parsed, + operands=operands, + throughput=None, + latency=None, + port_pressure=None, + ) if "TP" in instruction: - entry["throughput"] = _validate_measurement(float(line.split()[1]), "tp") - if not entry["throughput"]: + entry.throughput = _validate_measurement(float(line.split()[1]), "tp") + if not entry.throughput: warnings.warn( - "Your THROUGHPUT measurement for {} looks suspicious".format(key) + "Your throughput measurement for {} looks suspicious".format(key) + " and was not added. Please inspect your benchmark." ) elif "LT" in instruction: - entry["latency"] = _validate_measurement(float(line.split()[1]), "lt") - if not entry["latency"]: + entry.latency = _validate_measurement(float(line.split()[1]), "lt") + if not entry.latency: warnings.warn( - "Your LATENCY measurement for {} looks suspicious".format(key) + "Your latency measurement for {} looks suspicious".format(key) + " and was not added. Please inspect your benchmark." ) db_entries[key] = entry @@ -251,8 +255,8 @@ def _create_db_operand_aarch64(operand): "offset": "imd" if "o" in operand else None, "index": "gpr" if "i" in operand else None, "scale": 8 if "s" in operand else 1, - "pre-indexed": True if "r" in operand else False, - "post-indexed": True if "p" in operand else False, + "pre_indexed": True if "r" in operand else False, + "post_indexed": True if "p" in operand else False, } else: raise ValueError("Parameter {} is not a valid operand code".format(operand)) @@ -430,22 +434,6 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True): if arch_mm._check_for_duplicate(instr_form["name"], instr_form["operands"]): duplicate_instr_arch.append(instr_form) - # Check operands - for operand in instr_form["operands"]: - if operand["class"] == "register" and not ("name" in operand or "prefix" in operand): - # Missing 'name' key - bad_operand.append(instr_form) - elif operand["class"] == "memory" and ( - "base" not in operand - or "offset" not in operand - or "index" not in operand - or "scale" not in operand - ): - # Missing at least one key necessary for memory operands - bad_operand.append(instr_form) - elif operand["class"] == "immediate" and "imd" not in operand: - # Missing 'imd' key - bad_operand.append(instr_form) # every entry exists twice --> uniquify tmp_list = [] for _ in range(0, len(duplicate_instr_arch)): @@ -602,15 +590,25 @@ def _get_sanity_report_verbose( def _get_full_instruction_name(instruction_form): - """Get full instruction form name/identifier string out of given instruction form.""" + """Get one instruction name string including the mnemonic and all operands.""" operands = [] for op in instruction_form["operands"]: - op_attrs = [ - y + ":" + str(op[y]) - for y in list(filter(lambda x: True if x != "class" else False, op)) - ] - operands.append("{}({})".format(op["class"], ",".join(op_attrs))) - return "{} {}".format(instruction_form["name"], ",".join(operands)) + if isinstance(op, RegisterOperand): + op_attrs = [] + if op.name is not None: + op_attrs.append("name:" + op.name) + if op.prefix is not None: + op_attrs.append("prefix:" + op.prefix) + if op.shape is not None: + op_attrs.append("shape:" + op.shape) + operands.append("{}({})".format("register", ",".join(op_attrs))) + elif isinstance(op, MemoryOperand): + operands.append("mem") + elif isinstance(op, ImmediateOperand): + operands.append("imd") + else: + operands.append("") + return "{} {}".format(instruction_form["name"].lower(), ",".join(operands)) def __represent_none(self, data): diff --git a/osaca/frontend.py b/osaca/frontend.py old mode 100755 new mode 100644 index 9a5521d..763eb5c --- a/osaca/frontend.py +++ b/osaca/frontend.py @@ -8,7 +8,6 @@ import re from datetime import datetime as dt from osaca.semantics import INSTR_FLAGS, ArchSemantics, KernelDG, MachineModel -from osaca.parser import AttrDict def _get_version(*file_paths): @@ -54,7 +53,7 @@ class Frontend(object): :type instruction_form: `dict` :returns: `True` if comment line, `False` otherwise """ - return instruction_form["comment"] is not None and instruction_form["instruction"] is None + return instruction_form.comment is not None and instruction_form.mnemonic is None def throughput_analysis(self, kernel, show_lineno=False, show_cmnts=True): """ @@ -82,14 +81,16 @@ class Frontend(object): s += separator + "\n" for instruction_form in kernel: line = "{:4d} {} {} {}".format( - instruction_form["line_number"], + instruction_form.line_number, self._get_port_pressure( - instruction_form["port_pressure"], port_len, separator=sep_list + instruction_form.port_pressure, port_len, separator=sep_list ), - self._get_flag_symbols(instruction_form["flags"]) - if instruction_form["instruction"] is not None - else " ", - instruction_form["line"].strip().replace("\t", " "), + ( + self._get_flag_symbols(instruction_form.flags) + if instruction_form.mnemonic is not None + else " " + ), + instruction_form.line.strip().replace("\t", " "), ) line = line if show_lineno else col_sep + col_sep.join(line.split(col_sep)[1:]) if show_cmnts is False and self._is_comment(instruction_form): @@ -113,20 +114,20 @@ class Frontend(object): for instruction_form in cp_kernel: s += ( "{:4d} {} {:4.1f} {}{}{} {}".format( - instruction_form["line_number"], + instruction_form.line_number, separator, - instruction_form["latency_cp"], + instruction_form.latency_cp, separator, - "X" if INSTR_FLAGS.LT_UNKWN in instruction_form["flags"] else " ", + "X" if INSTR_FLAGS.LT_UNKWN in instruction_form.flags else " ", separator, - instruction_form["line"], + instruction_form.line, ) ) + "\n" s += ( "\n{:4} {} {:4.1f}".format( - " " * max([len(str(instr_form["line_number"])) for instr_form in cp_kernel]), + " " * max([len(str(instr_form.line_number)) for instr_form in cp_kernel]), " " * len(separator), - sum([instr_form["latency_cp"] for instr_form in cp_kernel]), + sum([instr_form.latency_cp for instr_form in cp_kernel]), ) ) + "\n" return s @@ -151,9 +152,9 @@ class Frontend(object): separator, dep_dict[dep]["latency"], separator, - dep_dict[dep]["root"]["line"].strip(), + dep_dict[dep]["root"].line.strip(), separator, - [node["line_number"] for node, lat in dep_dict[dep]["dependencies"]], + [node.line_number for node, lat in dep_dict[dep]["dependencies"]], ) return s @@ -238,10 +239,10 @@ class Frontend(object): if lcd_warning: warnings.append("LCDWarning") - if INSTR_FLAGS.TP_UNKWN in [flag for instr in kernel for flag in instr["flags"]]: + if INSTR_FLAGS.TP_UNKWN in [flag for instr in kernel for flag in instr.flags]: warnings.append("UnknownInstrWarning") - tp_sum = ArchSemantics.get_throughput_sum(kernel) or kernel[0]["port_pressure"] + tp_sum = ArchSemantics.get_throughput_sum(kernel) or kernel[0].port_pressure cp_kernel = kernel_dg.get_critical_path() dep_dict = kernel_dg.get_loopcarried_dependencies() @@ -254,31 +255,31 @@ class Frontend(object): "Warnings": warnings, "Kernel": [ { - "Line": re.sub(r"\s+", " ", x["line"].strip()), - "LineNumber": x["line_number"], - "Flags": list(x["flags"]), - "Instruction": x["instruction"], - "Operands": AttrDict.get_dict(x["operands"]), - "SemanticOperands": AttrDict.get_dict(x["semantic_operands"]), - "Label": x["label"], - "Directive": x["directive"], - "Latency": float(x["latency"]), - "LatencyCP": float(x["latency_cp"]), - "LatencyLCD": float(x["latency_lcd"]), - "Throughput": float(x["throughput"]), - "LatencyWithoutLoad": float(x["latency_wo_load"]), + "Line": re.sub(r"\s+", " ", x.line.strip()), + "LineNumber": x.line_number, + "Flags": list(x.flags), + "Instruction": x.mnemonic, + "Operands": x.operands, + "SemanticOperands": x.semantic_operands, + "Label": x.label, + "Directive": x.directive, + "Latency": float(x.latency), + "LatencyCP": float(x.latency_cp), + "LatencyLCD": float(x.latency_lcd), + "Throughput": float(x.throughput), + "LatencyWithoutLoad": float(x.latency_wo_load), "PortPressure": { self._machine_model.get_ports()[i]: v - for i, v in enumerate(x["port_pressure"]) + for i, v in enumerate(x.port_pressure) }, "PortUops": [ { "Ports": list(y[1]), "Cycles": y[0], } - for y in x["port_uops"] + for y in x.port_uops ], - "Comment": x["comment"], + "Comment": x.comment, } for x in kernel ], @@ -286,7 +287,7 @@ class Frontend(object): "PortPressure": { self._machine_model.get_ports()[i]: v for i, v in enumerate(tp_sum) }, - "CriticalPath": sum([x["latency_cp"] for x in cp_kernel]), + "CriticalPath": sum([x.latency_cp for x in cp_kernel]), "LCD": lcd_sum, }, "Target": { @@ -325,7 +326,7 @@ class Frontend(object): # Separator for ports separator = "-" * sum([x + 3 for x in port_len]) + "-" # ... for line numbers - separator += "--" + len(str(kernel[-1]["line_number"])) * "-" + separator += "--" + len(str(kernel[-1].line_number)) * "-" col_sep = "|" # for LCD/CP column separator += "-" * (2 * 6 + len(col_sep)) + "-" * len(col_sep) + "--" @@ -333,14 +334,14 @@ class Frontend(object): headline = "Port pressure in cycles" headline_str = "{{:^{}}}".format(len(separator)) # Prepare CP/LCD variable - cp_lines = [x["line_number"] for x in cp_kernel] + cp_lines = [x.line_number for x in cp_kernel] lcd_sum = 0.0 lcd_lines = {} if dep_dict: longest_lcd = max(dep_dict, key=lambda ln: dep_dict[ln]["latency"]) lcd_sum = dep_dict[longest_lcd]["latency"] lcd_lines = { - instr["line_number"]: lat for instr, lat in dep_dict[longest_lcd]["dependencies"] + instr.line_number: lat for instr, lat in dep_dict[longest_lcd]["dependencies"] } port_line = ( @@ -354,31 +355,33 @@ class Frontend(object): for instruction_form in kernel: if show_cmnts is False and self._is_comment(instruction_form): continue - line_number = instruction_form["line_number"] - used_ports = [list(uops[1]) for uops in instruction_form["port_uops"]] + line_number = instruction_form.line_number + used_ports = [list(uops[1]) for uops in instruction_form.port_uops] used_ports = list(set([p for uops_ports in used_ports for p in uops_ports])) s += "{:4d} {}{} {} {}\n".format( line_number, self._get_port_pressure( - instruction_form["port_pressure"], port_len, used_ports, sep_list + instruction_form.port_pressure, port_len, used_ports, sep_list ), self._get_lcd_cp_ports( - instruction_form["line_number"], + instruction_form.line_number, cp_kernel if line_number in cp_lines else None, lcd_lines.get(line_number), ), - self._get_flag_symbols(instruction_form["flags"]) - if instruction_form["instruction"] is not None - else " ", - instruction_form["line"].strip().replace("\t", " "), + ( + self._get_flag_symbols(instruction_form.flags) + if instruction_form.mnemonic is not None + else " " + ), + instruction_form.line.strip().replace("\t", " "), ) s += "\n" # check for unknown instructions and throw warning if called without --ignore-unknown if not ignore_unknown and INSTR_FLAGS.TP_UNKWN in [ - flag for instr in kernel for flag in instr["flags"] + flag for instr in kernel for flag in instr.flags ]: num_missing = len( - [instr["flags"] for instr in kernel if INSTR_FLAGS.TP_UNKWN in instr["flags"]] + [instr.flags for instr in kernel if INSTR_FLAGS.TP_UNKWN in instr.flags] ) s += self._missing_instruction_error(num_missing) else: @@ -386,8 +389,8 @@ class Frontend(object): tp_sum = ArchSemantics.get_throughput_sum(kernel) # if ALL instructions are unknown, take a line of 0s if not tp_sum: - tp_sum = kernel[0]["port_pressure"] - cp_sum = sum([x["latency_cp"] for x in cp_kernel]) + tp_sum = kernel[0].port_pressure + cp_sum = sum([x.latency_cp for x in cp_kernel]) s += ( lineno_filler + self._get_port_pressure(tp_sum, port_len, separator=" ") @@ -500,14 +503,14 @@ class Frontend(object): def _get_node_by_lineno(self, lineno, kernel): """Returns instruction form from kernel by its line number.""" - nodes = [instr for instr in kernel if instr["line_number"] == lineno] + nodes = [instr for instr in kernel if instr.line_number == lineno] return nodes[0] if len(nodes) > 0 else None def _get_lcd_cp_ports(self, line_number, cp_dg, dep_lat, separator="|"): """Returns the CP and LCD line for one instruction.""" lat_cp = lat_lcd = "" if cp_dg: - lat_cp = float(self._get_node_by_lineno(line_number, cp_dg)["latency_cp"]) + lat_cp = float(self._get_node_by_lineno(line_number, cp_dg).latency_cp) if dep_lat is not None: lat_lcd = float(dep_lat) return "{} {:>4} {} {:>4} {}".format(separator, lat_cp, separator, lat_lcd, separator) @@ -516,7 +519,7 @@ class Frontend(object): """Returns the maximal length needed to print all throughputs of the kernel.""" port_len = [4 for x in self._machine_model.get_ports()] for instruction_form in kernel: - for i, port in enumerate(instruction_form["port_pressure"]): + for i, port in enumerate(instruction_form.port_pressure): if len("{:.2f}".format(port)) > port_len[i]: port_len[i] = len("{:.2f}".format(port)) return port_len diff --git a/osaca/osaca.py b/osaca/osaca.py old mode 100755 new mode 100644 index c60e950..34460f3 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -337,7 +337,7 @@ def inspect(args, output_file=sys.stdout): # Reduce to marked kernel or chosen section and add semantics if args.lines: line_range = get_line_range(args.lines) - kernel = [line for line in parsed_code if line["line_number"] in line_range] + kernel = [line for line in parsed_code if line.line_number in line_range] print_length_warning = False else: kernel = reduce_to_section(parsed_code, isa) @@ -434,10 +434,7 @@ def get_unmatched_instruction_ratio(kernel): """Return ratio of unmatched from total instructions in kernel.""" unmatched_counter = 0 for instruction in kernel: - if ( - INSTR_FLAGS.TP_UNKWN in instruction["flags"] - and INSTR_FLAGS.LT_UNKWN in instruction["flags"] - ): + if INSTR_FLAGS.TP_UNKWN in instruction.flags and INSTR_FLAGS.LT_UNKWN in instruction.flags: unmatched_counter += 1 return unmatched_counter / len(kernel) diff --git a/osaca/parser/__init__.py b/osaca/parser/__init__.py index ba43c70..3b5e8ba 100644 --- a/osaca/parser/__init__.py +++ b/osaca/parser/__init__.py @@ -3,12 +3,21 @@ Collection of parsers supported by OSACA. Only the parser below will be exported, so please add new parsers to __all__. """ -from .attr_dict import AttrDict + from .base_parser import BaseParser from .parser_x86att import ParserX86ATT from .parser_AArch64 import ParserAArch64 +from .instruction_form import InstructionForm +from .operand import Operand -__all__ = ["AttrDict", "BaseParser", "ParserX86ATT", "ParserAArch64", "get_parser"] +__all__ = [ + "Operand", + "InstructionForm", + "BaseParser", + "ParserX86ATT", + "ParserAArch64", + "get_parser", +] def get_parser(isa): diff --git a/osaca/parser/attr_dict.py b/osaca/parser/attr_dict.py deleted file mode 100755 index 35f6c40..0000000 --- a/osaca/parser/attr_dict.py +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env python3 -"""Attribute Dictionary to access dictionary entries as attributes.""" - - -class AttrDict(dict): - def __init__(self, *args, **kwargs): - super(AttrDict, self).__init__(*args, **kwargs) - self.__dict__ = self - - @staticmethod - def convert_dict(dictionary): - """ - Convert given dictionary to `AttrDict`. - - :param dictionary: `dict` to be converted - :type dictionary: `dict` - :returns: `AttrDict` representation of ``dictionary`` - """ - if isinstance(dictionary, type(list())): - return [AttrDict.convert_dict(x) for x in dictionary] - if isinstance(dictionary, type(dict())): - for key in list(dictionary.keys()): - entry = dictionary[key] - if isinstance(entry, type(dict())) or isinstance(entry, type(AttrDict())): - dictionary[key] = AttrDict.convert_dict(dictionary[key]) - if isinstance(entry, type(list())): - dictionary[key] = [AttrDict.convert_dict(x) for x in entry] - return AttrDict(dictionary) - return dictionary - - @staticmethod - def get_dict(attrdict): - """ - Convert given `AttrDict` to a standard dictionary. - - :param attrdict: `AttrDict` to be converted - :type attrdict: `AttrDict` - :returns: `dict` representation of ``AttrDict`` - """ - if isinstance(attrdict, type(list())): - return [AttrDict.get_dict(x) for x in attrdict] - if isinstance(attrdict, type(AttrDict())): - newdict = {} - for key in list(attrdict.keys()): - entry = attrdict[key] - if isinstance(entry, type(dict())) or isinstance(entry, type(AttrDict())): - newdict[key] = AttrDict.get_dict(attrdict[key]) - elif isinstance(entry, type(list())): - newdict[key] = [AttrDict.get_dict(x) for x in entry] - else: - newdict[key] = entry - return newdict - return attrdict diff --git a/osaca/parser/base_parser.py b/osaca/parser/base_parser.py old mode 100755 new mode 100644 index b55c9b7..3ac2124 --- a/osaca/parser/base_parser.py +++ b/osaca/parser/base_parser.py @@ -6,16 +6,18 @@ import re class BaseParser(object): # Identifiers for operand types - COMMENT_ID = "comment" - DIRECTIVE_ID = "directive" - IMMEDIATE_ID = "immediate" - LABEL_ID = "label" - IDENTIFIER_ID = "identifier" - MEMORY_ID = "memory" - REGISTER_ID = "register" - SEGMENT_EXT_ID = "segment_extension" - INSTRUCTION_ID = "instruction" - OPERANDS_ID = "operands" + comment_id = "comment" + directive_id = "directive" + immediate_id = "immediate" + label_id = "label" + identifier = "identifier" + memory_id = "memory" + register_id = "register" + condition_id = "condition" + segment_ext = "segment_extension" + mnemonic = "instruction" + operands = "operands" + prefetch = "prfop" _parser_constructed = False def __init__(self): diff --git a/osaca/parser/condition.py b/osaca/parser/condition.py new file mode 100644 index 0000000..1acdf50 --- /dev/null +++ b/osaca/parser/condition.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class ConditionOperand(Operand): + def __init__( + self, + ccode=None, + source=False, + destination=False, + ): + super().__init__(source, destination) + self._ccode = ccode + + @property + def ccode(self): + return self._ccode + + @ccode.setter + def ccode(self, ccode): + self._ccode = ccode + + def __str__(self): + return f"Condition(ccode={self._ccode}, source={self._source}, destination={self._destination})" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/directive.py b/osaca/parser/directive.py new file mode 100644 index 0000000..fff2616 --- /dev/null +++ b/osaca/parser/directive.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class DirectiveOperand(Operand): + def __init__(self, name=None, parameters=None): + self._name = name + self._parameters = parameters + + @property + def name(self): + return self._name + + @name.setter + def name(self, name): + self._name = name + + @property + def parameters(self): + return self._parameters + + @parameters.setter + def parameters(self, parameters): + self._parameters = parameters + + def __eq__(self, other): + if isinstance(other, DirectiveOperand): + return self._name == other._name and self._parameters == other._parameters + elif isinstance(other, dict): + return self._name == other["name"] and self._parameters == other["parameters"] + return False + + def __str__(self): + return f"Directive(name={self._name}, parameters={self._parameters})" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/flag.py b/osaca/parser/flag.py new file mode 100644 index 0000000..7edce72 --- /dev/null +++ b/osaca/parser/flag.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class FlagOperand(Operand): + def __init__(self, name=None, source=False, destination=False): + self._name = name + super().__init__(source, destination) + + @property + def name(self): + return self._name + + @name.setter + def name(self, name): + self._name = name + + def __str__(self): + return f"Flag(name={self._name}, source={self._source}, relocation={self._destination})" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/identifier.py b/osaca/parser/identifier.py new file mode 100644 index 0000000..e5c0209 --- /dev/null +++ b/osaca/parser/identifier.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class IdentifierOperand(Operand): + def __init__(self, name=None, offset=None, relocation=None, source=False, destination=False): + super().__init__(source, destination) + self._name = name + self._offset = offset + self._relocation = relocation + + @property + def name(self): + return self._name + + @name.setter + def name(self, name): + self._name = name + + @property + def offset(self): + return self._offset + + @property + def relocation(self): + return self._relocation + + @offset.setter + def offset(self, offset): + self._offset = offset + + @relocation.setter + def relocation(self, relocation): + self._relocation = relocation + + def __str__(self): + return ( + f"Identifier(name={self._name}, offset={self._offset}, relocation={self._relocation})" + ) + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/immediate.py b/osaca/parser/immediate.py new file mode 100644 index 0000000..afda34c --- /dev/null +++ b/osaca/parser/immediate.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class ImmediateOperand(Operand): + def __init__( + self, + identifier=None, + imd_type=None, + value=None, + shift=None, + source=False, + destination=False, + ): + super().__init__(source, destination) + self._identifier = identifier + self._imd_type = imd_type + self._value = value + self._shift = shift + + @property + def identifier(self): + return self._identifier + + @property + def imd_type(self): + return self._imd_type + + @property + def value(self): + return self._value + + @property + def shift(self): + return self._imd_type + + @imd_type.setter + def imd_type(self, itype): + self._imd_type = itype + + @identifier.setter + def identifier(self, identifier): + self._identifier = identifier + + @value.setter + def value(self, value): + self._value = value + + @shift.setter + def shift(self, shift): + self._shift = shift + + def __str__(self): + return ( + f"Immediate(identifier={self._identifier}, imd_type={self._imd_type}, " + f"value={self._value}, shift={self._shift}, source={self._source}, destination={self._destination})" + ) + + def __repr__(self): + return self.__str__() + + def __eq__(self, other): + if isinstance(other, ImmediateOperand): + return ( + self._identifier == other._identifier + and self._imd_type == other._imd_type + and self._value == other._value + and self._shift == other._shift + ) + return False diff --git a/osaca/parser/instruction_form.py b/osaca/parser/instruction_form.py new file mode 100644 index 0000000..d32bc34 --- /dev/null +++ b/osaca/parser/instruction_form.py @@ -0,0 +1,224 @@ +#!/usr/bin/env python3 + + +class InstructionForm: + def __init__( + self, + mnemonic=None, + operands=[], + hidden_operands=[], + directive_id=None, + comment_id=None, + label_id=None, + line=None, + line_number=None, + semantic_operands={"source": [], "destination": [], "src_dst": []}, + throughput=None, + latency=None, + uops=None, + port_pressure=None, + operation=None, + breaks_dependency_on_equal_operands=False, + ): + self._mnemonic = mnemonic + self._operands = operands + self._hidden_operands = hidden_operands + self._directive_id = directive_id + self._comment_id = comment_id + self._label_id = label_id + self._line = line + self._line_number = line_number + + self._semantic_operands = semantic_operands + self._operation = operation + self._uops = uops + self._breaks_dependency_on_equal_operands = breaks_dependency_on_equal_operands + self._latency = latency + self._throughput = throughput + self._latency_cp = [] + self._latency_lcd = [] + self._latency_wo_load = None + self._port_pressure = port_pressure + self._port_uops = [] + self._flags = [] + + @property + def semantic_operands(self): + return self._semantic_operands + + @property + def mnemonic(self): + return self._mnemonic + + @property + def label(self): + return self._label_id + + @property + def comment(self): + return self._comment_id + + @property + def directive(self): + return self._directive_id + + @property + def line_number(self): + return self._line_number + + @property + def line(self): + return self._line + + @property + def operands(self): + return self._operands + + @property + def hidden_operands(self): + return self._hidden_operands + + @property + def port_pressure(self): + return self._port_pressure + + @property + def port_uops(self): + return self._port_uops + + @property + def flags(self): + return self._flags + + @property + def uops(self): + return self._uops + + @property + def throughput(self): + return self._throughput + + @property + def latency(self): + return self._latency + + @property + def latency_wo_load(self): + return self._latency_wo_load + + @property + def operation(self): + return self._operation + + @property + def breaks_dependency_on_equal_operands(self): + return self._breaks_dependency_on_equal_operands + + @semantic_operands.setter + def semantic_operands(self, semantic_operands): + self._semantic_operands = semantic_operands + + @directive.setter + def directive(self, directive): + self._directive_id = directive + + @line_number.setter + def line_number(self, line_number): + self._line_number = line_number + + @line.setter + def line(self, line): + self._line = line + + @operands.setter + def operands(self, operands): + self._operands = operands + + @hidden_operands.setter + def hidden_operands(self, hidden_operands): + self._hidden_operands = hidden_operands + + @breaks_dependency_on_equal_operands.setter + def breaks_dependency_on_equal_operands(self, boolean): + self._breaks_dependency_on_equal_operands = boolean + + @mnemonic.setter + def mnemonic(self, mnemonic): + self._mnemonic = mnemonic + + @label.setter + def label(self, label): + self._label_id = label + + @comment.setter + def comment(self, comment): + self._comment_id = comment + + @port_pressure.setter + def port_pressure(self, port_pressure): + self._port_pressure = port_pressure + + @port_uops.setter + def port_uops(self, port_uops): + self._port_uops = port_uops + + @flags.setter + def flags(self, flags): + self._flags = flags + + @uops.setter + def uops(self, uops): + self._uops = uops + + @throughput.setter + def throughput(self, throughput): + self._throughput = throughput + + @operation.setter + def operation(self, operation): + self._operation = operation + + @latency.setter + def latency(self, latency): + self._latency = latency + + @latency_wo_load.setter + def latency_wo_load(self, latency_wo_load): + self._latency_wo_load = latency_wo_load + + def __str__(self): + attributes = { + "mnemonic": self.mnemonic, + "operands": self.operands, + "hidden_operands": self.hidden_operands, + "directive_id": self.directive, + "comment_id": self.comment, + "label_id": self.label, + "line": self.line, + "line_number": self.line_number, + "semantic_operands": self.semantic_operands, + "throughput": self.throughput, + "latency": self.latency, + "uops": self.uops, + "port_pressure": self.port_pressure, + "operation": self.operation, + "breaks_dependency_on_equal_operands": self.breaks_dependency_on_equal_operands, + } + attr_str = "\n ".join(f"{key}={value}" for key, value in attributes.items()) + return f"InstructionForm({attr_str})" + + def __repr__(self): + return self.__str__() + + def __eq__(self, other): + if isinstance(other, InstructionForm): + return ( + self._mnemonic == other._mnemonic + and self._directive_id == other._directive_id + and self._comment_id == other._comment_id + and self._label_id == other._label_id + and self._line == other._line + and self._line_number == other._line_number + and self._semantic_operands == other._semantic_operands + ) + return False diff --git a/osaca/parser/label.py b/osaca/parser/label.py new file mode 100644 index 0000000..39b1ece --- /dev/null +++ b/osaca/parser/label.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class LabelOperand(Operand): + def __init__(self, name=None): + self._name = name + + @property + def name(self): + return self._name + + @name.setter + def name(self, name): + self._name = name + + def __str__(self): + return f"Label(name={self._name}" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/memory.py b/osaca/parser/memory.py new file mode 100644 index 0000000..25d07a6 --- /dev/null +++ b/osaca/parser/memory.py @@ -0,0 +1,144 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class MemoryOperand(Operand): + def __init__( + self, + offset=None, + base=None, + index=None, + scale=1, + segment_ext=None, + mask=None, + pre_indexed=False, + post_indexed=False, + indexed_val=None, + dst=None, + source=False, + destination=False, + ): + super().__init__(source, destination) + self._offset = offset + self._base = base + self._index = index + self._scale = scale + self._segment_ext = segment_ext + self._mask = mask + self._pre_indexed = pre_indexed + self._post_indexed = post_indexed + self._indexed_val = indexed_val + self._dst = dst + + @property + def offset(self): + return self._offset + + @property + def immediate(self): + return self._immediate_id + + @property + def base(self): + return self._base + + @property + def index(self): + return self._index + + @property + def scale(self): + return self._scale + + @property + def segment_ext(self): + return self._segment_ext + + @property + def mask(self): + return self._mask + + @property + def pre_indexed(self): + return self._pre_indexed + + @property + def post_indexed(self): + return self._post_indexed + + @property + def indexed_val(self): + return self._indexed_val + + @property + def dst(self): + return self._dst + + @dst.setter + def dst(self, dst): + self._dst = dst + + @segment_ext.setter + def segment_ext(self, segment): + self._segment_ext = segment + + @offset.setter + def offset(self, offset): + self._offset = offset + + @base.setter + def base(self, base): + self._base = base + + @index.setter + def index(self, index): + self._index = index + + @scale.setter + def scale(self, scale): + self._scale = scale + + @mask.setter + def mask(self, mask): + self._mask = mask + + @pre_indexed.setter + def pre_indexed(self, pre_indexed): + self._pre_indexed = pre_indexed + + @post_indexed.setter + def post_indexed(self, post_indexed): + self._post_indexed = post_indexed + + @indexed_val.setter + def indexed_val(self, value): + self._indexed_val = value + + def __str__(self): + return ( + f"MemoryOperand(offset={self._offset}, " + f"base={self._base}, index={self._index}, scale={self._scale}, " + f"segment_ext={self._segment_ext}, mask={self._mask}, " + f"pre_indexed={self._pre_indexed}, post_indexed={self._post_indexed}, " + f"indexed_val={self._indexed_val}," + f"source={self._source}, destination={self._destination})" + ) + + def __repr__(self): + return self.__str__() + + def __eq__(self, other): + if isinstance(other, MemoryOperand): + return ( + self._offset == other._offset + and self._base == other._base + and self._index == other._index + and self._scale == other._scale + and self._segment_ext == other._segment_ext + and self._mask == other._mask + and self._pre_indexed == other._pre_indexed + and self._post_indexed == other._post_indexed + and self._indexed_val == other._indexed_val + ) + return False diff --git a/osaca/parser/operand.py b/osaca/parser/operand.py new file mode 100644 index 0000000..cb4219c --- /dev/null +++ b/osaca/parser/operand.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 + + +class Operand: + def __init__(self, source=False, destination=False): + self._source = source + self._destination = destination + + @property + def source(self): + return self._source + + @property + def destination(self): + return self._destination + + @source.setter + def source(self, source): + self._source = source + + @destination.setter + def destination(self, destination): + self._destination = destination + + def __str__(self): + return f"Operand(Source: {self._source}, Destination: {self._destination})" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/parser_AArch64.py b/osaca/parser/parser_AArch64.py old mode 100755 new mode 100644 index 9464443..62ec851 --- a/osaca/parser/parser_AArch64.py +++ b/osaca/parser/parser_AArch64.py @@ -2,7 +2,17 @@ from copy import deepcopy import pyparsing as pp -from osaca.parser import AttrDict, BaseParser +from osaca.parser import BaseParser +from osaca.parser.instruction_form import InstructionForm +from osaca.parser.operand import Operand +from osaca.parser.directive import DirectiveOperand +from osaca.parser.memory import MemoryOperand +from osaca.parser.label import LabelOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.identifier import IdentifierOperand +from osaca.parser.immediate import ImmediateOperand +from osaca.parser.condition import ConditionOperand +from osaca.parser.prefetch import PrefetchOperand class ParserAArch64(BaseParser): @@ -24,7 +34,7 @@ class ParserAArch64(BaseParser): symbol_comment = "//" self.comment = pp.Literal(symbol_comment) + pp.Group( pp.ZeroOrMore(pp.Word(pp.printables)) - ).setResultsName(self.COMMENT_ID) + ).setResultsName(self.comment_id) # Define ARM assembly identifier decimal_number = pp.Combine( pp.Optional(pp.Literal("-")) + pp.Word(pp.nums) @@ -42,11 +52,11 @@ class ParserAArch64(BaseParser): pp.Suppress(pp.Literal("+")) + (hex_number | decimal_number).setResultsName("offset") ) - ).setResultsName(self.IDENTIFIER_ID) + ).setResultsName(self.identifier) # Label self.label = pp.Group( identifier.setResultsName("name") + pp.Literal(":") + pp.Optional(self.comment) - ).setResultsName(self.LABEL_ID) + ).setResultsName(self.label_id) # Directive directive_option = pp.Combine( pp.Word(pp.alphas + "#@.%", exact=1) @@ -61,7 +71,7 @@ class ParserAArch64(BaseParser): + pp.Word(pp.alphanums + "_").setResultsName("name") + (pp.OneOrMore(directive_parameter) ^ commaSeparatedList).setResultsName("parameters") + pp.Optional(self.comment) - ).setResultsName(self.DIRECTIVE_ID) + ).setResultsName(self.directive_id) # LLVM-MCA markers self.llvm_markers = pp.Group( pp.Literal("#") @@ -70,7 +80,7 @@ class ParserAArch64(BaseParser): + (pp.CaselessLiteral("BEGIN") | pp.CaselessLiteral("END")) ) + pp.Optional(self.comment) - ).setResultsName(self.COMMENT_ID) + ).setResultsName(self.comment_id) ############################## # Instructions @@ -96,7 +106,7 @@ class ParserAArch64(BaseParser): pp.Optional(pp.Literal(symbol_immediate)) + (hex_number ^ decimal_number ^ float_ ^ double_) | (pp.Optional(pp.Literal(symbol_immediate)) + identifier) - ).setResultsName(self.IMMEDIATE_ID) + ).setResultsName(self.immediate_id) shift_op = ( pp.CaselessLiteral("lsl") ^ pp.CaselessLiteral("lsr") @@ -112,7 +122,7 @@ class ParserAArch64(BaseParser): + pp.Suppress(pp.Literal(",")) + shift_op.setResultsName("shift_op") + pp.Optional(immediate).setResultsName("shift") - ).setResultsName(self.IMMEDIATE_ID) + ).setResultsName(self.immediate_id) # Register: # scalar: [XWBHSDQ][0-9]{1,2} | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])? # | predicate: P[0-9]{1,2}(/[ZM])? @@ -170,7 +180,7 @@ class ParserAArch64(BaseParser): + shift_op.setResultsName("shift_op") + pp.Optional(immediate).setResultsName("shift") ) - ).setResultsName(self.REGISTER_ID) + ).setResultsName(self.register_id) self.register = register # Memory register_index = register.setResultsName("index") + pp.Optional( @@ -186,7 +196,7 @@ class ParserAArch64(BaseParser): pp.Literal("!").setResultsName("pre_indexed") | (pp.Suppress(pp.Literal(",")) + immediate.setResultsName("post_indexed")) ) - ).setResultsName(self.MEMORY_ID) + ).setResultsName(self.memory_id) prefetch_op = pp.Group( pp.Group(pp.CaselessLiteral("PLD") ^ pp.CaselessLiteral("PST")).setResultsName("type") + pp.Group( @@ -252,24 +262,21 @@ class ParserAArch64(BaseParser): :type line_number: int, optional :return: `dict` -- parsed asm line (comment, label, directive or instruction form) """ - instruction_form = AttrDict( - { - self.INSTRUCTION_ID: None, - self.OPERANDS_ID: [], - self.DIRECTIVE_ID: None, - self.COMMENT_ID: None, - self.LABEL_ID: None, - "line": line, - "line_number": line_number, - } + instruction_form = InstructionForm( + mnemonic=None, + operands=[], + directive_id=None, + comment_id=None, + label_id=None, + line=line, + line_number=line_number, ) result = None # 1. Parse comment try: result = self.process_operand(self.comment.parseString(line, parseAll=True).asDict()) - result = AttrDict.convert_dict(result) - instruction_form[self.COMMENT_ID] = " ".join(result[self.COMMENT_ID]) + instruction_form.comment = " ".join(result[self.comment_id]) except pp.ParseException: pass # 1.2 check for llvm-mca marker @@ -277,40 +284,32 @@ class ParserAArch64(BaseParser): result = self.process_operand( self.llvm_markers.parseString(line, parseAll=True).asDict() ) - result = AttrDict.convert_dict(result) - instruction_form[self.COMMENT_ID] = " ".join(result[self.COMMENT_ID]) + instruction_form.comment = " ".join(result[self.comment_id]) except pp.ParseException: pass # 2. Parse label if result is None: try: + # returns tuple with label operand and comment, if any result = self.process_operand(self.label.parseString(line, parseAll=True).asDict()) - result = AttrDict.convert_dict(result) - instruction_form[self.LABEL_ID] = result[self.LABEL_ID].name - if self.COMMENT_ID in result[self.LABEL_ID]: - instruction_form[self.COMMENT_ID] = " ".join( - result[self.LABEL_ID][self.COMMENT_ID] - ) + instruction_form.label = result[0].name + if result[1] is not None: + instruction_form.comment = " ".join(result[1]) except pp.ParseException: pass # 3. Parse directive if result is None: try: + # returns directive with label operand and comment, if any result = self.process_operand( self.directive.parseString(line, parseAll=True).asDict() ) - result = AttrDict.convert_dict(result) - instruction_form[self.DIRECTIVE_ID] = AttrDict( - { - "name": result[self.DIRECTIVE_ID].name, - "parameters": result[self.DIRECTIVE_ID].parameters, - } + instruction_form.directive = DirectiveOperand( + name=result[0].name, parameters=result[0].parameters ) - if self.COMMENT_ID in result[self.DIRECTIVE_ID]: - instruction_form[self.COMMENT_ID] = " ".join( - result[self.DIRECTIVE_ID][self.COMMENT_ID] - ) + if result[1] is not None: + instruction_form.comment = " ".join(result[1]) except pp.ParseException: pass @@ -322,10 +321,9 @@ class ParserAArch64(BaseParser): raise ValueError( "Unable to parse {!r} on line {}".format(line, line_number) ) from e - instruction_form[self.INSTRUCTION_ID] = result[self.INSTRUCTION_ID] - instruction_form[self.OPERANDS_ID] = result[self.OPERANDS_ID] - instruction_form[self.COMMENT_ID] = result[self.COMMENT_ID] - + instruction_form.mnemonic = result.mnemonic + instruction_form.operands = result.operands + instruction_form.comment = result.comment return instruction_form def parse_instruction(self, instruction): @@ -336,7 +334,6 @@ class ParserAArch64(BaseParser): :returns: `dict` -- parsed instruction form """ result = self.instruction_parser.parseString(instruction, parseAll=True).asDict() - result = AttrDict.convert_dict(result) operands = [] # Add operands to list # Check first operand @@ -359,40 +356,69 @@ class ParserAArch64(BaseParser): if "operand5" in result: operand = self.process_operand(result["operand5"]) operands.extend(operand) if isinstance(operand, list) else operands.append(operand) - - return_dict = AttrDict( - { - self.INSTRUCTION_ID: result.mnemonic, - self.OPERANDS_ID: operands, - self.COMMENT_ID: " ".join(result[self.COMMENT_ID]) - if self.COMMENT_ID in result - else None, - } + return_dict = InstructionForm( + mnemonic=result["mnemonic"], + operands=operands, + comment_id=" ".join(result[self.comment_id]) if self.comment_id in result else None, ) return return_dict def process_operand(self, operand): """Post-process operand""" # structure memory addresses - if self.MEMORY_ID in operand: - return self.process_memory_address(operand[self.MEMORY_ID]) + if self.memory_id in operand: + return self.process_memory_address(operand[self.memory_id]) # structure register lists - if self.REGISTER_ID in operand and ( - "list" in operand[self.REGISTER_ID] or "range" in operand[self.REGISTER_ID] + if self.register_id in operand and ( + "list" in operand[self.register_id] or "range" in operand[self.register_id] ): # resolve ranges and lists - return self.resolve_range_list(self.process_register_list(operand[self.REGISTER_ID])) - if self.REGISTER_ID in operand and operand[self.REGISTER_ID]["name"].lower() == "sp": - return self.process_sp_register(operand[self.REGISTER_ID]) + return self.resolve_range_list(self.process_register_list(operand[self.register_id])) + if self.register_id in operand and operand[self.register_id]["name"].lower() == "sp": + return self.process_sp_register(operand[self.register_id]) # add value attribute to floating point immediates without exponent - if self.IMMEDIATE_ID in operand: - return self.process_immediate(operand[self.IMMEDIATE_ID]) - if self.LABEL_ID in operand: - return self.process_label(operand[self.LABEL_ID]) - if self.IDENTIFIER_ID in operand: - return self.process_identifier(operand[self.IDENTIFIER_ID]) + if self.immediate_id in operand: + return self.process_immediate(operand[self.immediate_id]) + if self.label_id in operand: + return self.process_label(operand[self.label_id]) + if self.identifier in operand: + return self.process_identifier(operand[self.identifier]) + if self.register_id in operand: + return self.process_register_operand(operand[self.register_id]) + if self.directive_id in operand: + return self.process_directive_operand(operand[self.directive_id]) + if self.condition_id in operand: + return self.process_condition(operand[self.condition_id]) + if self.prefetch in operand: + return self.process_prefetch_operand(operand[self.prefetch]) return operand + def process_prefetch_operand(self, operand): + return PrefetchOperand( + type_id=operand["type"] if "type" in operand else None, + target=operand["target"] if "target" in operand else None, + policy=operand["policy"] if "policy" in operand else None, + ) + + def process_directive_operand(self, operand): + return ( + DirectiveOperand( + name=operand["name"], + parameters=operand["parameters"], + ), + operand["comment"] if "comment" in operand else None, + ) + + def process_register_operand(self, operand): + return RegisterOperand( + prefix=operand["prefix"], + name=operand["name"], + shape=operand["shape"] if "shape" in operand else None, + lanes=operand["lanes"] if "lanes" in operand else None, + index=operand["index"] if "index" in operand else None, + predication=operand["predication"] if "predication" in operand else None, + ) + def process_memory_address(self, memory_address): """Post-process memory address operand""" # Remove unnecessarily created dictionary entries during parsing @@ -400,7 +426,9 @@ class ParserAArch64(BaseParser): if isinstance(offset, list) and len(offset) == 1: offset = offset[0] if offset is not None and "value" in offset: - offset["value"] = int(offset["value"], 0) + offset = ImmediateOperand(value=int(offset["value"], 0)) + if isinstance(offset, dict) and "identifier" in offset: + offset = self.process_identifier(offset["identifier"]) base = memory_address.get("base", None) index = memory_address.get("index", None) scale = 1 @@ -417,52 +445,69 @@ class ParserAArch64(BaseParser): if "shift" in memory_address["index"]: if memory_address["index"]["shift_op"].lower() in valid_shift_ops: scale = 2 ** int(memory_address["index"]["shift"][0]["value"]) - new_dict = AttrDict({"offset": offset, "base": base, "index": index, "scale": scale}) + if index is not None: + index = RegisterOperand( + name=index["name"], + prefix=index["prefix"] if "prefix" in index else None, + shift=index["shift"] if "shift" in index else None, + shift_op=index["shift_op"] if "shift_op" in index else None, + ) + new_dict = MemoryOperand( + offset=offset, + base=RegisterOperand(name=base["name"], prefix=base["prefix"]), + index=index, + scale=scale, + ) if "pre_indexed" in memory_address: - new_dict["pre_indexed"] = True + new_dict.pre_indexed = True if "post_indexed" in memory_address: if "value" in memory_address["post_indexed"]: - new_dict["post_indexed"] = { - "value": int(memory_address["post_indexed"]["value"], 0) - } + new_dict.post_indexed = {"value": int(memory_address["post_indexed"]["value"], 0)} else: - new_dict["post_indexed"] = memory_address["post_indexed"] - return AttrDict({self.MEMORY_ID: new_dict}) + new_dict.post_indexed = memory_address["post_indexed"] + return new_dict def process_sp_register(self, register): """Post-process stack pointer register""" - reg = register - reg["prefix"] = "x" - return AttrDict({self.REGISTER_ID: reg}) + return RegisterOperand(prefix="x", name="sp") + + def process_condition(self, condition): + return ConditionOperand(ccode=condition.upper()) def resolve_range_list(self, operand): """ Resolve range or list register operand to list of registers. Returns None if neither list nor range """ - if "register" in operand: - if "list" in operand.register: - index = operand.register.get("index") - range_list = [] - for reg in operand.register.list: - reg = deepcopy(reg) - if index is not None: - reg["index"] = int(index, 0) - range_list.append(AttrDict({self.REGISTER_ID: reg})) - return range_list - elif "range" in operand.register: - base_register = operand.register.range[0] - index = operand.register.get("index") - range_list = [] - start_name = base_register.name - end_name = operand.register.range[1].name - for name in range(int(start_name), int(end_name) + 1): - reg = deepcopy(base_register) - if index is not None: - reg["index"] = int(index, 0) - reg["name"] = str(name) - range_list.append(AttrDict({self.REGISTER_ID: reg})) - return range_list + if "list" in operand["register"]: + index = operand["register"].get("index", None) + range_list = [] + processed_list = [] + for reg in operand["register"]["list"]: + reg = deepcopy(reg) + if index is not None: + reg["index"] = int(index, 0) + range_list.append(reg) + for reg in range_list: + processed_list.append(self.process_register_operand(reg)) + return processed_list + # return range_list + elif "range" in operand["register"]: + base_register = operand["register"]["range"][0] + index = operand["register"].get("index", None) + range_list = [] + processed_list = [] + start_name = base_register["name"] + end_name = operand["register"]["range"][1]["name"] + for name in range(int(start_name), int(end_name) + 1): + reg = deepcopy(base_register) + if index is not None: + reg["index"] = int(index, 0) + reg["name"] = str(name) + range_list.append(reg) + for reg in range_list: + processed_list.append(self.process_register_operand(reg)) + return processed_list # neither register list nor range, return unmodified return operand @@ -476,86 +521,88 @@ class ParserAArch64(BaseParser): if "range" in register_list: dict_name = "range" for r in register_list[dict_name]: - rlist.append( - AttrDict.convert_dict(self.list_element.parseString(r, parseAll=True).asDict()) - ) + rlist.append(self.list_element.parseString(r, parseAll=True).asDict()) index = register_list.get("index", None) - new_dict = AttrDict({dict_name: rlist, "index": index}) - if len(new_dict[dict_name]) == 1: - return AttrDict({self.REGISTER_ID: new_dict[dict_name][0]}) - return AttrDict({self.REGISTER_ID: new_dict}) + new_dict = {dict_name: rlist, "index": index} + return {self.register_id: new_dict} def process_immediate(self, immediate): """Post-process immediate operand""" dict_name = "" if "identifier" in immediate: # actually an identifier, change declaration - return immediate + return self.process_identifier(immediate["identifier"]) if "value" in immediate: # normal integer value immediate["type"] = "int" # convert hex/bin immediates to dec - immediate["value"] = self.normalize_imd(immediate) - return AttrDict({self.IMMEDIATE_ID: immediate}) + new_immediate = ImmediateOperand(imd_type=immediate["type"], value=immediate["value"]) + new_immediate.value = self.normalize_imd(new_immediate) + return new_immediate if "base_immediate" in immediate: # arithmetic immediate, add calculated value as value immediate["shift"] = immediate["shift"][0] - immediate["value"] = self.normalize_imd(immediate["base_immediate"]) << int( + temp_immediate = ImmediateOperand(value=immediate["base_immediate"]["value"]) + immediate["type"] = "int" + new_immediate = ImmediateOperand( + imd_type=immediate["type"], value=None, shift=immediate["shift"] + ) + new_immediate.value = self.normalize_imd(temp_immediate) << int( immediate["shift"]["value"] ) - immediate["type"] = "int" - return AttrDict({self.IMMEDIATE_ID: immediate}) + return new_immediate if "float" in immediate: dict_name = "float" if "double" in immediate: dict_name = "double" if "exponent" in immediate[dict_name]: immediate["type"] = dict_name - return AttrDict({self.IMMEDIATE_ID: immediate}) + return ImmediateOperand(imd_type=immediate["type"], value=immediate[immediate["type"]]) else: # change 'mantissa' key to 'value' - return AttrDict( - { - self.IMMEDIATE_ID: AttrDict( - {"value": immediate[dict_name]["mantissa"], "type": dict_name} - ) - } - ) + return ImmediateOperand(value=immediate[dict_name]["mantissa"], imd_type=dict_name) def process_label(self, label): """Post-process label asm line""" # remove duplicated 'name' level due to identifier - label["name"] = label["name"]["name"] - return AttrDict({self.LABEL_ID: label}) + return ( + LabelOperand(name=label["name"]["name"]), + label["comment"] if self.comment_id in label else None, + ) def process_identifier(self, identifier): """Post-process identifier operand""" - # remove value if it consists of symbol+offset - if "value" in identifier: - del identifier["value"] - return AttrDict({self.IDENTIFIER_ID: identifier}) + return IdentifierOperand( + name=identifier["name"] if "name" in identifier else None, + offset=identifier["offset"] if "offset" in identifier else None, + relocation=identifier["relocation"] if "relocation" in identifier else None, + ) def get_full_reg_name(self, register): """Return one register name string including all attributes""" - name = register["prefix"] + str(register["name"]) - if "shape" in register: - name += "." + str(register.get("lanes", "")) + register["shape"] - if "index" in register: - name += "[" + register["index"] + "]" + name = register.prefix + str(register.name) + if register.shape is not None: + name += ( + "." + str(register.lanes if register.lanes is not None else "") + register.shape + ) + if register.index is not None: + name += "[" + str(register.index) + "]" return name def normalize_imd(self, imd): """Normalize immediate to decimal based representation""" - if "value" in imd: - if isinstance(imd["value"], str): + if isinstance(imd, IdentifierOperand): + return imd + if imd.value is not None and imd.imd_type == "float": + return self.ieee_to_float(imd.value) + elif imd.value is not None and imd.imd_type == "double": + return self.ieee_to_float(imd.value) + elif imd.value is not None: + if isinstance(imd.value, str): # hex or bin, return decimal - return int(imd["value"], 0) + return int(imd.value, 0) else: - return imd["value"] - elif "float" in imd: - return self.ieee_to_float(imd["float"]) - elif "double" in imd: - return self.ieee_to_float(imd["double"]) + return imd.value # identifier return imd @@ -571,13 +618,13 @@ class ParserAArch64(BaseParser): def is_gpr(self, register): """Check if register is a general purpose register""" - if register["prefix"] in "wx": + if register.prefix in "wx": return True return False def is_vector_register(self, register): """Check if register is a vector register""" - if register["prefix"] in "bhsdqvz": + if register.prefix in "bhsdqvz": return True return False @@ -585,21 +632,23 @@ class ParserAArch64(BaseParser): """Check if ``flag_a`` is dependent on ``flag_b``""" # we assume flags are independent of each other, e.g., CF can be read while ZF gets written # TODO validate this assumption - if flag_a["name"] == flag_b["name"]: - return True - return False + return flag_a.name == flag_b.name def is_reg_dependend_of(self, reg_a, reg_b): """Check if ``reg_a`` is dependent on ``reg_b``""" + # if not isinstance(reg_b, Operand): + # print(reg_b) + if not isinstance(reg_a, Operand): + reg_a = RegisterOperand(name=reg_a["name"]) prefixes_gpr = "wx" prefixes_vec = "bhsdqvz" - if reg_a["name"] == reg_b["name"]: - if reg_a["prefix"].lower() in prefixes_gpr and reg_b["prefix"].lower() in prefixes_gpr: + if reg_a.name == reg_b.name: + if reg_a.prefix.lower() in prefixes_gpr and reg_b.prefix.lower() in prefixes_gpr: return True - if reg_a["prefix"].lower() in prefixes_vec and reg_b["prefix"].lower() in prefixes_vec: + if reg_a.prefix.lower() in prefixes_vec and reg_b.prefix.lower() in prefixes_vec: return True return False def get_reg_type(self, register): """Get register type""" - return register["prefix"] + return register.prefix diff --git a/osaca/parser/parser_x86att.py b/osaca/parser/parser_x86att.py old mode 100755 new mode 100644 index 8739e00..c6d67b8 --- a/osaca/parser/parser_x86att.py +++ b/osaca/parser/parser_x86att.py @@ -5,7 +5,14 @@ import re import pyparsing as pp -from osaca.parser import AttrDict, BaseParser +from osaca.parser import BaseParser +from osaca.parser.instruction_form import InstructionForm +from osaca.parser.directive import DirectiveOperand +from osaca.parser.memory import MemoryOperand +from osaca.parser.label import LabelOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.identifier import IdentifierOperand +from osaca.parser.immediate import ImmediateOperand class ParserX86ATT(BaseParser): @@ -32,7 +39,7 @@ class ParserX86ATT(BaseParser): # Comment - either '#' or '//' (icc) self.comment = (pp.Literal("#") | pp.Literal("//")) + pp.Group( pp.ZeroOrMore(pp.Word(pp.printables)) - ).setResultsName(self.COMMENT_ID) + ).setResultsName(self.comment_id) # Define x86 assembly identifier relocation = pp.Combine(pp.Literal("@") + pp.Word(pp.alphas)) id_offset = pp.Word(pp.nums) + pp.Suppress(pp.Literal("+")) @@ -64,7 +71,7 @@ class ParserX86ATT(BaseParser): (label_identifier | numeric_identifier).setResultsName("name") + pp.Literal(":") + pp.Optional(self.comment) - ).setResultsName(self.LABEL_ID) + ).setResultsName(self.label_id) # Register: pp.Regex('^%[0-9a-zA-Z]+{}{z},?') self.register = pp.Group( pp.Literal("%") @@ -81,16 +88,16 @@ class ParserX86ATT(BaseParser): + pp.Suppress(pp.Literal("}")) ) ) - ).setResultsName(self.REGISTER_ID) + ).setResultsName(self.register_id) # Immediate: pp.Regex('^\$(-?[0-9]+)|(0x[0-9a-fA-F]+),?') symbol_immediate = "$" immediate = pp.Group( pp.Literal(symbol_immediate) + (hex_number | decimal_number | identifier) - ).setResultsName(self.IMMEDIATE_ID) + ).setResultsName(self.immediate_id) # Memory preparations offset = pp.Group(hex_number | decimal_number | identifier).setResultsName( - self.IMMEDIATE_ID + self.immediate_id ) scale = pp.Word("1248", exact=1) # Segment register extension @@ -112,7 +119,7 @@ class ParserX86ATT(BaseParser): pp.Optional(pp.Suppress(pp.Literal("*"))) + self.register.setResultsName("base") + pp.Literal(":") - + segment_extension.setResultsName(self.SEGMENT_EXT_ID) + + segment_extension.setResultsName(self.segment_ext) ) # Memory: offset | seg:seg_ext | offset(base, index, scale){mask} memory_abs = pp.Suppress(pp.Literal("*")) + (offset | self.register).setResultsName( @@ -139,7 +146,7 @@ class ParserX86ATT(BaseParser): | memory_abs | memory_segmentation | (hex_number | pp.Word(pp.nums)).setResultsName("offset") - ).setResultsName(self.MEMORY_ID) + ).setResultsName(self.memory_id) # Directive # parameter can be any quoted string or sequence of characters besides '#' (for comments) @@ -157,7 +164,7 @@ class ParserX86ATT(BaseParser): + pp.Word(pp.alphanums + "_").setResultsName("name") + pp.ZeroOrMore(directive_parameter).setResultsName("parameters") + pp.Optional(self.comment) - ).setResultsName(self.DIRECTIVE_ID) + ).setResultsName(self.directive_id) # Instructions # Mnemonic @@ -199,57 +206,41 @@ class ParserX86ATT(BaseParser): :type line_number: int, optional :return: ``dict`` -- parsed asm line (comment, label, directive or instruction form) """ - instruction_form = AttrDict( - { - self.INSTRUCTION_ID: None, - self.OPERANDS_ID: [], - self.DIRECTIVE_ID: None, - self.COMMENT_ID: None, - self.LABEL_ID: None, - "line": line, - "line_number": line_number, - } - ) + instruction_form = InstructionForm(line=line, line_number=line_number) result = None # 1. Parse comment try: result = self.process_operand(self.comment.parseString(line, parseAll=True).asDict()) - result = AttrDict.convert_dict(result) - instruction_form[self.COMMENT_ID] = " ".join(result[self.COMMENT_ID]) + instruction_form.comment = " ".join(result[self.comment_id]) except pp.ParseException: pass # 2. Parse label if result is None: try: + # returns tuple with label operand and comment, if any result = self.process_operand(self.label.parseString(line, parseAll=True).asDict()) - result = AttrDict.convert_dict(result) - instruction_form[self.LABEL_ID] = result[self.LABEL_ID]["name"] - if self.COMMENT_ID in result[self.LABEL_ID]: - instruction_form[self.COMMENT_ID] = " ".join( - result[self.LABEL_ID][self.COMMENT_ID] - ) + instruction_form.label = result[0].name + if result[1] is not None: + instruction_form.comment = " ".join(result[1]) except pp.ParseException: pass # 3. Parse directive if result is None: try: + # returns tuple with directive operand and comment, if any result = self.process_operand( self.directive.parseString(line, parseAll=True).asDict() ) - result = AttrDict.convert_dict(result) - instruction_form[self.DIRECTIVE_ID] = AttrDict( - { - "name": result[self.DIRECTIVE_ID]["name"], - "parameters": result[self.DIRECTIVE_ID]["parameters"], - } + instruction_form.directive = DirectiveOperand( + name=result[0].name, + parameters=result[0].parameters, ) - if self.COMMENT_ID in result[self.DIRECTIVE_ID]: - instruction_form[self.COMMENT_ID] = " ".join( - result[self.DIRECTIVE_ID][self.COMMENT_ID] - ) + + if result[1] is not None: + instruction_form.comment = " ".join(result[1]) except pp.ParseException: pass @@ -261,10 +252,9 @@ class ParserX86ATT(BaseParser): raise ValueError( "Could not parse instruction on line {}: {!r}".format(line_number, line) ) - instruction_form[self.INSTRUCTION_ID] = result[self.INSTRUCTION_ID] - instruction_form[self.OPERANDS_ID] = result[self.OPERANDS_ID] - instruction_form[self.COMMENT_ID] = result[self.COMMENT_ID] - + instruction_form.mnemonic = result.mnemonic + instruction_form.operands = result.operands + instruction_form.comment = result.comment return instruction_form def parse_instruction(self, instruction): @@ -275,7 +265,6 @@ class ParserX86ATT(BaseParser): :returns: `dict` -- parsed instruction form """ result = self.instruction_parser.parseString(instruction, parseAll=True).asDict() - result = AttrDict.convert_dict(result) operands = [] # Add operands to list # Check first operand @@ -290,86 +279,113 @@ class ParserX86ATT(BaseParser): # Check fourth operand if "operand4" in result: operands.append(self.process_operand(result["operand4"])) - return_dict = AttrDict( - { - self.INSTRUCTION_ID: result["mnemonic"].split(",")[0], - self.OPERANDS_ID: operands, - self.COMMENT_ID: " ".join(result[self.COMMENT_ID]) - if self.COMMENT_ID in result - else None, - } + return_dict = InstructionForm( + mnemonic=result["mnemonic"].split(",")[0], + operands=operands, + comment_id=" ".join(result[self.comment_id]) if self.comment_id in result else None, ) + return return_dict def process_operand(self, operand): """Post-process operand""" # For the moment, only used to structure memory addresses - if self.MEMORY_ID in operand: - return self.process_memory_address(operand[self.MEMORY_ID]) - if self.IMMEDIATE_ID in operand: - return self.process_immediate(operand[self.IMMEDIATE_ID]) - if self.LABEL_ID in operand: - return self.process_label(operand[self.LABEL_ID]) - if self.DIRECTIVE_ID in operand: - return self.process_directive(operand[self.DIRECTIVE_ID]) + if self.memory_id in operand: + return self.process_memory_address(operand[self.memory_id]) + if self.immediate_id in operand: + return self.process_immediate(operand[self.immediate_id]) + if self.label_id in operand: + return self.process_label(operand[self.label_id]) + if self.directive_id in operand: + return self.process_directive(operand[self.directive_id]) + if self.register_id in operand: + return self.process_register(operand[self.register_id]) + if self.identifier in operand: + return self.process_identifier(operand[self.identifier]) return operand + def process_register(self, operand): + return RegisterOperand( + prefix=operand["prefix"] if "prefix" in operand else None, + name=operand["name"], + shape=operand["shape"] if "shape" in operand else None, + lanes=operand["lanes"] if "lanes" in operand else None, + index=operand["index"] if "index" in operand else None, + predication=operand["predication"] if "predication" in operand else None, + ) + def process_directive(self, directive): - directive_new = {"name": directive["name"], "parameters": []} - if "parameters" in directive: - directive_new["parameters"] = directive["parameters"] - if "comment" in directive: - directive_new["comment"] = directive["comment"] - return AttrDict({self.DIRECTIVE_ID: directive_new}) + directive_new = DirectiveOperand( + name=directive["name"], + parameters=directive["parameters"] if "parameters" in directive else [], + ) + return directive_new, directive["comment"] if "comment" in directive else None def process_memory_address(self, memory_address): """Post-process memory address operand""" # Remove unecessarily created dictionary entries during memory address parsing offset = memory_address.get("offset", None) base = memory_address.get("base", None) + baseOp = None + indexOp = None index = memory_address.get("index", None) scale = 1 if "scale" not in memory_address else int(memory_address["scale"], 0) if isinstance(offset, str) and base is None and index is None: try: - offset = {"value": int(offset, 0)} + offset = ImmediateOperand(value=int(offset, 0)) except ValueError: - offset = {"value": offset} + offset = ImmediateOperand(value=offset) elif offset is not None and "value" in offset: - offset["value"] = int(offset["value"], 0) - new_dict = AttrDict({"offset": offset, "base": base, "index": index, "scale": scale}) + offset = ImmediateOperand(value=int(offset["value"], 0)) + if base is not None: + baseOp = RegisterOperand( + name=base["name"], prefix=base["prefix"] if "prefix" in base else None + ) + if index is not None: + indexOp = RegisterOperand( + name=index["name"], prefix=index["prefix"] if "prefix" in index else None + ) + if isinstance(offset, dict) and "identifier" in offset: + offset = IdentifierOperand(name=offset["identifier"]["name"]) + new_dict = MemoryOperand(offset=offset, base=baseOp, index=indexOp, scale=scale) # Add segmentation extension if existing - if self.SEGMENT_EXT_ID in memory_address: - new_dict[self.SEGMENT_EXT_ID] = memory_address[self.SEGMENT_EXT_ID] - return AttrDict({self.MEMORY_ID: new_dict}) + if self.segment_ext in memory_address: + new_dict.segment_ext = memory_address[self.segment_ext] + return new_dict def process_label(self, label): """Post-process label asm line""" # remove duplicated 'name' level due to identifier label["name"] = label["name"][0]["name"] - return AttrDict({self.LABEL_ID: label}) + return LabelOperand(name=label["name"]), label["comment"] if "comment" in label else None def process_immediate(self, immediate): """Post-process immediate operand""" if "identifier" in immediate: # actually an identifier, change declaration - return immediate + return self.process_identifier(immediate["identifier"]) # otherwise just make sure the immediate is a decimal - immediate["value"] = int(immediate["value"], 0) - return AttrDict({self.IMMEDIATE_ID: immediate}) + new_immediate = ImmediateOperand(value=int(immediate["value"], 0)) + return new_immediate + + def process_identifier(self, identifier): + return IdentifierOperand(name=identifier["name"]) def get_full_reg_name(self, register): """Return one register name string including all attributes""" # nothing to do - return register["name"] + return register.name def normalize_imd(self, imd): """Normalize immediate to decimal based representation""" - if "value" in imd: - if isinstance(imd["value"], str): + if isinstance(imd, IdentifierOperand): + return imd + if imd.value is not None: + if isinstance(imd.value, str): # return decimal - return int(imd["value"], 0) + return int(imd.value, 0) else: - return imd["value"] + return imd.value # identifier return imd @@ -377,15 +393,12 @@ class ParserX86ATT(BaseParser): """Check if ``flag_a`` is dependent on ``flag_b``""" # we assume flags are independent of each other, e.g., CF can be read while ZF gets written # TODO validate this assumption - if flag_a.name == flag_b.name: - return True - return False + return flag_a.name == flag_b.name def is_reg_dependend_of(self, reg_a, reg_b): """Check if ``reg_a`` is dependent on ``reg_b``""" - # Normalize name - reg_a_name = reg_a["name"].upper() - reg_b_name = reg_b["name"].upper() + reg_a_name = reg_a.name.upper() + reg_b_name = reg_b.name.upper() # Check if they are the same registers if reg_a_name == reg_b_name: @@ -426,8 +439,8 @@ class ParserX86ATT(BaseParser): def is_basic_gpr(self, register): """Check if register is a basic general purpose register (ebi, rax, ...)""" - if any(char.isdigit() for char in register["name"]) or any( - register["name"].lower().startswith(x) for x in ["mm", "xmm", "ymm", "zmm"] + if any(char.isdigit() for char in register.name) or any( + register.name.lower().startswith(x) for x in ["mm", "xmm", "ymm", "zmm"] ): return False return True @@ -438,13 +451,13 @@ class ParserX86ATT(BaseParser): return False if self.is_basic_gpr(register): return True - return re.match(r"R([0-9]+)[DWB]?", register["name"], re.IGNORECASE) + return re.match(r"R([0-9]+)[DWB]?", register.name, re.IGNORECASE) def is_vector_register(self, register): """Check if register is a vector register""" - if register is None: + if register is None or register.name is None: return False - if register["name"].rstrip(string.digits).lower() in [ + if register.name.rstrip(string.digits).lower() in [ "mm", "xmm", "ymm", @@ -460,5 +473,5 @@ class ParserX86ATT(BaseParser): if self.is_gpr(register): return "gpr" elif self.is_vector_register(register): - return register["name"].rstrip(string.digits).lower() + return register.name.rstrip(string.digits).lower() raise ValueError diff --git a/osaca/parser/prefetch.py b/osaca/parser/prefetch.py new file mode 100644 index 0000000..5455c4d --- /dev/null +++ b/osaca/parser/prefetch.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class PrefetchOperand(Operand): + def __init__(self, type_id=None, target=None, policy=None): + self._type_id = type_id + self._target = target + self._policy = policy + + @property + def type_id(self): + return self._type_id + + @type_id.setter + def type_id(self, type_id): + self._type_id = type_id + + @property + def target(self): + return self._target + + @target.setter + def target(self, target): + self._target = target + + @property + def policy(self): + return self._policy + + @policy.setter + def policy(self, policy): + self._policy = policy + + def __str__(self): + return f"Label(type_id={self._type_id},target={self._target},policy={self._policy})" + + def __repr__(self): + return self.__str__() diff --git a/osaca/parser/register.py b/osaca/parser/register.py new file mode 100644 index 0000000..23d4778 --- /dev/null +++ b/osaca/parser/register.py @@ -0,0 +1,179 @@ +#!/usr/bin/env python3 + +from osaca.parser.operand import Operand + + +class RegisterOperand(Operand): + def __init__( + self, + name=None, + width=None, + prefix=None, + regtype=None, + lanes=None, + shape=None, + index=None, + mask=False, + zeroing=False, + predication=None, + source=False, + destination=False, + pre_indexed=False, + post_indexed=False, + shift=False, + shift_op=False, + ): + super().__init__(source, destination) + self._name = name + self._width = width + self._prefix = prefix + self._regtype = regtype + self._lanes = lanes + self._shape = shape + self._index = index + self._mask = mask + self._zeroing = zeroing + self._predication = predication + self._pre_indexed = pre_indexed + self._post_indexed = post_indexed + self._shift = shift + self._shift_op = shift_op + + @property + def name(self): + return self._name + + @name.setter + def name(self, name): + self._name = name + + @property + def width(self): + return self._width + + @width.setter + def width(self, width): + self._width = width + + @property + def shift(self): + return self._shift + + @shift.setter + def shift(self, shift): + self._shift = shift + + @property + def shift_op(self): + return self._shift_op + + @shift_op.setter + def shift_op(self, shift_op): + self._shift_op = shift_op + + @property + def predication(self): + return self._predication + + @predication.setter + def predication(self, predication): + self._predication = predication + + @property + def pre_indexed(self): + return self._pre_indexed + + @property + def post_indexed(self): + return self._post_indexed + + @property + def prefix(self): + return self._prefix + + @prefix.setter + def prefix(self, prefix): + self._prefix = prefix + + @property + def regtype(self): + return self._regtype + + @regtype.setter + def regtype(self, regtype): + self._regtype = regtype + + @property + def lanes(self): + return self._lanes + + @lanes.setter + def lanes(self, lanes): + self._lanes = lanes + + @property + def shape(self): + return self._shape + + @shape.setter + def shape(self, shape): + self._shape = shape + + @property + def index(self): + return self._index + + @index.setter + def index(self, index): + self._index = index + + @property + def mask(self): + return self._mask + + @mask.setter + def mask(self, mask): + self._mask = mask + + @pre_indexed.setter + def pre_indexed(self, pre_indexed): + self._pre_indexed = pre_indexed + + @post_indexed.setter + def post_indexed(self, post_indexed): + self._post_indexed = post_indexed + + @property + def zeroing(self): + return self._zeroing + + @zeroing.setter + def zeroing(self, zeroing): + self._zeroing = zeroing + + def __str__(self): + return ( + f"Register(name={self._name}, width={self._width}, " + f"prefix={self._prefix}, regtype={self._regtype}, " + f"lanes={self._lanes}, shape={self._shape}, index={self._index}, " + f"mask={self._mask}, zeroing={self._zeroing},source={self._source},destination={self._destination}," + f"pre_indexed={self._pre_indexed}, post_indexed={self._post_indexed}) " + ) + + def __repr__(self): + return self.__str__() + + def __eq__(self, other): + if isinstance(other, RegisterOperand): + return ( + self._name == other._name + and self._width == other._width + and self._prefix == other._prefix + and self._regtype == other._regtype + and self._lanes == other._lanes + and self._shape == other._shape + and self._index == other._index + and self._mask == other._mask + and self._zeroing == other._zeroing + ) + return False diff --git a/osaca/semantics/__init__.py b/osaca/semantics/__init__.py index 8a0b000..47baf9e 100644 --- a/osaca/semantics/__init__.py +++ b/osaca/semantics/__init__.py @@ -3,6 +3,7 @@ Tools for semantic analysis of parser result. Only the classes below will be exported, so please add new semantic tools to __all__. """ + from .isa_semantics import ISASemantics, INSTR_FLAGS from .arch_semantics import ArchSemantics from .hw_model import MachineModel diff --git a/osaca/semantics/arch_semantics.py b/osaca/semantics/arch_semantics.py old mode 100755 new mode 100644 index 4be77ad..e87e5e7 --- a/osaca/semantics/arch_semantics.py +++ b/osaca/semantics/arch_semantics.py @@ -9,6 +9,8 @@ from copy import deepcopy from .hw_model import MachineModel from .isa_semantics import INSTR_FLAGS, ISASemantics +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand class ArchSemantics(ISASemantics): @@ -46,14 +48,14 @@ class ArchSemantics(ISASemantics): for idx, instruction_form in enumerate(kernel[start:], start): multiple_assignments = False # if iform has multiple possible port assignments, check all in a DFS manner and take the best - if isinstance(instruction_form["port_uops"], dict): + if isinstance(instruction_form.port_uops, dict): best_kernel = None best_kernel_tp = sys.maxsize - for port_util_alt in list(instruction_form["port_uops"].values())[1:]: + for port_util_alt in list(instruction_form.port_uops.values())[1:]: k_tmp = deepcopy(kernel) - k_tmp[idx]["port_uops"] = deepcopy(port_util_alt) - k_tmp[idx]["port_pressure"] = self._machine_model.average_port_pressure( - k_tmp[idx]["port_uops"] + k_tmp[idx].port_uops = deepcopy(port_util_alt) + k_tmp[idx].port_pressure = self._machine_model.average_port_pressure( + k_tmp[idx].port_uops ) k_tmp.reverse() self.assign_optimal_throughput(k_tmp, idx) @@ -62,16 +64,14 @@ class ArchSemantics(ISASemantics): best_kernel_tp = max(self.get_throughput_sum(best_kernel)) # check the first option in the main branch and compare against the best option later multiple_assignments = True - kernel[idx]["port_uops"] = list(instruction_form["port_uops"].values())[0] - for uop in instruction_form["port_uops"]: + kernel[idx].port_uops = list(instruction_form.port_uops.values())[0] + for uop in instruction_form.port_uops: cycles = uop[0] ports = list(uop[1]) indices = [port_list.index(p) for p in ports] # check if port sum of used ports for uop are unbalanced port_sums = self._to_list(itemgetter(*indices)(self.get_throughput_sum(kernel))) - instr_ports = self._to_list( - itemgetter(*indices)(instruction_form["port_pressure"]) - ) + instr_ports = self._to_list(itemgetter(*indices)(instruction_form.port_pressure)) if len(set(port_sums)) > 1: # balance ports # init list for keeping track of the current change @@ -87,7 +87,7 @@ class ArchSemantics(ISASemantics): differences[max_port_idx] -= INC differences[min_port_idx] += INC # instr_ports = [round(p, 2) for p in instr_ports] - self._itemsetter(*indices)(instruction_form["port_pressure"], *instr_ports) + self._itemsetter(*indices)(instruction_form.port_pressure, *instr_ports) # check if min port is zero if round(min(instr_ports), 2) <= 0: # if port_pressure is not exactly 0.00, add the residual to @@ -100,21 +100,19 @@ class ArchSemantics(ISASemantics): # delete it del differences[instr_ports.index(min(instr_ports))] self._itemsetter(*indices)( - instruction_form["port_pressure"], *instr_ports + instruction_form.port_pressure, *instr_ports ) zero_index = [ p for p in indices - if round(instruction_form["port_pressure"][p], 2) == 0 - or instruction_form["port_pressure"][p] < 0.00 + if round(instruction_form.port_pressure[p], 2) == 0 + or instruction_form.port_pressure[p] < 0.00 ][0] - instruction_form["port_pressure"][zero_index] = 0.0 + instruction_form.port_pressure[zero_index] = 0.0 # Remove from further balancing - indices = [ - p for p in indices if instruction_form["port_pressure"][p] > 0 - ] + indices = [p for p in indices if instruction_form.port_pressure[p] > 0] instr_ports = self._to_list( - itemgetter(*indices)(instruction_form["port_pressure"]) + itemgetter(*indices)(instruction_form.port_pressure) ) # never remove more than the fixed utilization per uop and port, i.e., # cycles/len(ports) @@ -124,7 +122,7 @@ class ArchSemantics(ISASemantics): # pressure is not 0 del indices[differences.index(min(differences))] instr_ports = self._to_list( - itemgetter(*indices)(instruction_form["port_pressure"]) + itemgetter(*indices)(instruction_form.port_pressure) ) del differences[differences.index(min(differences))] port_sums = self._to_list( @@ -134,19 +132,19 @@ class ArchSemantics(ISASemantics): if multiple_assignments: if max(self.get_throughput_sum(kernel)) > best_kernel_tp: for i, instr in enumerate(best_kernel): - kernel[i]["port_uops"] = best_kernel[i]["port_uops"] - kernel[i]["port_pressure"] = best_kernel[i]["port_pressure"] + kernel[i].port_uops = best_kernel[i].port_uops + kernel[i].port_pressure = best_kernel[i].port_pressure def set_hidden_loads(self, kernel): """Hide loads behind stores if architecture supports hidden loads (depricated)""" - loads = [instr for instr in kernel if INSTR_FLAGS.HAS_LD in instr["flags"]] - stores = [instr for instr in kernel if INSTR_FLAGS.HAS_ST in instr["flags"]] + loads = [instr for instr in kernel if INSTR_FLAGS.HAS_LD in instr.flags] + stores = [instr for instr in kernel if INSTR_FLAGS.HAS_ST in instr.flags] # Filter instructions including load and store - load_ids = [instr["line_number"] for instr in loads] - store_ids = [instr["line_number"] for instr in stores] + load_ids = [instr.line_number for instr in loads] + store_ids = [instr.line_number for instr in stores] shared_ldst = list(set(load_ids).intersection(set(store_ids))) - loads = [instr for instr in loads if instr["line_number"] not in shared_ldst] - stores = [instr for instr in stores if instr["line_number"] not in shared_ldst] + loads = [instr for instr in loads if instr.line_number not in shared_ldst] + stores = [instr for instr in stores if instr.line_number not in shared_ldst] if len(stores) == 0 or len(loads) == 0: # nothing to do @@ -154,27 +152,25 @@ class ArchSemantics(ISASemantics): if len(loads) <= len(stores): # Hide all loads for load in loads: - load["flags"] += [INSTR_FLAGS.HIDDEN_LD] - load["port_pressure"] = self._nullify_data_ports(load["port_pressure"]) + load.flags += [INSTR_FLAGS.HIDDEN_LD] + load.port_pressure = self._nullify_data_ports(load.port_pressure) else: for store in stores: # Get 'closest' load instruction min_distance_load = min( [ ( - abs(load_instr["line_number"] - store["line_number"]), - load_instr["line_number"], + abs(load_instr.line_number - store.line_number), + load_instr.line_number, ) for load_instr in loads - if INSTR_FLAGS.HIDDEN_LD not in load_instr["flags"] + if INSTR_FLAGS.HIDDEN_LD not in load_instr.flags ] ) - load = [instr for instr in kernel if instr["line_number"] == min_distance_load[1]][ - 0 - ] + load = [instr for instr in kernel if instr.line_number == min_distance_load[1]][0] # Hide load - load["flags"] += [INSTR_FLAGS.HIDDEN_LD] - load["port_pressure"] = self._nullify_data_ports(load["port_pressure"]) + load.flags += [INSTR_FLAGS.HIDDEN_LD] + load.port_pressure = self._nullify_data_ports(load.port_pressure) # get parser result and assign throughput and latency value to instruction form # mark instruction form with semantic flags @@ -182,35 +178,35 @@ class ArchSemantics(ISASemantics): """Assign throughput and latency to an instruction form.""" flags = [] port_number = len(self._machine_model["ports"]) - if instruction_form["instruction"] is None: + if instruction_form.mnemonic is None: # No instruction (label, comment, ...) --> ignore throughput = 0.0 latency = 0.0 latency_wo_load = latency - instruction_form["port_pressure"] = [0.0 for i in range(port_number)] - instruction_form["port_uops"] = [] + instruction_form.port_pressure = [0.0 for i in range(port_number)] + instruction_form.port_uops = [] else: instruction_data = self._machine_model.get_instruction( - instruction_form["instruction"], instruction_form["operands"] + instruction_form.mnemonic, instruction_form.operands ) if ( not instruction_data and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES + and instruction_form.mnemonic[-1] in self.GAS_SUFFIXES ): # check for instruction without GAS suffix instruction_data = self._machine_model.get_instruction( - instruction_form["instruction"][:-1], instruction_form["operands"] + instruction_form.mnemonic[:-1], instruction_form.operands ) if ( instruction_data is None and self._isa == "aarch64" - and "." in instruction_form["instruction"] + and "." in instruction_form.mnemonic ): # Check for instruction without shape/cc suffix - suffix_start = instruction_form["instruction"].index(".") + suffix_start = instruction_form.mnemonic.index(".") instruction_data = self._machine_model.get_instruction( - instruction_form["instruction"][:suffix_start], instruction_form["operands"] + instruction_form.mnemonic[:suffix_start], instruction_form.operands ) if instruction_data: # instruction form in DB @@ -227,65 +223,66 @@ class ArchSemantics(ISASemantics): assign_unknown = True # check for equivalent register-operands DB entry if LD if ( - INSTR_FLAGS.HAS_LD in instruction_form["flags"] - or INSTR_FLAGS.HAS_ST in instruction_form["flags"] + INSTR_FLAGS.HAS_LD in instruction_form.flags + or INSTR_FLAGS.HAS_ST in instruction_form.flags ): # dynamically combine LD/ST and reg form of instruction form # substitute mem and look for reg-only variant - operands = self.substitute_mem_address(instruction_form["operands"]) + operands = self.substitute_mem_address(instruction_form.operands) instruction_data_reg = self._machine_model.get_instruction( - instruction_form["instruction"], operands + instruction_form.mnemonic, operands ) if ( not instruction_data_reg and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES + and instruction_form.mnemonic[-1] in self.GAS_SUFFIXES ): # check for instruction without GAS suffix instruction_data_reg = self._machine_model.get_instruction( - instruction_form["instruction"][:-1], operands + instruction_form.mnemonic[:-1], operands ) if ( instruction_data_reg is None and self._isa == "aarch64" - and "." in instruction_form["instruction"] + and "." in instruction_form.mnemonic ): # Check for instruction without shape/cc suffix - suffix_start = instruction_form["instruction"].index(".") + suffix_start = instruction_form.mnemonic.index(".") instruction_data_reg = self._machine_model.get_instruction( - instruction_form["instruction"][:suffix_start], operands + instruction_form.mnemonic[:suffix_start], operands ) if instruction_data_reg: assign_unknown = False reg_type = self._parser.get_reg_type( - instruction_data_reg["operands"][ + instruction_data_reg.operands[ operands.index(self._create_reg_wildcard()) ] ) - dummy_reg = {"class": "register", "name": reg_type} + # dummy_reg = {"class": "register", "name": reg_type} + dummy_reg = RegisterOperand(name=reg_type) data_port_pressure = [0.0 for _ in range(port_number)] data_port_uops = [] - if INSTR_FLAGS.HAS_LD in instruction_form["flags"]: + if INSTR_FLAGS.HAS_LD in instruction_form.flags: # LOAD performance data load_perf_data = self._machine_model.get_load_throughput( [ - x["memory"] - for x in instruction_form["semantic_operands"]["source"] - + instruction_form["semantic_operands"]["src_dst"] - if "memory" in x + x + for x in instruction_form.semantic_operands["source"] + + instruction_form.semantic_operands["src_dst"] + if isinstance(x, MemoryOperand) ][0] ) # if multiple options, choose based on reg type data_port_uops = [ - ldp["port_pressure"] + ldp[1] for ldp in load_perf_data - if "dst" in ldp + if ldp[0].dst is not None and self._machine_model._check_operands( - dummy_reg, {"register": {"name": ldp["dst"]}} + dummy_reg, RegisterOperand(name=ldp[0].dst) ) ] if len(data_port_uops) < 1: - data_port_uops = load_perf_data[0]["port_pressure"] + data_port_uops = load_perf_data[0][1] else: data_port_uops = data_port_uops[0] data_port_pressure = self._machine_model.average_port_pressure( @@ -296,36 +293,38 @@ class ArchSemantics(ISASemantics): reg_type ] data_port_pressure = [pp * multiplier for pp in data_port_pressure] - if INSTR_FLAGS.HAS_ST in instruction_form["flags"]: + if INSTR_FLAGS.HAS_ST in instruction_form.flags: # STORE performance data destinations = ( - instruction_form["semantic_operands"]["destination"] - + instruction_form["semantic_operands"]["src_dst"] + instruction_form.semantic_operands["destination"] + + instruction_form.semantic_operands["src_dst"] ) store_perf_data = self._machine_model.get_store_throughput( - [x["memory"] for x in destinations if "memory" in x][0], dummy_reg + [x for x in destinations if isinstance(x, MemoryOperand)][0], + dummy_reg, ) - st_data_port_uops = store_perf_data[0]["port_pressure"] + st_data_port_uops = store_perf_data[0][1] # zero data port pressure and remove HAS_ST flag if # - no mem operand in dst && - # - all mem operands in src_dst are pre-/post-indexed + # - all mem operands in src_dst are pre-/post_indexed # since it is no mem store if ( self._isa == "aarch64" - and "memory" - not in instruction_form["semantic_operands"]["destination"] + and not isinstance( + instruction_form.semantic_operands["destination"], + MemoryOperand, + ) and all( [ - "post_indexed" in op["memory"] - or "pre_indexed" in op["memory"] - for op in instruction_form["semantic_operands"]["src_dst"] - if "memory" in op + op.post_indexed or op.pre_indexed + for op in instruction_form.semantic_operands["src_dst"] + if isinstance(op, MemoryOperand) ] ) ): st_data_port_uops = [] - instruction_form["flags"].remove(INSTR_FLAGS.HAS_ST) + instruction_form.flags.remove(INSTR_FLAGS.HAS_ST) # sum up all data ports in case for LOAD and STORE st_data_port_pressure = self._machine_model.average_port_pressure( @@ -342,23 +341,21 @@ class ArchSemantics(ISASemantics): sum(x) for x in zip(data_port_pressure, st_data_port_pressure) ] data_port_uops += st_data_port_uops - throughput = max( - max(data_port_pressure), instruction_data_reg["throughput"] - ) - latency = instruction_data_reg["latency"] + throughput = max(max(data_port_pressure), instruction_data_reg.throughput) + latency = instruction_data_reg.latency # Add LD and ST latency latency += ( self._machine_model.get_load_latency(reg_type) - if INSTR_FLAGS.HAS_LD in instruction_form["flags"] + if INSTR_FLAGS.HAS_LD in instruction_form.flags else 0 ) latency += ( self._machine_model.get_store_latency(reg_type) - if INSTR_FLAGS.HAS_ST in instruction_form["flags"] + if INSTR_FLAGS.HAS_ST in instruction_form.flags else 0 ) - latency_wo_load = instruction_data_reg["latency"] - # add latency of ADD if post- or pre-indexed load + latency_wo_load = instruction_data_reg.latency + # add latency of ADD if post- or pre_indexed load # TODO more investigation: check dot-graph, wrong latency distribution! # if ( # latency_wo_load == 0 @@ -367,23 +364,23 @@ class ArchSemantics(ISASemantics): # [ # 'post_indexed' in op['memory'] or # 'pre_indexed' in op['memory'] - # for op in instruction_form['operands'] + # for op in instruction_form.operands # if 'memory' in op # ] # ) # ): # latency_wo_load = 1.0 - instruction_form["port_pressure"] = [ + instruction_form.port_pressure = [ sum(x) for x in zip( data_port_pressure, self._machine_model.average_port_pressure( - instruction_data_reg["port_pressure"] + instruction_data_reg.port_pressure ), ) ] - instruction_form["port_uops"] = list( - chain(instruction_data_reg["port_pressure"], data_port_uops) + instruction_form.port_uops = list( + chain(instruction_data_reg.port_pressure, data_port_uops) ) if assign_unknown: @@ -391,33 +388,31 @@ class ArchSemantics(ISASemantics): throughput = 0.0 latency = 0.0 latency_wo_load = latency - instruction_form["port_pressure"] = [0.0 for i in range(port_number)] - instruction_form["port_uops"] = [] + instruction_form.port_pressure = [0.0 for i in range(port_number)] + # instruction_formport_uops = [] flags += [INSTR_FLAGS.TP_UNKWN, INSTR_FLAGS.LT_UNKWN] # flatten flag list flags = list(set(flags)) - if "flags" not in instruction_form: - instruction_form["flags"] = flags + if instruction_form.flags == []: + instruction_form.flags = flags else: - instruction_form["flags"] += flags - instruction_form["throughput"] = throughput - instruction_form["latency"] = latency - instruction_form["latency_wo_load"] = latency_wo_load + instruction_form.flags += flags + instruction_form.throughput = throughput + instruction_form.latency = latency + instruction_form.latency_wo_load = latency_wo_load # for later CP and loop-carried dependency analysis - instruction_form["latency_cp"] = 0 - instruction_form["latency_lcd"] = 0 + instruction_form.latency_cp = 0 + instruction_form.latency_lcd = 0 def _handle_instruction_found(self, instruction_data, port_number, instruction_form, flags): """Apply performance data to instruction if it was found in the archDB""" - throughput = instruction_data["throughput"] - port_pressure = self._machine_model.average_port_pressure( - instruction_data["port_pressure"] - ) - instruction_form["port_uops"] = instruction_data["port_pressure"] + throughput = instruction_data.throughput + port_pressure = self._machine_model.average_port_pressure(instruction_data.port_pressure) + instruction_form.port_uops = instruction_data.port_pressure try: assert isinstance(port_pressure, list) assert len(port_pressure) == port_number - instruction_form["port_pressure"] = port_pressure + instruction_form.port_pressure = port_pressure if sum(port_pressure) == 0 and throughput is not None: # port pressure on all ports 0 --> not bound to a port flags.append(INSTR_FLAGS.NOT_BOUND) @@ -426,33 +421,33 @@ class ArchSemantics(ISASemantics): "Port pressure could not be imported correctly from database. " + "Please check entry for:\n {}".format(instruction_form) ) - instruction_form["port_pressure"] = [0.0 for i in range(port_number)] - instruction_form["port_uops"] = [] + instruction_form.port_pressure = [0.0 for i in range(port_number)] + instruction_form.port_uops = [] flags.append(INSTR_FLAGS.TP_UNKWN) if throughput is None: # assume 0 cy and mark as unknown throughput = 0.0 flags.append(INSTR_FLAGS.TP_UNKWN) - latency = instruction_data["latency"] + latency = instruction_data.latency latency_wo_load = latency if latency is None: # assume 0 cy and mark as unknown latency = 0.0 latency_wo_load = latency flags.append(INSTR_FLAGS.LT_UNKWN) - if INSTR_FLAGS.HAS_LD in instruction_form["flags"]: + if INSTR_FLAGS.HAS_LD in instruction_form.flags: flags.append(INSTR_FLAGS.LD) return throughput, port_pressure, latency, latency_wo_load - def convert_op_to_reg(self, reg_type, reg_id="0"): + def convert_op_to_reg(self, reg_type, regtype="0"): """Create register operand for a memory addressing operand""" if self._isa == "x86": if reg_type == "gpr": - register = {"register": {"name": "r" + str(int(reg_id) + 9)}} + register = RegisterOperand(name="r" + str(int(regtype) + 9)) else: - register = {"register": {"name": reg_type + reg_id}} + register = RegisterOperand(name=reg_type + regtype) elif self._isa == "aarch64": - register = {"register": {"prefix": reg_type, "name": reg_id}} + register = RegisterOperand(name=regtype, prefix=reg_type) return register def _nullify_data_ports(self, port_pressure): @@ -489,7 +484,7 @@ class ArchSemantics(ISASemantics): """Get the overall throughput sum separated by port of all instructions of a kernel.""" # ignoring all lines with throughput == 0.0, because there won't be anything to sum up # typically comment, label and non-instruction lines - port_pressures = [instr["port_pressure"] for instr in kernel if instr["throughput"] != 0.0] + port_pressures = [instr.port_pressure for instr in kernel if instr.throughput != 0.0] # Essentially summing up each columns of port_pressures, where each column is one port # and each row is one line of the kernel # round is necessary to ensure termination of ArchsSemantics.assign_optimal_throughput diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py old mode 100755 new mode 100644 index 9bc67d5..76be6c9 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -6,13 +6,21 @@ import pickle import re import string from collections import defaultdict -from copy import deepcopy from itertools import product from pathlib import Path import ruamel.yaml from osaca import __version__, utils from osaca.parser import ParserX86ATT +from osaca.parser.instruction_form import InstructionForm +from osaca.parser.operand import Operand +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand +from osaca.parser.identifier import IdentifierOperand +from osaca.parser.condition import ConditionOperand +from osaca.parser.flag import FlagOperand +from osaca.parser.prefetch import PrefetchOperand from ruamel.yaml.compat import StringIO @@ -41,7 +49,6 @@ class MachineModel(object): "index": i, "offset": o, "scale": s, - "port_pressure": [], } for b, i, o, s in product(["gpr"], ["gpr", None], ["imd", None], [1, 8]) ], @@ -96,11 +103,88 @@ class MachineModel(object): self._data["instruction_forms"].remove(entry) # Normalize instruction_form names (to UPPERCASE) and build dict for faster access: self._data["instruction_forms_dict"] = defaultdict(list) + for iform in self._data["instruction_forms"]: iform["name"] = iform["name"].upper() - self._data["instruction_forms_dict"][iform["name"]].append(iform) + if iform["operands"] != []: + new_operands = [] + # Change operand types from dicts to classes + for o in iform["operands"]: + self.operand_to_class(o, new_operands) + iform["operands"] = new_operands + # Do the same for hidden operands + if "hidden_operands" in iform: + new_operands = [] + # Change operand types from dicts to classes + for o in iform["hidden_operands"]: + self.operand_to_class(o, new_operands) + iform["hidden_operands"] = new_operands + + # Change dict iform style to class style + new_iform = InstructionForm( + mnemonic=iform["name"].upper() if "name" in iform else None, + operands=iform["operands"] if "operands" in iform else [], + hidden_operands=( + iform["hidden_operands"] if "hidden_operands" in iform else [] + ), + directive_id=iform["directive"] if "directive" in iform else None, + comment_id=iform["comment"] if "comment" in iform else None, + line=iform["line"] if "line" in iform else None, + line_number=iform["line_number"] if "line_number" in iform else None, + latency=iform["latency"] if "latency" in iform else None, + throughput=iform["throughput"] if "throughput" in iform else None, + uops=iform["uops"] if "uops" in iform else None, + port_pressure=iform["port_pressure"] if "port_pressure" in iform else None, + operation=iform["operation"] if "operation" in iform else None, + breaks_dependency_on_equal_operands=( + iform["breaks_dependency_on_equal_operands"] + if "breaks_dependency_on_equal_operands" in iform + else False + ), + semantic_operands=( + iform["semantic_operands"] + if "semantic_operands" in iform + else {"source": [], "destination": [], "src_dst": []} + ), + ) + # List containing classes with same name/instruction + self._data["instruction_forms_dict"][iform["name"]].append(new_iform) self._data["internal_version"] = self.INTERNAL_VERSION + # Convert load and store throughput memory operands to classes + new_throughputs = [] + if "load_throughput" in self._data: + for m in self._data["load_throughput"]: + new_throughputs.append( + ( + MemoryOperand( + base=m["base"], + offset=m["offset"], + scale=m["scale"], + index=m["index"], + dst=m["dst"] if "dst" in m else None, + ), + m["port_pressure"], + ) + ) + self._data["load_throughput"] = new_throughputs + + new_throughputs = [] + if "store_throughput" in self._data: + for m in self._data["store_throughput"]: + new_throughputs.append( + ( + MemoryOperand( + base=m["base"], + offset=m["offset"], + scale=m["scale"], + index=m["index"], + ), + m["port_pressure"], + ) + ) + self._data["store_throughput"] = new_throughputs + if not lazy: # cache internal representation for future use self._write_in_cache(self._path) @@ -108,6 +192,84 @@ class MachineModel(object): if not lazy: MachineModel._runtime_cache[self._path] = self._data + def operand_to_class(self, o, new_operands): + """Convert an operand from dict type to class""" + if o["class"] == "register": + new_operands.append( + RegisterOperand( + name=o["name"] if "name" in o else None, + prefix=o["prefix"] if "prefix" in o else None, + shape=o["shape"] if "shape" in o else None, + mask=o["mask"] if "mask" in o else False, + pre_indexed=o["pre_indexed"] if "pre_indexed" in o else False, + post_indexed=o["post_indexed"] if "post_indexed" in o else False, + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + ) + ) + elif o["class"] == "memory": + if isinstance(o["base"], dict): + o["base"] = RegisterOperand(name=o["base"]["name"]) + if isinstance(o["index"], dict): + o["index"] = RegisterOperand( + name=o["index"]["name"], + prefix=o["index"]["prefix"] if "prefix" in o["index"] else None, + ) + new_operands.append( + MemoryOperand( + base=o["base"], + offset=o["offset"], + index=o["index"], + scale=o["scale"], + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + pre_indexed=o["pre_indexed"] if "pre_indexed" in o else False, + post_indexed=o["post_indexed"] if "post_indexed" in o else False, + ) + ) + elif o["class"] == "immediate": + new_operands.append( + ImmediateOperand( + imd_type=o["imd"], + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + ) + ) + elif o["class"] == "identifier": + new_operands.append( + IdentifierOperand( + name=o["name"] if "name" in o else None, + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + ) + ) + elif o["class"] == "condition": + new_operands.append( + ConditionOperand( + ccode=o["ccode"].upper(), + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + ) + ) + elif o["class"] == "flag": + new_operands.append( + FlagOperand( + name=o["name"], + source=o["source"] if "source" in o else False, + destination=o["destination"] if "destination" in o else False, + ) + ) + elif o["class"] == "prfop": + new_operands.append( + PrefetchOperand( + type_id=o["type"] if "type" in o else None, + target=o["target"] if "target" in o else None, + policy=o["policy"] if "policy" in o else None, + ) + ) + else: + new_operands.append(o) + def get(self, key, default=None): """Return config entry for key or default/None.""" return self._data.get(key, default) @@ -128,12 +290,13 @@ class MachineModel(object): if name is None: return None name_matched_iforms = self._data["instruction_forms_dict"].get(name.upper(), []) + try: return next( instruction_form for instruction_form in name_matched_iforms if self._match_operands( - instruction_form["operands"] if "operands" in instruction_form else [], + instruction_form.operands, operands, ) ) @@ -162,7 +325,7 @@ class MachineModel(object): def set_instruction( self, - name, + mnemonic, operands=None, latency=None, port_pressure=None, @@ -171,28 +334,30 @@ class MachineModel(object): ): """Import instruction form information.""" # If it already exists. Overwrite information. - instr_data = self.get_instruction(name, operands) + instr_data = self.get_instruction(mnemonic, operands) if instr_data is None: - instr_data = {} + instr_data = InstructionForm() self._data["instruction_forms"].append(instr_data) - self._data["instruction_forms_dict"][name].append(instr_data) + self._data["instruction_forms_dict"][mnemonic].append(instr_data) - instr_data["name"] = name - instr_data["operands"] = operands - instr_data["latency"] = latency - instr_data["port_pressure"] = port_pressure - instr_data["throughput"] = throughput - instr_data["uops"] = uops + instr_data.mnemonic = mnemonic + instr_data.operands = operands + instr_data.latency = latency + instr_data.port_pressure = port_pressure + instr_data.throughput = throughput + instr_data.uops = uops def set_instruction_entry(self, entry): """Import instruction as entry object form information.""" + if entry.mnemonic is None and entry.operands == []: + raise KeyError self.set_instruction( - entry["name"], - entry["operands"] if "operands" in entry else None, - entry["latency"] if "latency" in entry else None, - entry["port_pressure"] if "port_pressure" in entry else None, - entry["throughput"] if "throughput" in entry else None, - entry["uops"] if "uops" in entry else None, + entry.mnemonic, + entry.operands, + entry.latency, + entry.port_pressure, + entry.throughput, + entry.uops, ) def add_port(self, port): @@ -224,10 +389,10 @@ class MachineModel(object): def get_load_throughput(self, memory): """Return load thorughput for given register type.""" - ld_tp = [m for m in self._data["load_throughput"] if self._match_mem_entries(memory, m)] + ld_tp = [m for m in self._data["load_throughput"] if self._match_mem_entries(memory, m[0])] if len(ld_tp) > 0: return ld_tp.copy() - return [{"port_pressure": self._data["load_throughput_default"].copy()}] + return [(memory, self._data["load_throughput_default"].copy())] def get_store_latency(self, reg_type): """Return store latency for given register type.""" @@ -236,16 +401,19 @@ class MachineModel(object): def get_store_throughput(self, memory, src_reg=None): """Return store throughput for a given destination and register type.""" - st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m)] + st_tp = [ + m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m[0]) + ] if src_reg is not None: st_tp = [ tp for tp in st_tp - if "src" in tp and self._check_operands(src_reg, {"register": {"name": tp["src"]}}) + if "src" in tp[0] + and self._check_operands(src_reg, RegisterOperand(name=tp[0]["src"])) ] if len(st_tp) > 0: return st_tp.copy() - return [{"port_pressure": self._data["store_throughput_default"].copy()}] + return [(memory, self._data["store_throughput_default"].copy())] def _match_mem_entries(self, mem, i_mem): """Check if memory addressing ``mem`` and ``i_mem`` are of the same type.""" @@ -260,18 +428,6 @@ class MachineModel(object): data_ports = [x for x in filter(data_port.match, self._data["ports"])] return data_ports - @staticmethod - def get_full_instruction_name(instruction_form): - """Get one instruction name string including the mnemonic and all operands.""" - operands = [] - for op in instruction_form["operands"]: - op_attrs = [ - y + ":" + str(op[y]) - for y in list(filter(lambda x: True if x != "class" else False, op)) - ] - operands.append("{}({})".format(op["class"], ",".join(op_attrs))) - return "{} {}".format(instruction_form["name"].lower(), ",".join(operands)) - @staticmethod def get_isa_for_arch(arch): """Return ISA for given micro-arch ``arch``.""" @@ -311,23 +467,75 @@ class MachineModel(object): else: raise ValueError("Unknown architecture {!r}.".format(arch)) + def class_to_dict(self, op): + """Need to convert operand classes to dicts for the dump. Memory operand types may have their index/base/offset as a register operand/""" + if isinstance(op, Operand): + dict_op = dict( + (key.lstrip("_"), value) + for key, value in op.__dict__.items() + if not callable(value) and not key.startswith("__") + ) + if isinstance(op, MemoryOperand): + if isinstance(dict_op["index"], Operand): + dict_op["index"] = dict( + (key.lstrip("_"), value) + for key, value in dict_op["index"].__dict__.items() + if not callable(value) and not key.startswith("__") + ) + if isinstance(dict_op["offset"], Operand): + dict_op["offset"] = dict( + (key.lstrip("_"), value) + for key, value in dict_op["offset"].__dict__.items() + if not callable(value) and not key.startswith("__") + ) + if isinstance(dict_op["base"], Operand): + dict_op["base"] = dict( + (key.lstrip("_"), value) + for key, value in dict_op["base"].__dict__.items() + if not callable(value) and not key.startswith("__") + ) + return dict_op + return op + def dump(self, stream=None): """Dump machine model to stream or return it as a ``str`` if no stream is given.""" # Replace instruction form's port_pressure with styled version for RoundtripDumper - formatted_instruction_forms = deepcopy(self._data["instruction_forms"]) - for instruction_form in formatted_instruction_forms: + formatted_instruction_forms = [] + for instruction_form in self._data["instruction_forms"]: + if isinstance(instruction_form, InstructionForm): + instruction_form = dict( + (key.lstrip("_"), value) + for key, value in instruction_form.__dict__.items() + if not callable(value) and not key.startswith("__") + ) if instruction_form["port_pressure"] is not None: cs = ruamel.yaml.comments.CommentedSeq(instruction_form["port_pressure"]) cs.fa.set_flow_style() instruction_form["port_pressure"] = cs + dict_operands = [] + for op in instruction_form["operands"]: + dict_operands.append(self.class_to_dict(op)) + instruction_form["operands"] = dict_operands + formatted_instruction_forms.append(instruction_form) # Replace load_throughput with styled version for RoundtripDumper formatted_load_throughput = [] for lt in self._data["load_throughput"]: - cm = ruamel.yaml.comments.CommentedMap(lt) + cm = self.class_to_dict(lt[0]) + cm["port_pressure"] = lt[1] + cm = ruamel.yaml.comments.CommentedMap(cm) cm.fa.set_flow_style() formatted_load_throughput.append(cm) + # Replace store_throughput with styled version for RoundtripDumper + formatted_store_throughput = [] + for st in self._data["store_throughput"]: + cm = self.class_to_dict(st[0]) + cm["port_pressure"] = st[1] + cm = ruamel.yaml.comments.CommentedMap(cm) + cm.fa.set_flow_style() + formatted_store_throughput.append(cm) + # Create YAML object yaml = self._create_yaml_object() if not stream: @@ -342,12 +550,15 @@ class MachineModel(object): "instruction_forms", "instruction_forms_dict", "load_throughput", + "store_throughput", "internal_version", ] }, stream, ) + yaml.dump({"load_throughput": formatted_load_throughput}, stream) + yaml.dump({"store_throughput": formatted_store_throughput}, stream) yaml.dump({"instruction_forms": formatted_instruction_forms}, stream) if isinstance(stream, StringIO): @@ -449,48 +660,46 @@ class MachineModel(object): operand_string += ( "s" if operand["scale"] == self.WILDCARD or operand["scale"] > 1 else "" ) - if "pre-indexed" in operand: - operand_string += "r" if operand["pre-indexed"] else "" - operand_string += "p" if operand["post-indexed"] else "" + if "pre_indexed" in operand: + operand_string += "r" if operand["pre_indexed"] else "" + operand_string += "p" if operand["post_indexed"] else "" return operand_string def _create_db_operand_aarch64(self, operand): """Create instruction form operand for DB out of operand string.""" if operand == "i": - return {"class": "immediate", "imd": "int"} + return ImmediateOperand(imd_type="int") elif operand in "wxbhsdq": - return {"class": "register", "prefix": operand} + return RegisterOperand(prefix=operand) elif operand.startswith("v"): - return {"class": "register", "prefix": "v", "shape": operand[1:2]} + return RegisterOperand(prefix="v", shape=operand[1:2]) elif operand.startswith("m"): - return { - "class": "memory", - "base": "x" if "b" in operand else None, - "offset": "imd" if "o" in operand else None, - "index": "gpr" if "i" in operand else None, - "scale": 8 if "s" in operand else 1, - "pre-indexed": True if "r" in operand else False, - "post-indexed": True if "p" in operand else False, - } + return MemoryOperand( + base="x" if "b" in operand else None, + offset="imd" if "o" in operand else None, + index="gpr" if "i" in operand else None, + scale=8 if "s" in operand else 1, + pre_indexed=True if "r" in operand else False, + post_indexed=True if "p" in operand else False, + ) else: raise ValueError("Parameter {} is not a valid operand code".format(operand)) def _create_db_operand_x86(self, operand): """Create instruction form operand for DB out of operand string.""" if operand == "r": - return {"class": "register", "name": "gpr"} + return RegisterOperand(name="gpr") elif operand in "xyz": - return {"class": "register", "name": operand + "mm"} + return RegisterOperand(name=operand + "mm") elif operand == "i": - return {"class": "immediate", "imd": "int"} + return ImmediateOperand(imd_type="int") elif operand.startswith("m"): - return { - "class": "memory", - "base": "gpr" if "b" in operand else None, - "offset": "imd" if "o" in operand else None, - "index": "gpr" if "i" in operand else None, - "scale": 8 if "s" in operand else 1, - } + return MemoryOperand( + base="gpr" if "b" in operand else None, + offset="imd" if "o" in operand else None, + index="gpr" if "i" in operand else None, + scale=8 if "s" in operand else 1, + ) else: raise ValueError("Parameter {} is not a valid operand code".format(operand)) @@ -529,12 +738,8 @@ class MachineModel(object): def _check_operands(self, i_operand, operand): """Check if the types of operand ``i_operand`` and ``operand`` match.""" # check for wildcard - if self.WILDCARD in operand: - if ( - "class" in i_operand - and i_operand["class"] == "register" - or "register" in i_operand - ): + if isinstance(operand, dict) and self.WILDCARD in operand: + if isinstance(i_operand, RegisterOperand): return True else: return False @@ -545,87 +750,87 @@ class MachineModel(object): def _check_AArch64_operands(self, i_operand, operand): """Check if the types of operand ``i_operand`` and ``operand`` match.""" - if "class" in operand: - # compare two DB entries - return self._compare_db_entries(i_operand, operand) + # if "class" in operand: + # compare two DB entries + # return self._compare_db_entries(i_operand, operand) # TODO support class wildcards # register - if "register" in operand: - if i_operand["class"] != "register": + if isinstance(operand, RegisterOperand): + if not isinstance(i_operand, RegisterOperand): return False - return self._is_AArch64_reg_type(i_operand, operand["register"]) + return self._is_AArch64_reg_type(i_operand, operand) # memory - if "memory" in operand: - if i_operand["class"] != "memory": + if isinstance(operand, MemoryOperand): + if not isinstance(i_operand, MemoryOperand): return False - return self._is_AArch64_mem_type(i_operand, operand["memory"]) + return self._is_AArch64_mem_type(i_operand, operand) # immediate - if i_operand["class"] == "immediate" and i_operand["imd"] == self.WILDCARD: - return "value" in operand or ( - "immediate" in operand and "value" in operand["immediate"] + if isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == self.WILDCARD: + return isinstance(operand, ImmediateOperand) and (operand.value is not None) + + if isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == "int": + return ( + isinstance(operand, ImmediateOperand) + and operand.imd_type == "int" + and operand.value is not None ) - if i_operand["class"] == "immediate" and i_operand["imd"] == "int": - return ("value" in operand and operand.get("type", None) == "int") or ( - "immediate" in operand - and "value" in operand["immediate"] - and operand["immediate"].get("type", None) == "int" + + if isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == "float": + return ( + isinstance(operand, ImmediateOperand) + and operand.imd_type == "float" + and operand.value is not None ) - if i_operand["class"] == "immediate" and i_operand["imd"] == "float": - return ("float" in operand and operand.get("type", None) == "float") or ( - "immediate" in operand - and "float" in operand["immediate"] - and operand["immediate"].get("type", None) == "float" - ) - if i_operand["class"] == "immediate" and i_operand["imd"] == "double": - return ("double" in operand and operand.get("type", None) == "double") or ( - "immediate" in operand - and "double" in operand["immediate"] - and operand["immediate"].get("type", None) == "double" + + if isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == "double": + return ( + isinstance(operand, ImmediateOperand) + and operand.imd_type == "double" + and operand.value is not None ) + # identifier - if "identifier" in operand or ( - "immediate" in operand and "identifier" in operand["immediate"] + if isinstance(operand, IdentifierOperand) or ( + isinstance(operand, ImmediateOperand) and operand.identifier is not None ): - return i_operand["class"] == "identifier" + return isinstance(i_operand, IdentifierOperand) # prefetch option - if "prfop" in operand: - return i_operand["class"] == "prfop" + if isinstance(operand, PrefetchOperand): + return isinstance(i_operand, PrefetchOperand) # condition - if "condition" in operand: - if i_operand["class"] == "condition" and i_operand["ccode"] == self.WILDCARD: - return True - return i_operand["class"] == "condition" and ( - operand.get("condition", None) == i_operand.get("ccode", None).upper() - if isinstance(i_operand.get("ccode", None), str) - else i_operand.get("ccode", None) - ) + if isinstance(operand, ConditionOperand): + if isinstance(i_operand, ConditionOperand): + return (i_operand.ccode == self.WILDCARD) or (i_operand.ccode == operand.ccode) # no match return False def _check_x86_operands(self, i_operand, operand): """Check if the types of operand ``i_operand`` and ``operand`` match.""" - if "class" in operand: - # compare two DB entries - return self._compare_db_entries(i_operand, operand) + # if "class" in operand.name: + # compare two DB entries + # return self._compare_db_entries(i_operand, operand) # register - if "register" in operand: - if i_operand["class"] != "register": + if isinstance(operand, RegisterOperand): + if not isinstance(i_operand, RegisterOperand): return False - return self._is_x86_reg_type(i_operand, operand["register"], consider_masking=False) + return self._is_x86_reg_type(i_operand, operand, consider_masking=False) # memory - if "memory" in operand: - if i_operand["class"] != "memory": + if isinstance(operand, MemoryOperand): + if not isinstance(i_operand, MemoryOperand): return False - return self._is_x86_mem_type(i_operand, operand["memory"]) + return self._is_x86_mem_type(i_operand, operand) # immediate - if "immediate" in operand or "value" in operand: - return i_operand["class"] == "immediate" and i_operand["imd"] == "int" + if isinstance(operand, ImmediateOperand): + # if "immediate" in operand.name or operand.value != None: + return isinstance(i_operand, ImmediateOperand) and i_operand.imd_type == "int" # identifier (e.g., labels) - if "identifier" in operand: - return i_operand["class"] == "identifier" + if isinstance(operand, IdentifierOperand): + return isinstance(i_operand, IdentifierOperand) + return self._compare_db_entries(i_operand, operand) def _compare_db_entries(self, operand_1, operand_2): """Check if operand types in DB format (i.e., not parsed) match.""" + return True operand_attributes = list( filter( lambda x: True if x != "source" and x != "destination" else False, @@ -645,27 +850,26 @@ class MachineModel(object): def _is_AArch64_reg_type(self, i_reg, reg): """Check if register type match.""" # check for wildcards - if reg["prefix"] == self.WILDCARD or i_reg["prefix"] == self.WILDCARD: - if "shape" in reg: - if "shape" in i_reg and ( - reg["shape"] == i_reg["shape"] - or self.WILDCARD in (reg["shape"] + i_reg["shape"]) + if reg.prefix == self.WILDCARD or i_reg.prefix == self.WILDCARD: + if reg.shape is not None: + if i_reg.shape is not None and ( + reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape) ): return True return False return True # check for prefix and shape - if reg["prefix"] != i_reg["prefix"]: + if reg.prefix != i_reg.prefix: return False - if "shape" in reg: - if "shape" in i_reg and ( - reg["shape"] == i_reg["shape"] or self.WILDCARD in (reg["shape"] + i_reg["shape"]) + if reg.shape is not None: + if i_reg.shape is not None and ( + reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape) ): return True return False - if "lanes" in reg: - if "lanes" in i_reg and ( - reg["lanes"] == i_reg["lanes"] or self.WILDCARD in (reg["lanes"] + i_reg["lanes"]) + if reg.lanes is not None: + if i_reg.lanes is not None and ( + reg.lanes == i_reg.lanes or self.WILDCARD in (reg.lanes + i_reg.lanes) ): return True return False @@ -673,48 +877,52 @@ class MachineModel(object): def _is_x86_reg_type(self, i_reg, reg, consider_masking=False): """Check if register type match.""" - i_reg_name = i_reg["name"] if i_reg and "name" in i_reg else i_reg if reg is None: if i_reg is None: return True return False + if isinstance(i_reg, RegisterOperand): + i_reg_name = i_reg.name + else: + i_reg_name = i_reg # check for wildcards - if i_reg_name == self.WILDCARD or reg["name"] == self.WILDCARD: + if isinstance(reg, str): + return False + if i_reg_name is None and reg.name is None: + return True + if i_reg_name == self.WILDCARD or reg.name == self.WILDCARD: return True # differentiate between vector registers (mm, xmm, ymm, zmm) and others (gpr) parser_x86 = ParserX86ATT() if parser_x86.is_vector_register(reg): - if reg["name"].rstrip(string.digits).lower() == i_reg_name: + if reg.name.rstrip(string.digits).lower() == i_reg_name: # Consider masking and zeroing for AVX512 if consider_masking: mask_ok = zero_ok = True - if "mask" in reg or "mask" in i_reg: + if reg.mask is not None or i_reg.mask is not None: # one instruction is missing the masking while the other has it mask_ok = False # check for wildcard if ( ( - "mask" in reg - and reg["mask"].rstrip(string.digits).lower() == i_reg.get("mask") + reg.mask is not None + and reg.mask.rstrip(string.digits).lower() == i_reg.mask ) - or reg.get("mask") == self.WILDCARD - or i_reg.get("mask") == self.WILDCARD + or reg.mask == self.WILDCARD + or i_reg.mask == self.WILDCARD ): mask_ok = True - if bool("zeroing" in reg) ^ bool("zeroing" in i_reg): + if bool(reg.zeroing) ^ bool("zeroing" in i_reg): # one instruction is missing zeroing while the other has it zero_ok = False # check for wildcard - if ( - i_reg.get("zeroing") == self.WILDCARD - or reg.get("zeroing") == self.WILDCARD - ): + if i_reg.zeroing == self.WILDCARD or reg.zeroing == self.WILDCARD: zero_ok = True if not mask_ok or not zero_ok: return False return True else: - if reg["name"].rstrip(string.digits).lower() == i_reg_name: + if reg.name.rstrip(string.digits).lower() == i_reg_name: return True if i_reg_name == "gpr": return True @@ -725,50 +933,48 @@ class MachineModel(object): if ( # check base ( - (mem["base"] is None and i_mem["base"] is None) - or i_mem["base"] == self.WILDCARD - or mem["base"]["prefix"] == i_mem["base"] + (mem.base is None and i_mem.base is None) + or i_mem.base == self.WILDCARD + or (isinstance(mem.base, RegisterOperand) and (mem.base.prefix == i_mem.base)) ) # check offset and ( - mem["offset"] == i_mem["offset"] - or i_mem["offset"] == self.WILDCARD + mem.offset == i_mem.offset + or i_mem.offset == self.WILDCARD or ( - mem["offset"] is not None - and "identifier" in mem["offset"] - and i_mem["offset"] == "identifier" + mem.offset is not None + and isinstance(mem.offset, IdentifierOperand) + and isinstance(i_mem.offset, IdentifierOperand) ) or ( - mem["offset"] is not None - and "value" in mem["offset"] - and i_mem["offset"] == "imd" + mem.offset is not None + and isinstance(mem.offset, ImmediateOperand) + and i_mem.offset == "imd" ) ) # check index and ( - mem["index"] == i_mem["index"] - or i_mem["index"] == self.WILDCARD + mem.index == i_mem.index + or i_mem.index == self.WILDCARD or ( - mem["index"] is not None - and "prefix" in mem["index"] - and mem["index"]["prefix"] == i_mem["index"] + mem.index is not None + and mem.index.prefix is not None + and mem.index.prefix == i_mem.index ) ) # check scale and ( - mem["scale"] == i_mem["scale"] - or i_mem["scale"] == self.WILDCARD - or (mem["scale"] != 1 and i_mem["scale"] != 1) + mem.scale == i_mem.scale + or i_mem.scale == self.WILDCARD + or (mem.scale != 1 and i_mem.scale != 1) ) # check pre-indexing - and ( - i_mem["pre-indexed"] == self.WILDCARD - or ("pre_indexed" in mem) == (i_mem["pre-indexed"]) - ) + and (i_mem.pre_indexed == self.WILDCARD or mem.pre_indexed == i_mem.pre_indexed) # check post-indexing and ( - i_mem["post-indexed"] == self.WILDCARD - or ("post_indexed" in mem) == (i_mem["post-indexed"]) + i_mem.post_indexed == self.WILDCARD + or mem.post_indexed == i_mem.post_indexed + or (isinstance(mem.post_indexed, dict) and i_mem.post_indexed) ) ): return True @@ -779,48 +985,43 @@ class MachineModel(object): if ( # check base ( - (mem["base"] is None and i_mem["base"] is None) - or i_mem["base"] == self.WILDCARD - or self._is_x86_reg_type(i_mem["base"], mem["base"]) + (mem.base is None and i_mem.base is None) + or i_mem.base == self.WILDCARD + or self._is_x86_reg_type(i_mem.base, mem.base) ) # check offset and ( - mem["offset"] == i_mem["offset"] - or i_mem["offset"] == self.WILDCARD + mem.offset == i_mem.offset + or i_mem.offset == self.WILDCARD or ( - mem["offset"] is not None - and "identifier" in mem["offset"] - and i_mem["offset"] == "identifier" + mem.offset is not None + and isinstance(mem.offset, IdentifierOperand) + and isinstance(i_mem.offset, IdentifierOperand) ) or ( - mem["offset"] is not None - and "value" in mem["offset"] + mem.offset is not None + and isinstance(mem.offset, ImmediateOperand) and ( - i_mem["offset"] == "imd" - or (i_mem["offset"] is None and mem["offset"]["value"] == "0") + i_mem.offset == "imd" or (i_mem.offset is None and mem.offset.value == "0") ) ) - or ( - mem["offset"] is not None - and "identifier" in mem["offset"] - and i_mem["offset"] == "id" - ) + or (isinstance(mem.offset, IdentifierOperand) and i_mem.offset == "id") ) # check index and ( - mem["index"] == i_mem["index"] - or i_mem["index"] == self.WILDCARD + mem.index == i_mem.index + or i_mem.index == self.WILDCARD or ( - mem["index"] is not None - and "name" in mem["index"] - and self._is_x86_reg_type(i_mem["index"], mem["index"]) + mem.index is not None + # and mem.index.name != None + and self._is_x86_reg_type(i_mem.index, mem.index) ) ) # check scale and ( - mem["scale"] == i_mem["scale"] - or i_mem["scale"] == self.WILDCARD - or (mem["scale"] != 1 and i_mem["scale"] != 1) + mem.scale == i_mem.scale + or i_mem.scale == self.WILDCARD + or (mem.scale != 1 and i_mem.scale != 1) ) ): return True diff --git a/osaca/semantics/isa_semantics.py b/osaca/semantics/isa_semantics.py old mode 100755 new mode 100644 index 1c26818..a84602d --- a/osaca/semantics/isa_semantics.py +++ b/osaca/semantics/isa_semantics.py @@ -2,7 +2,11 @@ from itertools import chain from osaca import utils -from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT +from osaca.parser import ParserAArch64, ParserX86ATT +from osaca.parser.memory import MemoryOperand +from osaca.parser.operand import Operand +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand from .hw_model import MachineModel @@ -45,33 +49,32 @@ class ISASemantics(object): def assign_src_dst(self, instruction_form): """Update instruction form dictionary with source, destination and flag information.""" # if the instruction form doesn't have operands or is None, there's nothing to do - if instruction_form["operands"] is None or instruction_form["instruction"] is None: - instruction_form["semantic_operands"] = AttrDict( - {"source": [], "destination": [], "src_dst": []} - ) + if instruction_form.operands is None or instruction_form.mnemonic is None: + instruction_form.semantic_operands = {"source": [], "destination": [], "src_dst": []} return # check if instruction form is in ISA yaml, otherwise apply standard operand assignment # (one dest, others source) isa_data = self._isa_model.get_instruction( - instruction_form["instruction"], instruction_form["operands"] + instruction_form.mnemonic, instruction_form.operands ) if ( isa_data is None and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES + and instruction_form.mnemonic[-1] in self.GAS_SUFFIXES ): # Check for instruction without GAS suffix isa_data = self._isa_model.get_instruction( - instruction_form["instruction"][:-1], instruction_form["operands"] + instruction_form.mnemonic[:-1], instruction_form.operands ) - if isa_data is None and self._isa == "aarch64" and "." in instruction_form["instruction"]: + if isa_data is None and self._isa == "aarch64" and "." in instruction_form.mnemonic: # Check for instruction without shape/cc suffix - suffix_start = instruction_form["instruction"].index(".") + suffix_start = instruction_form.mnemonic.index(".") isa_data = self._isa_model.get_instruction( - instruction_form["instruction"][:suffix_start], instruction_form["operands"] + instruction_form.mnemonic[:suffix_start], instruction_form.operands ) - operands = instruction_form["operands"] + operands = instruction_form.operands op_dict = {} + assign_default = False if isa_data: # load src/dst structure from isa_data @@ -80,33 +83,34 @@ class ISASemantics(object): # Couldn't found instruction form in ISA DB assign_default = True # check for equivalent register-operands DB entry if LD/ST - if any(["memory" in op for op in operands]): - operands_reg = self.substitute_mem_address(instruction_form["operands"]) + if any([isinstance(op, MemoryOperand) for op in operands]): + operands_reg = self.substitute_mem_address(instruction_form.operands) isa_data_reg = self._isa_model.get_instruction( - instruction_form["instruction"], operands_reg + instruction_form.mnemonic, operands_reg ) if ( isa_data_reg is None and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES + and instruction_form.mnemonic[-1] in self.GAS_SUFFIXES ): # Check for instruction without GAS suffix isa_data_reg = self._isa_model.get_instruction( - instruction_form["instruction"][:-1], operands_reg + instruction_form.mnemonic[:-1], operands_reg ) if ( isa_data_reg is None and self._isa == "aarch64" - and "." in instruction_form["instruction"] + and "." in instruction_form.mnemonic ): # Check for instruction without shape/cc suffix - suffix_start = instruction_form["instruction"].index(".") + suffix_start = instruction_form.mnemonic.index(".") isa_data_reg = self._isa_model.get_instruction( - instruction_form["instruction"][:suffix_start], operands_reg + instruction_form.mnemonic[:suffix_start], operands_reg ) if isa_data_reg: assign_default = False op_dict = self._apply_found_ISA_data(isa_data_reg, operands) + if assign_default: # no irregular operand structure, apply default op_dict["source"] = self._get_regular_source_operands(instruction_form) @@ -114,50 +118,41 @@ class ISASemantics(object): op_dict["src_dst"] = [] # post-process pre- and post-indexing for aarch64 memory operands if self._isa == "aarch64": - for operand in [op for op in op_dict["source"] if "memory" in op]: - post_indexed = ( - "post_indexed" in operand["memory"] and operand["memory"]["post_indexed"] - ) - pre_indexed = ( - "pre_indexed" in operand["memory"] and operand["memory"]["pre_indexed"] - ) - if post_indexed or pre_indexed: - op_dict["src_dst"].append( - AttrDict.convert_dict( - { - "register": operand["memory"]["base"], - "pre_indexed": pre_indexed, - "post_indexed": post_indexed, - } - ) - ) - for operand in [op for op in op_dict["destination"] if "memory" in op]: - post_indexed = ( - "post_indexed" in operand["memory"] and operand["memory"]["post_indexed"] - ) - pre_indexed = ( - "pre_indexed" in operand["memory"] and operand["memory"]["pre_indexed"] - ) - if post_indexed or pre_indexed: - op_dict["src_dst"].append( - AttrDict.convert_dict( - { - "register": operand["memory"]["base"], - "pre_indexed": pre_indexed, - "post_indexed": post_indexed, - } - ) - ) + for operand in [op for op in op_dict["source"] if isinstance(op, MemoryOperand)]: + post_indexed = operand.post_indexed + pre_indexed = operand.pre_indexed + if ( + post_indexed + or pre_indexed + or (isinstance(post_indexed, dict) and "value" in post_indexed) + ): + new_op = operand.base + new_op.pre_indexed = pre_indexed + new_op.post_indexed = post_indexed + op_dict["src_dst"].append(new_op) + for operand in [op for op in op_dict["destination"] if isinstance(op, MemoryOperand)]: + post_indexed = operand.post_indexed + pre_indexed = operand.pre_indexed + if ( + post_indexed + or pre_indexed + or (isinstance(post_indexed, dict) and "value" in post_indexed) + ): + new_op = operand.base + new_op.pre_indexed = pre_indexed + new_op.post_indexed = post_indexed + op_dict["src_dst"].append(new_op) # store operand list in dict and reassign operand key/value pair - instruction_form["semantic_operands"] = AttrDict.convert_dict(op_dict) + instruction_form.semantic_operands = op_dict # assign LD/ST flags - instruction_form["flags"] = ( - instruction_form["flags"] if "flags" in instruction_form else [] - ) + # instruction_form.flags = ( + # instruction_form.flags if "flags" in instruction_form else [] + # ) + if self._has_load(instruction_form): - instruction_form["flags"] += [INSTR_FLAGS.HAS_LD] + instruction_form.flags += [INSTR_FLAGS.HAS_LD] if self._has_store(instruction_form): - instruction_form["flags"] += [INSTR_FLAGS.HAS_ST] + instruction_form.flags += [INSTR_FLAGS.HAS_ST] def get_reg_changes(self, instruction_form, only_postindexed=False): """ @@ -166,43 +161,48 @@ class ISASemantics(object): Empty dict if no changes of registers occured. None for registers with unknown changes. If only_postindexed is True, only considers changes due to post_indexed memory references. """ - if instruction_form.get("instruction") is None: + if instruction_form.mnemonic is None: return {} dest_reg_names = [ - op.register.get("prefix", "") + op.register.name + (op.prefix if op.prefix is not None else "") + op.name for op in chain( - instruction_form.semantic_operands.destination, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ) - if "register" in op + if isinstance(op, RegisterOperand) ] isa_data = self._isa_model.get_instruction( - instruction_form["instruction"], instruction_form["operands"] + instruction_form.mnemonic, instruction_form.operands ) if ( isa_data is None and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES + and instruction_form.mnemonic[-1] in self.GAS_SUFFIXES ): # Check for instruction without GAS suffix isa_data = self._isa_model.get_instruction( - instruction_form["instruction"][:-1], instruction_form["operands"] + instruction_form.mnemonic[:-1], instruction_form.operands ) - if isa_data is None and self._isa == "aarch64" and "." in instruction_form["instruction"]: + if isa_data is None and self._isa == "aarch64" and "." in instruction_form.mnemonic: # Check for instruction without shape/cc suffix - suffix_start = instruction_form["instruction"].index(".") + suffix_start = instruction_form.mnemonic.index(".") isa_data = self._isa_model.get_instruction( - instruction_form["instruction"][:suffix_start], instruction_form["operands"] + instruction_form.mnemonic[:suffix_start], instruction_form.operands ) if only_postindexed: for o in instruction_form.operands: - if "post_indexed" in o.get("memory", {}): - base_name = o.memory.base.get("prefix", "") + o.memory.base.name + if ( + isinstance(o, MemoryOperand) + and o.base is not None + and isinstance(o.post_indexed, dict) + ): + base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name return { base_name: { - "name": o.memory.base.get("prefix", "") + o.memory.base.name, - "value": o.memory.post_indexed.value, + "name": (o.base.prefix if o.base.prefix is not None else "") + + o.base.name, + "value": o.post_indexed["value"], } } return {} @@ -211,31 +211,32 @@ class ISASemantics(object): operand_state = {} # e.g., {'op1': {'name': 'rax', 'value': 0}} 0 means unchanged for o in instruction_form.operands: - if "pre_indexed" in o.get("memory", {}): + if isinstance(o, MemoryOperand) and o.pre_indexed: # Assuming no isa_data.operation - if isa_data is not None and isa_data.get("operation", None) is not None: + if isa_data is not None and isa_data.operation is not None: raise ValueError( - "ISA information for pre-indexed instruction {!r} has operation set." + "ISA information for pre_indexed instruction {!r} has operation set." "This is currently not supprted.".format(instruction_form.line) ) - base_name = o.memory.base.get("prefix", "") + o.memory.base.name - reg_operand_names = {base_name: "op1"} - operand_state = {"op1": {"name": base_name, "value": o.memory.offset.value}} - if isa_data is not None and "operation" in isa_data: + base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name + reg_operand_names = {base_name: "op1"} + operand_state = {"op1": {"name": base_name, "value": o.offset.value}} + + if isa_data is not None and isa_data.operation is not None: for i, o in enumerate(instruction_form.operands): operand_name = "op{}".format(i + 1) - if "register" in o: - o_reg_name = o["register"].get("prefix", "") + o["register"]["name"] + + if isinstance(o, RegisterOperand): + o_reg_name = (o.prefix if o.prefix is not None else "") + o.name reg_operand_names[o_reg_name] = operand_name operand_state[operand_name] = {"name": o_reg_name, "value": 0} - elif "immediate" in o: - operand_state[operand_name] = {"value": o["immediate"]["value"]} - elif "memory" in o: + elif isinstance(o, ImmediateOperand): + operand_state[operand_name] = {"value": o.value} + elif isinstance(o, MemoryOperand): # TODO lea needs some thinking about pass - - exec(isa_data["operation"], {}, operand_state) + exec(isa_data.operation, {}, operand_state) change_dict = { reg_name: operand_state.get(reg_operand_names.get(reg_name)) @@ -261,100 +262,95 @@ class ISASemantics(object): op_dict["src_dst"] = [] # handle dependency breaking instructions - if "breaks_dependency_on_equal_operands" in isa_data and operands[1:] == operands[:-1]: + if isa_data.breaks_dependency_on_equal_operands and operands[1:] == operands[:-1]: op_dict["destination"] += operands - if "hidden_operands" in isa_data: - op_dict["destination"] += [ - AttrDict.convert_dict( - { - hop["class"]: { - k: hop[k] for k in ["name", "class", "source", "destination"] - } - } - ) - for hop in isa_data["hidden_operands"] - ] + if isa_data.hidden_operands != []: + op_dict["destination"] += [hop for hop in isa_data.hidden_operands] return op_dict - for i, op in enumerate(isa_data["operands"]): - if op["source"] and op["destination"]: + for i, op in enumerate(isa_data.operands): + if op.source and op.destination: op_dict["src_dst"].append(operands[i]) continue - if op["source"]: + if op.source: op_dict["source"].append(operands[i]) continue - if op["destination"]: + if op.destination: op_dict["destination"].append(operands[i]) continue + # check for hidden operands like flags or registers - if "hidden_operands" in isa_data: + if isa_data.hidden_operands != []: # add operand(s) to semantic_operands of instruction form - for op in isa_data["hidden_operands"]: - dict_key = ( - "src_dst" - if op["source"] and op["destination"] - else "source" - if op["source"] - else "destination" - ) - hidden_op = {op["class"]: {}} - key_filter = ["class", "source", "destination"] - for key in [k for k in op.keys() if k not in key_filter]: - hidden_op[op["class"]][key] = op[key] - hidden_op = AttrDict.convert_dict(hidden_op) - op_dict[dict_key].append(hidden_op) + for op in isa_data.hidden_operands: + if isinstance(op, Operand): + dict_key = ( + "src_dst" + if op.source and op.destination + else "source" if op.source else "destination" + ) + else: + dict_key = ( + "src_dst" + if op["source"] and op["destination"] + else "source" if op["source"] else "destination" + ) + op_dict[dict_key].append(op) + return op_dict def _has_load(self, instruction_form): """Check if instruction form performs a LOAD""" for operand in chain( - instruction_form["semantic_operands"]["source"], - instruction_form["semantic_operands"]["src_dst"], + instruction_form.semantic_operands["source"], + instruction_form.semantic_operands["src_dst"], ): - if "memory" in operand: + if isinstance(operand, MemoryOperand): return True return False def _has_store(self, instruction_form): """Check if instruction form perfroms a STORE""" for operand in chain( - instruction_form["semantic_operands"]["destination"], - instruction_form["semantic_operands"]["src_dst"], + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ): - if "memory" in operand: + if isinstance(operand, MemoryOperand): return True return False def _get_regular_source_operands(self, instruction_form): """Get source operand of given instruction form assuming regular src/dst behavior.""" # if there is only one operand, assume it is a source operand - if len(instruction_form["operands"]) == 1: - return [instruction_form["operands"][0]] + if len(instruction_form.operands) == 1: + return [instruction_form.operands[0]] if self._isa == "x86": # return all but last operand - return [op for op in instruction_form["operands"][0:-1]] + return [op for op in instruction_form.operands[0:-1]] elif self._isa == "aarch64": - return [op for op in instruction_form["operands"][1:]] + return [op for op in instruction_form.operands[1:]] else: raise ValueError("Unsupported ISA {}.".format(self._isa)) def _get_regular_destination_operands(self, instruction_form): """Get destination operand of given instruction form assuming regular src/dst behavior.""" # if there is only one operand, assume no destination - if len(instruction_form["operands"]) == 1: + if len(instruction_form.operands) == 1: return [] if self._isa == "x86": # return last operand - return instruction_form["operands"][-1:] + return instruction_form.operands[-1:] if self._isa == "aarch64": # return first operand - return instruction_form["operands"][:1] + return instruction_form.operands[:1] else: raise ValueError("Unsupported ISA {}.".format(self._isa)) def substitute_mem_address(self, operands): """Create memory wildcard for all memory operands""" - return [self._create_reg_wildcard() if "memory" in op else op for op in operands] + return [ + self._create_reg_wildcard() if isinstance(op, MemoryOperand) else op for op in operands + ] def _create_reg_wildcard(self): """Wildcard constructor""" diff --git a/osaca/semantics/kernel_dg.py b/osaca/semantics/kernel_dg.py old mode 100755 new mode 100644 index a21beac..c9d64a5 --- a/osaca/semantics/kernel_dg.py +++ b/osaca/semantics/kernel_dg.py @@ -9,6 +9,10 @@ from multiprocessing import Manager, Process, cpu_count import networkx as nx from osaca.semantics import INSTR_FLAGS, ArchSemantics, MachineModel +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand +from osaca.parser.flag import FlagOperand class KernelDG(nx.DiGraph): @@ -59,43 +63,42 @@ class KernelDG(nx.DiGraph): # 3. get LT value and set as edge weight dg = nx.DiGraph() for i, instruction_form in enumerate(kernel): - dg.add_node(instruction_form["line_number"]) - dg.nodes[instruction_form["line_number"]]["instruction_form"] = instruction_form + dg.add_node(instruction_form.line_number) + dg.nodes[instruction_form.line_number]["instruction_form"] = instruction_form # add load as separate node if existent if ( - INSTR_FLAGS.HAS_LD in instruction_form["flags"] - and INSTR_FLAGS.LD not in instruction_form["flags"] + INSTR_FLAGS.HAS_LD in instruction_form.flags + and INSTR_FLAGS.LD not in instruction_form.flags ): # add new node - dg.add_node(instruction_form["line_number"] + 0.1) - dg.nodes[instruction_form["line_number"] + 0.1][ - "instruction_form" - ] = instruction_form + dg.add_node(instruction_form.line_number + 0.1) + dg.nodes[instruction_form.line_number + 0.1]["instruction_form"] = instruction_form # and set LD latency as edge weight dg.add_edge( - instruction_form["line_number"] + 0.1, - instruction_form["line_number"], - latency=instruction_form["latency"] - instruction_form["latency_wo_load"], + instruction_form.line_number + 0.1, + instruction_form.line_number, + latency=instruction_form.latency - instruction_form.latency_wo_load, ) for dep, dep_flags in self.find_depending( instruction_form, kernel[i + 1 :], flag_dependencies ): + # print(instruction_form.line_number,"\t",dep.line_number,"\n") edge_weight = ( - instruction_form["latency"] - if "mem_dep" in dep_flags or "latency_wo_load" not in instruction_form - else instruction_form["latency_wo_load"] + instruction_form.latency + if "mem_dep" in dep_flags or instruction_form.latency_wo_load is None + else instruction_form.latency_wo_load ) if "storeload_dep" in dep_flags and self.model is not None: edge_weight += self.model.get("store_to_load_forward_latency", 0) if "p_indexed" in dep_flags and self.model is not None: edge_weight = self.model.get("p_index_latency", 1) dg.add_edge( - instruction_form["line_number"], - dep["line_number"], + instruction_form.line_number, + dep.line_number, latency=edge_weight, ) - dg.nodes[dep["line_number"]]["instruction_form"] = dep + dg.nodes[dep.line_number]["instruction_form"] = dep return dg def check_for_loopcarried_dep(self, kernel, timeout=10, flag_dependencies=False): @@ -114,7 +117,7 @@ class KernelDG(nx.DiGraph): tmp_kernel = [] + kernel for orig_iform in kernel: temp_iform = copy.copy(orig_iform) - temp_iform["line_number"] += offset + temp_iform.line_number += offset tmp_kernel.append(temp_iform) # get dependency graph dg = self.create_DG(tmp_kernel, flag_dependencies) @@ -224,26 +227,26 @@ class KernelDG(nx.DiGraph): def get_critical_path(self): """Find and return critical path after the creation of a directed graph.""" - max_latency_instr = max(self.kernel, key=lambda k: k["latency"]) + max_latency_instr = max(self.kernel, key=lambda k: k.latency) if nx.algorithms.dag.is_directed_acyclic_graph(self.dg): longest_path = nx.algorithms.dag.dag_longest_path(self.dg, weight="latency") # TODO verify that we can remove the next two lince due to earlier initialization for line_number in longest_path: - self._get_node_by_lineno(int(line_number))["latency_cp"] = 0 + self._get_node_by_lineno(int(line_number)).latency_cp = 0 # set cp latency to instruction path_latency = 0.0 for s, d in nx.utils.pairwise(longest_path): node = self._get_node_by_lineno(int(s)) - node["latency_cp"] = self.dg.edges[(s, d)]["latency"] - path_latency += node["latency_cp"] + node.latency_cp = self.dg.edges[(s, d)]["latency"] + path_latency += node.latency_cp # add latency for last instruction node = self._get_node_by_lineno(int(longest_path[-1])) - node["latency_cp"] = node["latency"] - if max_latency_instr["latency"] > path_latency: - max_latency_instr["latency_cp"] = float(max_latency_instr["latency"]) + node.latency_cp = node.latency + if max_latency_instr.latency > path_latency: + max_latency_instr.latency_cp = float(max_latency_instr.latency) return [max_latency_instr] else: - return [x for x in self.kernel if x["line_number"] in longest_path] + return [x for x in self.kernel if x.line_number in longest_path] else: # split to DAG raise NotImplementedError("Kernel is cyclic.") @@ -272,8 +275,8 @@ class KernelDG(nx.DiGraph): if instruction_form.semantic_operands is None: return for dst in chain( - instruction_form.semantic_operands.destination, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ): # TODO instructions before must be considered as well, if they update registers # not used by insruction_form. E.g., validation/build/A64FX/gcc/O1/gs-2d-5pt.marked.s @@ -282,27 +285,31 @@ class KernelDG(nx.DiGraph): for i, instr_form in enumerate(instructions): self._update_reg_changes(instr_form, register_changes) # print(" TO", instr_form.line, register_changes) - if "register" in dst: + if isinstance(dst, RegisterOperand): # read of register - if self.is_read(dst.register, instr_form): - if dst.get("pre_indexed", False) or dst.get("post_indexed", False): + if self.is_read(dst, instr_form): + if ( + dst.pre_indexed + or dst.post_indexed + or (isinstance(dst.post_indexed, dict)) + ): yield instr_form, ["p_indexed"] else: yield instr_form, [] # write to register -> abort - if self.is_written(dst.register, instr_form): + if self.is_written(dst, instr_form): break - if "flag" in dst and flag_dependencies: + if isinstance(dst, FlagOperand) and flag_dependencies: # read of flag - if self.is_read(dst.flag, instr_form): + if self.is_read(dst, instr_form): yield instr_form, [] # write to flag -> abort - if self.is_written(dst.flag, instr_form): + if self.is_written(dst, instr_form): break - if "memory" in dst: + if isinstance(dst, MemoryOperand): # base register is altered during memory access - if "pre_indexed" in dst.memory: - if self.is_written(dst.memory.base, instr_form): + if dst.pre_indexed: + if self.is_written(dst.base, instr_form): break # if dst.memory.base: # if self.is_read(dst.memory.base, instr_form): @@ -310,18 +317,18 @@ class KernelDG(nx.DiGraph): # if dst.memory.index: # if self.is_read(dst.memory.index, instr_form): # yield instr_form, [] - if "post_indexed" in dst.memory: + if dst.post_indexed: # Check for read of base register until overwrite - if self.is_written(dst.memory.base, instr_form): + if self.is_written(dst.base, instr_form): break # TODO record register changes # (e.g., mov, leaadd, sub, inc, dec) in instructions[:i] # and pass to is_memload and is_memstore to consider relevance. # load from same location (presumed) - if self.is_memload(dst.memory, instr_form, register_changes): + if self.is_memload(dst, instr_form, register_changes): yield instr_form, ["storeload_dep"] # store to same location (presumed) - if self.is_memstore(dst.memory, instr_form, register_changes): + if self.is_memstore(dst, instr_form, register_changes): break self._update_reg_changes(instr_form, register_changes, only_postindexed=True) @@ -365,32 +372,28 @@ class KernelDG(nx.DiGraph): if instruction_form.semantic_operands is None: return is_read for src in chain( - instruction_form.semantic_operands.source, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["source"], + instruction_form.semantic_operands["src_dst"], ): - if "register" in src: - is_read = self.parser.is_reg_dependend_of(register, src.register) or is_read - if "flag" in src: - is_read = self.parser.is_flag_dependend_of(register, src.flag) or is_read - if "memory" in src: - if src.memory.base is not None: - is_read = self.parser.is_reg_dependend_of(register, src.memory.base) or is_read - if src.memory.index is not None: - is_read = ( - self.parser.is_reg_dependend_of(register, src.memory.index) or is_read - ) + if isinstance(src, RegisterOperand): + is_read = self.parser.is_reg_dependend_of(register, src) or is_read + if isinstance(src, FlagOperand): + is_read = self.parser.is_flag_dependend_of(register, src) or is_read + if isinstance(src, MemoryOperand): + if src.base is not None: + is_read = self.parser.is_reg_dependend_of(register, src.base) or is_read + if src.index is not None and isinstance(src.index, RegisterOperand): + is_read = self.parser.is_reg_dependend_of(register, src.index) or is_read # Check also if read in destination memory address for dst in chain( - instruction_form.semantic_operands.destination, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ): - if "memory" in dst: - if dst.memory.base is not None: - is_read = self.parser.is_reg_dependend_of(register, dst.memory.base) or is_read - if dst.memory.index is not None: - is_read = ( - self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read - ) + if isinstance(dst, MemoryOperand): + if dst.base is not None: + is_read = self.parser.is_reg_dependend_of(register, dst.base) or is_read + if dst.index is not None: + is_read = self.parser.is_reg_dependend_of(register, dst.index) or is_read return is_read def is_memload(self, mem, instruction_form, register_changes={}): @@ -398,29 +401,37 @@ class KernelDG(nx.DiGraph): if instruction_form.semantic_operands is None: return False for src in chain( - instruction_form.semantic_operands.source, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["source"], + instruction_form.semantic_operands["src_dst"], ): # Here we check for mem dependecies only - if "memory" not in src: + if not isinstance(src, MemoryOperand): continue - src = src.memory + # src = src.memory # determine absolute address change addr_change = 0 - if src.offset and "value" in src.offset: + if isinstance(src.offset, ImmediateOperand) and src.offset.value is not None: addr_change += src.offset.value if mem.offset: addr_change -= mem.offset.value if mem.base and src.base: base_change = register_changes.get( - src.base.get("prefix", "") + src.base.name, - {"name": src.base.get("prefix", "") + src.base.name, "value": 0}, + (src.base.prefix if src.base.prefix is not None else "") + src.base.name, + { + "name": (src.base.prefix if src.base.prefix is not None else "") + + src.base.name, + "value": 0, + }, ) if base_change is None: # Unknown change occurred continue - if mem.base.get("prefix", "") + mem.base["name"] != base_change["name"]: + if ( + mem.base.prefix + if mem.base.prefix is not None + else "" + mem.base.name != base_change["name"] + ): # base registers do not match continue addr_change += base_change["value"] @@ -429,8 +440,12 @@ class KernelDG(nx.DiGraph): continue if mem.index and src.index: index_change = register_changes.get( - src.index.get("prefix", "") + src.index.name, - {"name": src.index.get("prefix", "") + src.index.name, "value": 0}, + (src.index.prefix if src.index.prefix is not None else "") + src.index.name, + { + "name": (src.index.prefix if src.index.prefix is not None else "") + + src.index.name, + "value": 0, + }, ) if index_change is None: # Unknown change occurred @@ -438,7 +453,11 @@ class KernelDG(nx.DiGraph): if mem.scale != src.scale: # scale factors do not match continue - if mem.index.get("prefix", "") + mem.index["name"] != index_change["name"]: + if ( + mem.index.prefix + if mem.index.prefix is not None + else "" + mem.index.name != index_change["name"] + ): # index registers do not match continue addr_change += index_change["value"] * src.scale @@ -456,28 +475,24 @@ class KernelDG(nx.DiGraph): if instruction_form.semantic_operands is None: return is_written for dst in chain( - instruction_form.semantic_operands.destination, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ): - if "register" in dst: - is_written = self.parser.is_reg_dependend_of(register, dst.register) or is_written - if "flag" in dst: - is_written = self.parser.is_flag_dependend_of(register, dst.flag) or is_written - if "memory" in dst: - if "pre_indexed" in dst.memory or "post_indexed" in dst.memory: - is_written = ( - self.parser.is_reg_dependend_of(register, dst.memory.base) or is_written - ) + if isinstance(dst, RegisterOperand): + is_written = self.parser.is_reg_dependend_of(register, dst) or is_written + if isinstance(dst, FlagOperand): + is_written = self.parser.is_flag_dependend_of(register, dst) or is_written + if isinstance(dst, MemoryOperand): + if dst.pre_indexed or dst.post_indexed: + is_written = self.parser.is_reg_dependend_of(register, dst.base) or is_written # Check also for possible pre- or post-indexing in memory addresses for src in chain( - instruction_form.semantic_operands.source, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["source"], + instruction_form.semantic_operands["src_dst"], ): - if "memory" in src: - if "pre_indexed" in src.memory or "post_indexed" in src.memory: - is_written = ( - self.parser.is_reg_dependend_of(register, src.memory.base) or is_written - ) + if isinstance(src, MemoryOperand): + if src.pre_indexed or src.post_indexed: + is_written = self.parser.is_reg_dependend_of(register, src.base) or is_written return is_written def is_memstore(self, mem, instruction_form, register_changes={}): @@ -486,11 +501,11 @@ class KernelDG(nx.DiGraph): if instruction_form.semantic_operands is None: return is_store for dst in chain( - instruction_form.semantic_operands.destination, - instruction_form.semantic_operands.src_dst, + instruction_form.semantic_operands["destination"], + instruction_form.semantic_operands["src_dst"], ): - if "memory" in dst: - is_store = mem == dst["memory"] or is_store + if isinstance(dst, MemoryOperand): + is_store = mem == dst or is_store return is_store def export_graph(self, filepath=None): @@ -503,11 +518,11 @@ class KernelDG(nx.DiGraph): """ graph = copy.deepcopy(self.dg) cp = self.get_critical_path() - cp_line_numbers = [x["line_number"] for x in cp] + cp_line_numbers = [x.line_number for x in cp] lcd = self.get_loopcarried_dependencies() lcd_line_numbers = {} for dep in lcd: - lcd_line_numbers[dep] = [x["line_number"] for x, lat in lcd[dep]["dependencies"]] + lcd_line_numbers[dep] = [x.line_number for x, lat in lcd[dep]["dependencies"]] # add color scheme graph.graph["node"] = {"colorscheme": "accent8"} graph.graph["edge"] = {"colorscheme": "accent8"} @@ -518,7 +533,7 @@ class KernelDG(nx.DiGraph): max_line_number = max(lcd_line_numbers[dep]) graph.add_edge(max_line_number, min_line_number) graph.edges[max_line_number, min_line_number]["latency"] = [ - lat for x, lat in lcd[dep]["dependencies"] if x["line_number"] == max_line_number + lat for x, lat in lcd[dep]["dependencies"] if x.line_number == max_line_number ] # add label to edges @@ -527,7 +542,7 @@ class KernelDG(nx.DiGraph): # add CP values to graph for n in cp: - graph.nodes[n["line_number"]]["instruction_form"]["latency_cp"] = n["latency_cp"] + graph.nodes[n.line_number]["instruction_form"].latency_cp = n.latency_cp # color CP and LCD for n in graph.nodes: @@ -546,8 +561,8 @@ class KernelDG(nx.DiGraph): # color edges for e in graph.edges: if ( - graph.nodes[e[0]]["instruction_form"]["line_number"] in cp_line_numbers - and graph.nodes[e[1]]["instruction_form"]["line_number"] in cp_line_numbers + graph.nodes[e[0]]["instruction_form"].line_number in cp_line_numbers + and graph.nodes[e[1]]["instruction_form"].line_number in cp_line_numbers and e[0] < e[1] ): bold_edge = True @@ -559,9 +574,8 @@ class KernelDG(nx.DiGraph): graph.edges[e]["penwidth"] = 3 for dep in lcd_line_numbers: if ( - graph.nodes[e[0]]["instruction_form"]["line_number"] in lcd_line_numbers[dep] - and graph.nodes[e[1]]["instruction_form"]["line_number"] - in lcd_line_numbers[dep] + graph.nodes[e[0]]["instruction_form"].line_number in lcd_line_numbers[dep] + and graph.nodes[e[1]]["instruction_form"].line_number in lcd_line_numbers[dep] ): graph.edges[e]["color"] = graph.nodes[e[1]]["fillcolor"] @@ -574,12 +588,12 @@ class KernelDG(nx.DiGraph): graph.nodes[n]["fontsize"] = 11.0 else: node = graph.nodes[n]["instruction_form"] - if node["instruction"] is not None: - mapping[n] = "{}: {}".format(n, node["instruction"]) + if node.mnemonic is not None: + mapping[n] = "{}: {}".format(n, node.mnemonic) else: - label = "label" if node["label"] else None - label = "directive" if node["directive"] else label - label = "comment" if node["comment"] and label is None else label + label = "label" if node.label is not None else None + label = "directive" if node.directive is not None else label + label = "comment" if node.comment is not None and label is None else label mapping[n] = "{}: {}".format(n, label) graph.nodes[n]["fontname"] = "italic" graph.nodes[n]["fontsize"] = 11.0 diff --git a/osaca/semantics/marker_utils.py b/osaca/semantics/marker_utils.py old mode 100755 new mode 100644 index 62a28b0..5f2eb4a --- a/osaca/semantics/marker_utils.py +++ b/osaca/semantics/marker_utils.py @@ -2,6 +2,9 @@ from collections import OrderedDict from osaca.parser import ParserAArch64, ParserX86ATT, get_parser +from osaca.parser.register import RegisterOperand +from osaca.parser.identifier import IdentifierOperand +from osaca.parser.immediate import ImmediateOperand COMMENT_MARKER = {"start": "OSACA-BEGIN", "end": "OSACA-END"} @@ -133,13 +136,13 @@ def find_marked_section( index_end = -1 for i, line in enumerate(lines): try: - if line.instruction is None and comments is not None and line.comment is not None: + if line.mnemonic is None and comments is not None and line.comment is not None: if comments["start"] == line.comment: index_start = i + 1 elif comments["end"] == line.comment: index_end = i elif ( - line.instruction in mov_instr + line.mnemonic in mov_instr and len(lines) > i + 1 and lines[i + 1].directive is not None ): @@ -147,10 +150,10 @@ def find_marked_section( destination = line.operands[1 if not reverse else 0] # instruction pair matches, check for operands if ( - "immediate" in source - and parser.normalize_imd(source.immediate) == mov_vals[0] - and "register" in destination - and parser.get_full_reg_name(destination.register) == mov_reg + isinstance(source, ImmediateOperand) + and parser.normalize_imd(source) == mov_vals[0] + and isinstance(destination, RegisterOperand) + and parser.get_full_reg_name(destination) == mov_reg ): # operands of first instruction match start, check for second one match, line_count = match_bytes(lines, i + 1, nop_bytes) @@ -158,10 +161,10 @@ def find_marked_section( # return first line after the marker index_start = i + 1 + line_count elif ( - "immediate" in source - and parser.normalize_imd(source.immediate) == mov_vals[1] - and "register" in destination - and parser.get_full_reg_name(destination.register) == mov_reg + isinstance(source, ImmediateOperand) + and parser.normalize_imd(source) == mov_vals[1] + and isinstance(destination, RegisterOperand) + and parser.get_full_reg_name(destination) == mov_reg ): # operand of first instruction match end, check for second one match, line_count = match_bytes(lines, i + 1, nop_bytes) @@ -203,14 +206,14 @@ def find_jump_labels(lines): labels = OrderedDict() current_label = None for i, line in enumerate(lines): - if line["label"] is not None: + if line.label is not None: # When a new label is found, add to blocks dict - labels[line["label"]] = (i,) + labels[line.label] = (i,) # End previous block at previous line if current_label is not None: labels[current_label] = (labels[current_label][0], i) # Update current block name - current_label = line["label"] + current_label = line.label elif current_label is None: # If no block has been started, skip end detection continue @@ -222,9 +225,9 @@ def find_jump_labels(lines): for label in list(labels): if all( [ - line["instruction"].startswith(".") + line.mnemonic.startswith(".") for line in lines[labels[label][0] : labels[label][1]] - if line["instruction"] is not None + if line.mnemonic is not None ] ): del labels[label] @@ -251,11 +254,11 @@ def find_basic_blocks(lines): terminate = False blocks[label].append(line) # Find end of block by searching for references to valid jump labels - if line["instruction"] and line["operands"]: - for operand in [o for o in line["operands"] if "identifier" in o]: - if operand["identifier"]["name"] in valid_jump_labels: + if line.mnemonic is not None and line.operands != []: + for operand in [o for o in line.operands if isinstance(o, IdentifierOperand)]: + if operand.name in valid_jump_labels: terminate = True - elif line["label"] is not None: + elif line.label is not None: terminate = True if terminate: break @@ -280,15 +283,15 @@ def find_basic_loop_bodies(lines): terminate = False current_block.append(line) # Find end of block by searching for references to valid jump labels - if line["instruction"] and line["operands"]: + if line.mnemonic is not None and line.operands != []: # Ignore `b.none` instructions (relevant von ARM SVE code) # This branch instruction is often present _within_ inner loop blocks, but usually # do not terminate - if line["instruction"] == "b.none": + if line.mnemonic == "b.none": continue - for operand in [o for o in line["operands"] if "identifier" in o]: - if operand["identifier"]["name"] in valid_jump_labels: - if operand["identifier"]["name"] == label: + for operand in [o for o in line.operands if isinstance(o, IdentifierOperand)]: + if operand.name in valid_jump_labels: + if operand.name == label: loop_bodies[label] = current_block terminate = True break diff --git a/tests/test_base_parser.py b/tests/test_base_parser.py index 77f92d0..9794ce9 100755 --- a/tests/test_base_parser.py +++ b/tests/test_base_parser.py @@ -6,7 +6,9 @@ Unit tests for base assembly parser import os import unittest -from osaca.parser import AttrDict, BaseParser +from osaca.parser import BaseParser +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand class TestBaseParser(unittest.TestCase): @@ -44,8 +46,8 @@ class TestBaseParser(unittest.TestCase): self.parser.parse_instruction(instr1) def test_register_funcs(self): - reg_a1 = AttrDict({"name": "rax"}) - reg_a2 = AttrDict({"name": "eax"}) + reg_a1 = RegisterOperand(name="rax") + reg_a2 = RegisterOperand(name="eax") register_string = "v1.2d" with self.assertRaises(NotImplementedError): self.parser.is_reg_dependend_of(reg_a1, reg_a2) @@ -61,7 +63,7 @@ class TestBaseParser(unittest.TestCase): self.parser.get_full_reg_name(reg_a1) def test_normalize_imd(self): - imd_hex_1 = {"value": "0x4f"} + imd_hex_1 = ImmediateOperand(value="0x4f") with self.assertRaises(NotImplementedError): self.parser.normalize_imd(imd_hex_1) diff --git a/tests/test_cli.py b/tests/test_cli.py index 11f04dc..47d1623 100755 --- a/tests/test_cli.py +++ b/tests/test_cli.py @@ -199,6 +199,7 @@ class TestCLI(unittest.TestCase): ) output = StringIO() osaca.run(args, output_file=output) + # WARNING for length self.assertTrue( output.getvalue().count( diff --git a/tests/test_db_interface.py b/tests/test_db_interface.py index a58a7a3..a5fd7c5 100755 --- a/tests/test_db_interface.py +++ b/tests/test_db_interface.py @@ -7,41 +7,40 @@ import unittest from io import StringIO import osaca.db_interface as dbi -from osaca.db_interface import sanity_check +from osaca.db_interface import sanity_check, _get_full_instruction_name from osaca.semantics import MachineModel +from osaca.parser import InstructionForm +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand +import copy class TestDBInterface(unittest.TestCase): @classmethod def setUpClass(self): - sample_entry = { - "name": "DoItRightAndDoItFast", - "operands": [ - { - "class": "memory", - "offset": "imd", - "base": "gpr", - "index": "gpr", - "scale": 8, - }, - {"class": "register", "name": "xmm"}, + sample_entry = InstructionForm( + mnemonic="DoItRightAndDoItFast", + operands=[ + MemoryOperand(offset="imd", base="gpr", index="gpr", scale=8), + RegisterOperand(name="xmm"), ], - "throughput": 1.25, - "latency": 125, - "uops": 6, - } - self.entry_csx = sample_entry.copy() - self.entry_tx2 = sample_entry.copy() - self.entry_zen1 = sample_entry.copy() + throughput=1.25, + latency=125, + uops=6, + ) - # self.entry_csx['port_pressure'] = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0] - self.entry_csx["port_pressure"] = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]] - # self.entry_tx2['port_pressure'] = [2.5, 2.5, 0, 0, 0.5, 0.5] - self.entry_tx2["port_pressure"] = [[5, "01"], [1, "45"]] - del self.entry_tx2["operands"][1]["name"] - self.entry_tx2["operands"][1]["prefix"] = "x" - # self.entry_zen1['port_pressure'] = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1] - self.entry_zen1["port_pressure"] = [ + self.entry_csx = copy.copy(sample_entry) + self.entry_tx2 = copy.copy(sample_entry) + self.entry_zen1 = copy.copy(sample_entry) + + self.entry_csx.port_pressure = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0] + self.entry_csx.port_pressure = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]] + self.entry_tx2.port_pressure = [2.5, 2.5, 0, 0, 0.5, 0.5] + self.entry_tx2.port_pressure = [[5, "01"], [1, "45"]] + self.entry_tx2.operands[1].name = None + self.entry_tx2.operands[1].prefix = "x" + self.entry_zen1.port_pressure = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1] + self.entry_zen1.port_pressure = [ [4, "0123"], [1, "4"], [1, "89"], @@ -62,7 +61,7 @@ class TestDBInterface(unittest.TestCase): mm_csx.set_instruction_entry(self.entry_csx) mm_tx2.set_instruction_entry(self.entry_tx2) - mm_zen1.set_instruction_entry({"name": "empty_operation"}) + mm_zen1.set_instruction_entry(InstructionForm(mnemonic="empty_operation")) num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2 @@ -73,7 +72,7 @@ class TestDBInterface(unittest.TestCase): self.assertEqual(num_entries_zen1, 1) def test_invalid_add(self): - entry = {} + entry = InstructionForm() with self.assertRaises(KeyError): MachineModel("csx").set_instruction_entry(entry) with self.assertRaises(TypeError): @@ -98,15 +97,15 @@ class TestDBInterface(unittest.TestCase): entries = dbi._get_ibench_output(input_data, "x86") self.assertEqual(len(entries), 3) for _, e in entries.items(): - self.assertIsNotNone(e["throughput"]) - self.assertIsNotNone(e["latency"]) + self.assertIsNotNone(e.throughput) + self.assertIsNotNone(e.latency) with open(self._find_file("ibench_import_aarch64.dat")) as input_file: input_data = input_file.readlines() entries = dbi._get_ibench_output(input_data, "aarch64") self.assertEqual(len(entries), 4) for _, e in entries.items(): - self.assertIsNotNone(e["throughput"]) - self.assertIsNotNone(e["latency"]) + self.assertIsNotNone(e.throughput) + self.assertIsNotNone(e.latency) def test_asmbench_import(self): # only check import without dumping the DB file (takes too much time) @@ -115,15 +114,15 @@ class TestDBInterface(unittest.TestCase): entries = dbi._get_asmbench_output(input_data, "x86") self.assertEqual(len(entries), 3) for _, e in entries.items(): - self.assertIsNotNone(e["throughput"]) - self.assertIsNotNone(e["latency"]) + self.assertIsNotNone(e.throughput) + self.assertIsNotNone(e.latency) with open(self._find_file("asmbench_import_aarch64.dat")) as input_file: input_data = input_file.readlines() entries = dbi._get_asmbench_output(input_data, "aarch64") self.assertEqual(len(entries), 4) for _, e in entries.items(): - self.assertIsNotNone(e["throughput"]) - self.assertIsNotNone(e["latency"]) + self.assertIsNotNone(e.throughput) + self.assertIsNotNone(e.latency) # remove empty line => no import since broken format del input_data[3] entries = dbi._get_asmbench_output(input_data, "aarch64") @@ -147,6 +146,34 @@ class TestDBInterface(unittest.TestCase): instr_3 = ["vfmadd132pd", (True, "")] self.assertEqual(dbi._scrape_from_felixcloutier(instr_3[0]), instr_3[1]) + def test_human_readable_instr_name(self): + instr_form_x86 = dict( + name="vaddpd", + operands=[ + RegisterOperand(name="xmm"), + RegisterOperand(name="xmm"), + RegisterOperand(name="xmm"), + ], + ) + instr_form_arm = dict( + name="fadd", + operands=[ + RegisterOperand(prefix="v", shape="s"), + RegisterOperand(prefix="v", shape="s"), + RegisterOperand(prefix="v", shape="s"), + ], + ) + # test full instruction name + self.assertEqual( + _get_full_instruction_name(instr_form_x86), + "vaddpd register(name:xmm),register(name:xmm),register(name:xmm)", + ) + self.assertEqual( + _get_full_instruction_name(instr_form_arm), + "fadd register(prefix:v,shape:s),register(prefix:v,shape:s)," + + "register(prefix:v,shape:s)", + ) + ################## # Helper functions ################## diff --git a/tests/test_files/test_db_aarch64.yml b/tests/test_files/test_db_aarch64.yml index 5378602..78ee895 100644 --- a/tests/test_files/test_db_aarch64.yml +++ b/tests/test_files/test_db_aarch64.yml @@ -8,22 +8,22 @@ scheduler_size: 60 hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '34'], [1, '012']]} load_throughput_default: [[1, '34']] store_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[2, '34'], [2, '5']]} +- {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[2, '34'], [2, '5']]} store_throughput_default: [[1, '34'], [1, '5']] ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5'] port_model_scheme: | @@ -307,8 +307,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34']] @@ -323,8 +323,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -339,8 +339,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34']] @@ -355,8 +355,8 @@ instruction_forms: offset: ~ index: ~ scale: 1 - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -371,8 +371,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34']] @@ -387,8 +387,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true - post-indexed: false + pre_indexed: true + post_indexed: false throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -403,8 +403,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 4.0 # 2*p34 port_pressure: [[2.0, '34'], [1, '012']] @@ -417,8 +417,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1.0, '34']] @@ -431,8 +431,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1.0, '34']] @@ -445,8 +445,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1.0, '34']] @@ -459,8 +459,8 @@ instruction_forms: offset: imd index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1.0, '34']] @@ -473,8 +473,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - post-indexed: false - pre-indexed: false + post_indexed: false + pre_indexed: false throughput: 0.5 latency: 4.0 # 1*p34 port_pressure: [[1.0, '34']] @@ -536,8 +536,8 @@ instruction_forms: offset: imd index: ~ scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: ~ latency: ~ port_pressure: [] @@ -552,8 +552,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p34+2*p5 port_pressure: [[2.0, '34'], [2.0, '5']] @@ -568,8 +568,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 2.0 latency: 0 # 2*p34+2*p5+1*012 port_pressure: [[2.0, '34'], [2.0, '5'], [1, '012']] @@ -584,8 +584,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 2.0 latency: 0 # 2*p34+2*p5 port_pressure: [[2.0, '34'], [2.0, '5']] @@ -598,8 +598,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -612,8 +612,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 4.0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -626,8 +626,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -640,8 +640,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -654,8 +654,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] @@ -668,8 +668,8 @@ instruction_forms: offset: '*' index: '*' scale: 1 - pre-indexed: false - post-indexed: false + pre_indexed: false + post_indexed: false throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5']] @@ -682,8 +682,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] @@ -696,8 +696,8 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: false - post-indexed: true + pre_indexed: false + post_indexed: true throughput: 1.0 latency: 0 # 1*p34+1*p5 port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] diff --git a/tests/test_frontend.py b/tests/test_frontend.py index 58780da..1436bd0 100755 --- a/tests/test_frontend.py +++ b/tests/test_frontend.py @@ -41,6 +41,7 @@ class TestFrontend(unittest.TestCase): self.machine_model_tx2, path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "isa/aarch64.yml"), ) + for i in range(len(self.kernel_x86)): self.semantics_csx.assign_src_dst(self.kernel_x86[i]) self.semantics_csx.assign_tp_lt(self.kernel_x86[i]) @@ -89,28 +90,28 @@ class TestFrontend(unittest.TestCase): self.assertEqual("csx", analysis_dict["Header"]["Architecture"]) self.assertEqual(len(analysis_dict["Warnings"]), 0) for i, line in enumerate(self.kernel_x86): - self.assertEqual(line["throughput"], analysis_dict["Kernel"][i]["Throughput"]) - self.assertEqual(line["latency"], analysis_dict["Kernel"][i]["Latency"]) + self.assertEqual(line.throughput, analysis_dict["Kernel"][i]["Throughput"]) + self.assertEqual(line.latency, analysis_dict["Kernel"][i]["Latency"]) self.assertEqual( - line["latency_wo_load"], analysis_dict["Kernel"][i]["LatencyWithoutLoad"] + line.latency_wo_load, analysis_dict["Kernel"][i]["LatencyWithoutLoad"] ) - self.assertEqual(line["latency_cp"], analysis_dict["Kernel"][i]["LatencyCP"]) - self.assertEqual(line["instruction"], analysis_dict["Kernel"][i]["Instruction"]) - self.assertEqual(len(line["operands"]), len(analysis_dict["Kernel"][i]["Operands"])) + self.assertEqual(line.latency_cp, analysis_dict["Kernel"][i]["LatencyCP"]) + self.assertEqual(line.mnemonic, analysis_dict["Kernel"][i]["Instruction"]) + self.assertEqual(len(line.operands), len(analysis_dict["Kernel"][i]["Operands"])) self.assertEqual( - len(line["semantic_operands"]["source"]), + len(line.semantic_operands["source"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["source"]), ) self.assertEqual( - len(line["semantic_operands"]["destination"]), + len(line.semantic_operands["destination"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["destination"]), ) self.assertEqual( - len(line["semantic_operands"]["src_dst"]), + len(line.semantic_operands["src_dst"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["src_dst"]), ) - self.assertEqual(line["flags"], analysis_dict["Kernel"][i]["Flags"]) - self.assertEqual(line["line_number"], analysis_dict["Kernel"][i]["LineNumber"]) + self.assertEqual(line.flags, analysis_dict["Kernel"][i]["Flags"]) + self.assertEqual(line.line_number, analysis_dict["Kernel"][i]["LineNumber"]) def test_dict_output_AArch64(self): reduced_kernel = reduce_to_section(self.kernel_AArch64, self.semantics_tx2._isa) @@ -126,28 +127,28 @@ class TestFrontend(unittest.TestCase): self.assertEqual("tx2", analysis_dict["Header"]["Architecture"]) self.assertEqual(len(analysis_dict["Warnings"]), 0) for i, line in enumerate(reduced_kernel): - self.assertEqual(line["throughput"], analysis_dict["Kernel"][i]["Throughput"]) - self.assertEqual(line["latency"], analysis_dict["Kernel"][i]["Latency"]) + self.assertEqual(line.throughput, analysis_dict["Kernel"][i]["Throughput"]) + self.assertEqual(line.latency, analysis_dict["Kernel"][i]["Latency"]) self.assertEqual( - line["latency_wo_load"], analysis_dict["Kernel"][i]["LatencyWithoutLoad"] + line.latency_wo_load, analysis_dict["Kernel"][i]["LatencyWithoutLoad"] ) - self.assertEqual(line["latency_cp"], analysis_dict["Kernel"][i]["LatencyCP"]) - self.assertEqual(line["instruction"], analysis_dict["Kernel"][i]["Instruction"]) - self.assertEqual(len(line["operands"]), len(analysis_dict["Kernel"][i]["Operands"])) + self.assertEqual(line.latency_cp, analysis_dict["Kernel"][i]["LatencyCP"]) + self.assertEqual(line.mnemonic, analysis_dict["Kernel"][i]["Instruction"]) + self.assertEqual(len(line.operands), len(analysis_dict["Kernel"][i]["Operands"])) self.assertEqual( - len(line["semantic_operands"]["source"]), + len(line.semantic_operands["source"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["source"]), ) self.assertEqual( - len(line["semantic_operands"]["destination"]), + len(line.semantic_operands["destination"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["destination"]), ) self.assertEqual( - len(line["semantic_operands"]["src_dst"]), + len(line.semantic_operands["src_dst"]), len(analysis_dict["Kernel"][i]["SemanticOperands"]["src_dst"]), ) - self.assertEqual(line["flags"], analysis_dict["Kernel"][i]["Flags"]) - self.assertEqual(line["line_number"], analysis_dict["Kernel"][i]["LineNumber"]) + self.assertEqual(line.flags, analysis_dict["Kernel"][i]["Flags"]) + self.assertEqual(line.line_number, analysis_dict["Kernel"][i]["LineNumber"]) ################## # Helper functions diff --git a/tests/test_marker_utils.py b/tests/test_marker_utils.py index b6dd515..49da8e8 100755 --- a/tests/test_marker_utils.py +++ b/tests/test_marker_utils.py @@ -285,6 +285,7 @@ class TestMarkerUtils(unittest.TestCase): else: kernel_start = 0 parsed_kernel = self.parser_x86.parse_file(kernel, start_line=kernel_start) + self.assertEqual( test_kernel, parsed_kernel, @@ -356,7 +357,7 @@ class TestMarkerUtils(unittest.TestCase): def test_find_basic_blocks(self): self.assertEqual( [ - (k, v[0]["line_number"], v[-1]["line_number"]) + (k, v[0].line_number, v[-1].line_number) for k, v in find_basic_blocks(self.parsed_x86).items() ], [ @@ -380,7 +381,7 @@ class TestMarkerUtils(unittest.TestCase): self.assertEqual( [ - (k, v[0]["line_number"], v[-1]["line_number"]) + (k, v[0].line_number, v[-1].line_number) for k, v in find_basic_blocks(self.parsed_AArch).items() ], [ @@ -420,7 +421,7 @@ class TestMarkerUtils(unittest.TestCase): def test_find_basic_loop_body(self): self.assertEqual( [ - (k, v[0]["line_number"], v[-1]["line_number"]) + (k, v[0].line_number, v[-1].line_number) for k, v in find_basic_loop_bodies(self.parsed_x86).items() ], [(".L4", 66, 74), (".L10", 146, 154), (".L28", 290, 300)], @@ -428,7 +429,7 @@ class TestMarkerUtils(unittest.TestCase): self.assertEqual( [ - (k, v[0]["line_number"], v[-1]["line_number"]) + (k, v[0].line_number, v[-1].line_number) for k, v in find_basic_loop_bodies(self.parsed_AArch).items() ], [ diff --git a/tests/test_parser_AArch64.py b/tests/test_parser_AArch64.py index c9ffc76..c895c99 100755 --- a/tests/test_parser_AArch64.py +++ b/tests/test_parser_AArch64.py @@ -8,7 +8,13 @@ import unittest from pyparsing import ParseException -from osaca.parser import AttrDict, ParserAArch64 +from osaca.parser import ParserAArch64, InstructionForm +from osaca.parser.directive import DirectiveOperand +from osaca.parser.memory import MemoryOperand +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand +from osaca.parser.identifier import IdentifierOperand +from osaca.parser.prefetch import PrefetchOperand class TestParserAArch64(unittest.TestCase): @@ -33,42 +39,42 @@ class TestParserAArch64(unittest.TestCase): ) def test_label_parser(self): - self.assertEqual(self._get_label(self.parser, "main:").name, "main") - self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10") - self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3") - self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1").name, ".L1") + self.assertEqual(self._get_label(self.parser, "main:")[0].name, "main") + self.assertEqual(self._get_label(self.parser, "..B1.10:")[0].name, "..B1.10") + self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:")[0].name, ".2.3_2_pack.3") + self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1")[0].name, ".L1") self.assertEqual( - " ".join(self._get_label(self.parser, ".L1:\t\t\t//label1").comment), + " ".join(self._get_label(self.parser, ".L1:\t\t\t//label1")[1]), "label1", ) with self.assertRaises(ParseException): self._get_label(self.parser, "\t.cfi_startproc") def test_directive_parser(self): - self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text") - self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0) - self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align") - self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2) + self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text") + self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0) + self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align") self.assertEqual( - self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90" + len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2 + ) + self.assertEqual( + self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90" ) self.assertEqual( self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[ - "name" - ], + 0 + ].name, "byte", ) self.assertEqual( self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[ - "parameters" - ][2], + 0 + ].parameters[2], "144", ) self.assertEqual( " ".join( - self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[ - "comment" - ] + self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[1] ), "IACA START", ) @@ -102,70 +108,70 @@ class TestParserAArch64(unittest.TestCase): parsed_8 = self.parser.parse_instruction(instr8) parsed_9 = self.parser.parse_instruction(instr9) - self.assertEqual(parsed_1.instruction, "vcvt.F32.S32") - self.assertEqual(parsed_1.operands[0].register.name, "1") - self.assertEqual(parsed_1.operands[0].register.prefix, "w") - self.assertEqual(parsed_1.operands[1].register.name, "2") - self.assertEqual(parsed_1.operands[1].register.prefix, "w") + self.assertEqual(parsed_1.mnemonic, "vcvt.F32.S32") + self.assertEqual(parsed_1.operands[0].name, "1") + self.assertEqual(parsed_1.operands[0].prefix, "w") + self.assertEqual(parsed_1.operands[1].name, "2") + self.assertEqual(parsed_1.operands[1].prefix, "w") self.assertEqual(parsed_1.comment, "12.27") - self.assertEqual(parsed_2.instruction, "b.lo") - self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4") + self.assertEqual(parsed_2.mnemonic, "b.lo") + self.assertEqual(parsed_2.operands[0].name, "..B1.4") self.assertEqual(len(parsed_2.operands), 1) self.assertIsNone(parsed_2.comment) - self.assertEqual(parsed_3.instruction, "mov") - self.assertEqual(parsed_3.operands[0].register.name, "2") - self.assertEqual(parsed_3.operands[0].register.prefix, "x") - self.assertEqual(parsed_3.operands[1].immediate.value, int("0x222", 0)) + self.assertEqual(parsed_3.mnemonic, "mov") + self.assertEqual(parsed_3.operands[0].name, "2") + self.assertEqual(parsed_3.operands[0].prefix, "x") + self.assertEqual(parsed_3.operands[1].value, int("0x222", 0)) self.assertEqual(parsed_3.comment, "NOT IACA END") - self.assertEqual(parsed_4.instruction, "str") - self.assertIsNone(parsed_4.operands[1].memory.offset) - self.assertEqual(parsed_4.operands[1].memory.base.name, "sp") - self.assertEqual(parsed_4.operands[1].memory.base.prefix, "x") - self.assertEqual(parsed_4.operands[1].memory.index.name, "1") - self.assertEqual(parsed_4.operands[1].memory.index.prefix, "x") - self.assertEqual(parsed_4.operands[1].memory.scale, 16) - self.assertEqual(parsed_4.operands[0].register.name, "28") - self.assertEqual(parsed_4.operands[0].register.prefix, "x") + self.assertEqual(parsed_4.mnemonic, "str") + self.assertIsNone(parsed_4.operands[1].offset) + self.assertEqual(parsed_4.operands[1].base.name, "sp") + self.assertEqual(parsed_4.operands[1].base.prefix, "x") + self.assertEqual(parsed_4.operands[1].index.name, "1") + self.assertEqual(parsed_4.operands[1].index.prefix, "x") + self.assertEqual(parsed_4.operands[1].scale, 16) + self.assertEqual(parsed_4.operands[0].name, "28") + self.assertEqual(parsed_4.operands[0].prefix, "x") self.assertEqual(parsed_4.comment, "12.9") - self.assertEqual(parsed_5.instruction, "ldr") - self.assertEqual(parsed_5.operands[0].register.name, "0") - self.assertEqual(parsed_5.operands[0].register.prefix, "x") - self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "q2c") - self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation, ":got_lo12:") - self.assertEqual(parsed_5.operands[1].memory.base.name, "0") - self.assertEqual(parsed_5.operands[1].memory.base.prefix, "x") - self.assertIsNone(parsed_5.operands[1].memory.index) - self.assertEqual(parsed_5.operands[1].memory.scale, 1) + self.assertEqual(parsed_5.mnemonic, "ldr") + self.assertEqual(parsed_5.operands[0].name, "0") + self.assertEqual(parsed_5.operands[0].prefix, "x") + self.assertEqual(parsed_5.operands[1].offset.name, "q2c") + self.assertEqual(parsed_5.operands[1].offset.relocation, ":got_lo12:") + self.assertEqual(parsed_5.operands[1].base.name, "0") + self.assertEqual(parsed_5.operands[1].base.prefix, "x") + self.assertIsNone(parsed_5.operands[1].index) + self.assertEqual(parsed_5.operands[1].scale, 1) - self.assertEqual(parsed_6.instruction, "adrp") - self.assertEqual(parsed_6.operands[0].register.name, "0") - self.assertEqual(parsed_6.operands[0].register.prefix, "x") - self.assertEqual(parsed_6.operands[1].identifier.relocation, ":got:") - self.assertEqual(parsed_6.operands[1].identifier.name, "visited") + self.assertEqual(parsed_6.mnemonic, "adrp") + self.assertEqual(parsed_6.operands[0].name, "0") + self.assertEqual(parsed_6.operands[0].prefix, "x") + self.assertEqual(parsed_6.operands[1].relocation, ":got:") + self.assertEqual(parsed_6.operands[1].name, "visited") - self.assertEqual(parsed_7.instruction, "fadd") - self.assertEqual(parsed_7.operands[0].register.name, "17") - self.assertEqual(parsed_7.operands[0].register.prefix, "v") - self.assertEqual(parsed_7.operands[0].register.lanes, "2") - self.assertEqual(parsed_7.operands[0].register.shape, "d") - self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register), "v1.2d") + self.assertEqual(parsed_7.mnemonic, "fadd") + self.assertEqual(parsed_7.operands[0].name, "17") + self.assertEqual(parsed_7.operands[0].prefix, "v") + self.assertEqual(parsed_7.operands[0].lanes, "2") + self.assertEqual(parsed_7.operands[0].shape, "d") + self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2]), "v1.2d") - self.assertEqual(parsed_8.instruction, "mov.d") - self.assertEqual(parsed_8.operands[0].register.name, "0") - self.assertEqual(parsed_8.operands[0].register.prefix, "x") - self.assertEqual(parsed_8.operands[1].register.name, "16") - self.assertEqual(parsed_8.operands[1].register.prefix, "v") - self.assertEqual(parsed_8.operands[1].register.index, "1") - self.assertEqual(self.parser.get_full_reg_name(parsed_8.operands[1].register), "v16.d[1]") + self.assertEqual(parsed_8.mnemonic, "mov.d") + self.assertEqual(parsed_8.operands[0].name, "0") + self.assertEqual(parsed_8.operands[0].prefix, "x") + self.assertEqual(parsed_8.operands[1].name, "16") + self.assertEqual(parsed_8.operands[1].prefix, "v") + self.assertEqual(parsed_8.operands[1].index, "1") + self.assertEqual(self.parser.get_full_reg_name(parsed_8.operands[1]), "v16.d[1]") - self.assertEqual(parsed_9.instruction, "ccmp") - self.assertEqual(parsed_9.operands[0].register.name, "0") - self.assertEqual(parsed_9.operands[0].register.prefix, "x") - self.assertEqual(parsed_9.operands[3].condition, "CC") + self.assertEqual(parsed_9.mnemonic, "ccmp") + self.assertEqual(parsed_9.operands[0].name, "0") + self.assertEqual(parsed_9.operands[0].prefix, "x") + self.assertEqual(parsed_9.operands[3].ccode, "CC") def test_parse_line(self): line_comment = "// -- Begin main" @@ -178,149 +184,137 @@ class TestParserAArch64(unittest.TestCase): line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90" line_conditions = "ccmn x11, #1, #3, eq" - instruction_form_1 = { - "instruction": None, - "operands": [], - "directive": None, - "comment": "-- Begin main", - "label": None, - "line": "// -- Begin main", - "line_number": 1, - } + instruction_form_1 = InstructionForm( + mnemonic=None, + operands=[], + directive_id=None, + comment_id="-- Begin main", + label_id=None, + line="// -- Begin main", + line_number=1, + ) - instruction_form_2 = { - "instruction": None, - "operands": [], - "directive": None, - "comment": "=>This Inner Loop Header: Depth=1", - "label": ".LBB0_1", - "line": ".LBB0_1: // =>This Inner Loop Header: Depth=1", - "line_number": 2, - } - instruction_form_3 = { - "instruction": None, - "operands": [], - "directive": {"name": "cfi_def_cfa", "parameters": ["w29", "-16"]}, - "comment": None, - "label": None, - "line": ".cfi_def_cfa w29, -16", - "line_number": 3, - } - instruction_form_4 = { - "instruction": "ldr", - "operands": [ - {"register": {"prefix": "s", "name": "0"}}, - { - "memory": { - "offset": None, - "base": {"prefix": "x", "name": "11"}, - "index": { - "prefix": "w", - "name": "10", - "shift_op": "sxtw", - "immediate": {"value": "2"}, - "shift": [{"value": "2"}], - }, - "scale": 4, - } - }, + instruction_form_2 = InstructionForm( + mnemonic=None, + operands=[], + directive_id=None, + comment_id="=>This Inner Loop Header: Depth=1", + label_id=".LBB0_1", + line=".LBB0_1: // =>This Inner Loop Header: Depth=1", + line_number=2, + ) + instruction_form_3 = InstructionForm( + mnemonic=None, + operands=[], + directive_id=DirectiveOperand(name="cfi_def_cfa", parameters=["w29", "-16"]), + comment_id=None, + label_id=None, + line=".cfi_def_cfa w29, -16", + line_number=3, + ) + instruction_form_4 = InstructionForm( + mnemonic="ldr", + operands=[ + RegisterOperand(prefix="s", name="0"), + MemoryOperand( + offset=None, + base=RegisterOperand(prefix="x", name="11"), + index=RegisterOperand( + prefix="w", name="10", shift_op="sxtw", shift=[{"value": "2"}] + ), + scale=4, + ), ], - "directive": None, - "comment": "= <<2", - "label": None, - "line": "ldr s0, [x11, w10, sxtw #2] // = <<2", - "line_number": 4, - } - instruction_form_5 = { - "instruction": "prfm", - "operands": [ - {"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}}, - { - "memory": { - "offset": {"value": 2048}, - "base": {"prefix": "x", "name": "26"}, - "index": None, - "scale": 1, - } - }, + directive_id=None, + comment_id="= <<2", + label_id=None, + line="ldr s0, [x11, w10, sxtw #2] // = <<2", + line_number=4, + ) + instruction_form_5 = InstructionForm( + mnemonic="prfm", + operands=[ + PrefetchOperand(type_id=["PLD"], target=["L1"], policy=["KEEP"]), + MemoryOperand( + offset=ImmediateOperand(value=2048), + base=RegisterOperand(prefix="x", name="26"), + index=None, + scale=1, + ), ], - "directive": None, - "comment": "HPL", - "label": None, - "line": "prfm pldl1keep, [x26, #2048] //HPL", - "line_number": 5, - } - instruction_form_6 = { - "instruction": "stp", - "operands": [ - {"register": {"prefix": "x", "name": "29"}}, - {"register": {"prefix": "x", "name": "30"}}, - { - "memory": { - "offset": {"value": -16}, - "base": {"name": "sp", "prefix": "x"}, - "index": None, - "scale": 1, - "pre_indexed": True, - } - }, + directive_id=None, + comment_id="HPL", + label_id=None, + line="prfm pldl1keep, [x26, #2048] //HPL", + line_number=5, + ) + instruction_form_6 = InstructionForm( + mnemonic="stp", + operands=[ + RegisterOperand(prefix="x", name="29"), + RegisterOperand(prefix="x", name="30"), + MemoryOperand( + offset=ImmediateOperand(value=-16), + base=RegisterOperand(name="sp", prefix="x"), + index=None, + scale=1, + pre_indexed=True, + ), ], - "directive": None, - "comment": None, - "label": None, - "line": "stp x29, x30, [sp, #-16]!", - "line_number": 6, - } - instruction_form_7 = { - "instruction": "ldp", - "operands": [ - {"register": {"prefix": "q", "name": "2"}}, - {"register": {"prefix": "q", "name": "3"}}, - { - "memory": { - "offset": None, - "base": {"prefix": "x", "name": "11"}, - "index": None, - "scale": 1, - "post_indexed": {"value": 64}, - } - }, + directive_id=None, + comment_id=None, + label_id=None, + line="stp x29, x30, [sp, #-16]!", + line_number=6, + ) + instruction_form_7 = InstructionForm( + mnemonic="ldp", + operands=[ + RegisterOperand(prefix="q", name="2"), + RegisterOperand(prefix="q", name="3"), + MemoryOperand( + offset=None, + base=RegisterOperand(name="11", prefix="x"), + index=None, + scale=1, + post_indexed={"value": 64}, + ), ], - "directive": None, - "comment": None, - "label": None, - "line": "ldp q2, q3, [x11], #64", - "line_number": 7, - } - instruction_form_8 = { - "instruction": "fcmla", - "operands": [ - {"register": {"prefix": "z", "name": "26", "shape": "d"}}, - {"register": {"prefix": "p", "name": "0", "predication": "m"}}, - {"register": {"prefix": "z", "name": "29", "shape": "d"}}, - {"register": {"prefix": "z", "name": "21", "shape": "d"}}, - {"immediate": {"value": 90, "type": "int"}}, + directive_id=None, + comment_id=None, + label_id=None, + line="ldp q2, q3, [x11], #64", + line_number=7, + ) + instruction_form_8 = InstructionForm( + mnemonic="fcmla", + operands=[ + RegisterOperand(prefix="z", name="26", shape="d"), + RegisterOperand(prefix="p", name="0", predication="m"), + RegisterOperand(prefix="z", name="29", shape="d"), + RegisterOperand(prefix="z", name="21", shape="d"), + ImmediateOperand(value=90, imd_type="int"), ], - "directive": None, - "comment": None, - "label": None, - "line": "fcmla z26.d, p0/m, z29.d, z21.d, #90", - "line_number": 8, - } - instruction_form_9 = { - "instruction": "ccmn", - "operands": [ - {"register": {"prefix": "x", "name": "11"}}, - {"immediate": {"value": 1, "type": "int"}}, - {"immediate": {"value": 3, "type": "int"}}, + directive_id=None, + comment_id=None, + label_id=None, + line="fcmla z26.d, p0/m, z29.d, z21.d, #90", + line_number=8, + ) + instruction_form_9 = InstructionForm( + mnemonic="ccmn", + operands=[ + RegisterOperand(prefix="x", name="11"), + ImmediateOperand(value=1, imd_type="int"), + ImmediateOperand(value=3, imd_type="int"), {"condition": "EQ"}, ], - "directive": None, - "comment": None, - "label": None, - "line": "ccmn x11, #1, #3, eq", - "line_number": 9, - } + directive_id=None, + comment_id=None, + label_id=None, + line="ccmn x11, #1, #3, eq", + line_number=9, + ) parsed_1 = self.parser.parse_line(line_comment, 1) parsed_2 = self.parser.parse_line(line_label, 2) @@ -348,15 +342,23 @@ class TestParserAArch64(unittest.TestCase): self.assertEqual(len(parsed), 645) def test_normalize_imd(self): - imd_decimal_1 = {"value": "79"} - imd_hex_1 = {"value": "0x4f"} - imd_decimal_2 = {"value": "8"} - imd_hex_2 = {"value": "0x8"} - imd_float_11 = {"float": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}} - imd_float_12 = {"float": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}} - imd_double_11 = {"double": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}} - imd_double_12 = {"double": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}} - identifier = {"identifier": {"name": "..B1.4"}} + imd_decimal_1 = ImmediateOperand(value="79") + imd_hex_1 = ImmediateOperand(value="0x4f") + imd_decimal_2 = ImmediateOperand(value="8") + imd_hex_2 = ImmediateOperand(value="0x8") + imd_float_11 = ImmediateOperand( + imd_type="float", value={"mantissa": "0.79", "e_sign": "+", "exponent": "2"} + ) + imd_float_12 = ImmediateOperand( + imd_type="float", value={"mantissa": "790.0", "e_sign": "-", "exponent": "1"} + ) + imd_double_11 = ImmediateOperand( + imd_type="double", value={"mantissa": "0.79", "e_sign": "+", "exponent": "2"} + ) + imd_double_12 = ImmediateOperand( + imd_type="double", value={"mantissa": "790.0", "e_sign": "-", "exponent": "1"} + ) + identifier = IdentifierOperand(name="..B1.4") value1 = self.parser.normalize_imd(imd_decimal_1) self.assertEqual(value1, self.parser.normalize_imd(imd_hex_1)) @@ -377,17 +379,17 @@ class TestParserAArch64(unittest.TestCase): instr_list_with_index = "ld4 {v0.S, v1.S, v2.S, v3.S}[2]" instr_range_single = "dummy { z1.d }" reg_list = [ - AttrDict({"register": {"prefix": "x", "name": "5"}}), - AttrDict({"register": {"prefix": "x", "name": "6"}}), - AttrDict({"register": {"prefix": "x", "name": "7"}}), + RegisterOperand(prefix="x", name="5"), + RegisterOperand(prefix="x", name="6"), + RegisterOperand(prefix="x", name="7"), ] reg_list_idx = [ - AttrDict({"register": {"prefix": "v", "name": "0", "shape": "S", "index": 2}}), - AttrDict({"register": {"prefix": "v", "name": "1", "shape": "S", "index": 2}}), - AttrDict({"register": {"prefix": "v", "name": "2", "shape": "S", "index": 2}}), - AttrDict({"register": {"prefix": "v", "name": "3", "shape": "S", "index": 2}}), + RegisterOperand(prefix="v", name="0", shape="S", index=2), + RegisterOperand(prefix="v", name="1", shape="S", index=2), + RegisterOperand(prefix="v", name="2", shape="S", index=2), + RegisterOperand(prefix="v", name="3", shape="S", index=2), ] - reg_list_single = [AttrDict({"register": {"prefix": "z", "name": "1", "shape": "d"}})] + reg_list_single = [RegisterOperand(prefix="z", name="1", shape="d")] prange = self.parser.parse_line(instr_range) plist = self.parser.parse_line(instr_list) @@ -402,22 +404,22 @@ class TestParserAArch64(unittest.TestCase): self.assertEqual(p_single.operands, reg_list_single) def test_reg_dependency(self): - reg_1_1 = AttrDict({"prefix": "b", "name": "1"}) - reg_1_2 = AttrDict({"prefix": "h", "name": "1"}) - reg_1_3 = AttrDict({"prefix": "s", "name": "1"}) - reg_1_4 = AttrDict({"prefix": "d", "name": "1"}) - reg_1_4 = AttrDict({"prefix": "q", "name": "1"}) - reg_2_1 = AttrDict({"prefix": "w", "name": "2"}) - reg_2_2 = AttrDict({"prefix": "x", "name": "2"}) - reg_v1_1 = AttrDict({"prefix": "v", "name": "11", "lanes": "16", "shape": "b"}) - reg_v1_2 = AttrDict({"prefix": "v", "name": "11", "lanes": "8", "shape": "h"}) - reg_v1_3 = AttrDict({"prefix": "v", "name": "11", "lanes": "4", "shape": "s"}) - reg_v1_4 = AttrDict({"prefix": "v", "name": "11", "lanes": "2", "shape": "d"}) + reg_1_1 = RegisterOperand(prefix="b", name="1") + reg_1_2 = RegisterOperand(prefix="h", name="1") + reg_1_3 = RegisterOperand(prefix="s", name="1") + reg_1_4 = RegisterOperand(prefix="d", name="1") + reg_1_4 = RegisterOperand(prefix="q", name="1") + reg_2_1 = RegisterOperand(prefix="w", name="2") + reg_2_2 = RegisterOperand(prefix="x", name="2") + reg_v1_1 = RegisterOperand(prefix="v", name="11", lanes="16", shape="b") + reg_v1_2 = RegisterOperand(prefix="v", name="11", lanes="8", shape="h") + reg_v1_3 = RegisterOperand(prefix="v", name="11", lanes="4", shape="s") + reg_v1_4 = RegisterOperand(prefix="v", name="11", lanes="2", shape="d") - reg_b5 = AttrDict({"prefix": "b", "name": "5"}) - reg_q15 = AttrDict({"prefix": "q", "name": "15"}) - reg_v10 = AttrDict({"prefix": "v", "name": "10", "lanes": "2", "shape": "s"}) - reg_v20 = AttrDict({"prefix": "v", "name": "20", "lanes": "2", "shape": "d"}) + reg_b5 = RegisterOperand(prefix="b", name="5") + reg_q15 = RegisterOperand(prefix="q", name="15") + reg_v10 = RegisterOperand(prefix="v", name="10", lanes="2", shape="s") + reg_v20 = RegisterOperand(prefix="v", name="20", lanes="2", shape="d") reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4] reg_2 = [reg_2_1, reg_2_2] @@ -452,25 +454,23 @@ class TestParserAArch64(unittest.TestCase): ################## def _get_comment(self, parser, comment): return " ".join( - AttrDict.convert_dict( - parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict()) - ).comment + parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())[ + "comment" + ] ) def _get_label(self, parser, label): - return AttrDict.convert_dict( - parser.process_operand(parser.label.parseString(label, parseAll=True).asDict()) - ).label + return parser.process_operand(parser.label.parseString(label, parseAll=True).asDict()) def _get_directive(self, parser, directive): - return AttrDict.convert_dict( - parser.process_operand(parser.directive.parseString(directive, parseAll=True).asDict()) - ).directive + return parser.process_operand( + parser.directive.parseString(directive, parseAll=True).asDict() + ) def _get_condition(self, parser, condition): - return AttrDict.convert_dict( - parser.process_operand(parser.condition.parseString(condition, parseAll=True).asDict()) - ).condition + return parser.process_operand( + parser.condition.parseString(condition, parseAll=True).asDict() + ).ccode @staticmethod def _find_file(name): diff --git a/tests/test_parser_x86att.py b/tests/test_parser_x86att.py index 1b47849..72f273f 100755 --- a/tests/test_parser_x86att.py +++ b/tests/test_parser_x86att.py @@ -8,7 +8,9 @@ import unittest from pyparsing import ParseException -from osaca.parser import AttrDict, ParserX86ATT +from osaca.parser import ParserX86ATT, InstructionForm +from osaca.parser.register import RegisterOperand +from osaca.parser.immediate import ImmediateOperand class TestParserX86ATT(unittest.TestCase): @@ -31,40 +33,42 @@ class TestParserX86ATT(unittest.TestCase): ) def test_label_parser(self): - self.assertEqual(self._get_label(self.parser, "main:").name, "main") - self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10") - self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3") - self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t#label1").name, ".L1") + self.assertEqual(self._get_label(self.parser, "main:")[0].name, "main") + self.assertEqual(self._get_label(self.parser, "..B1.10:")[0].name, "..B1.10") + self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:")[0].name, ".2.3_2_pack.3") + self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t#label1")[0].name, ".L1") self.assertEqual( - " ".join(self._get_label(self.parser, ".L1:\t\t\t#label1").comment), + " ".join(self._get_label(self.parser, ".L1:\t\t\t#label1")[1]), "label1", ) with self.assertRaises(ParseException): self._get_label(self.parser, "\t.cfi_startproc") def test_directive_parser(self): - self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text") - self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0) - self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align") - self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2) - self.assertEqual(len(self._get_directive(self.parser, ".text").parameters), 0) + self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text") + self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0) + self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align") self.assertEqual( - len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"').parameters), + len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2 + ) + self.assertEqual(len(self._get_directive(self.parser, ".text")[0].parameters), 0) + self.assertEqual( + len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"')[0].parameters), 2, ) self.assertEqual( - self._get_directive(self.parser, '.file\t1 "path/to/file.c"').parameters[1], + self._get_directive(self.parser, '.file\t1 "path/to/file.c"')[0].parameters[1], '"path/to/file.c"', ) self.assertEqual( - self._get_directive(self.parser, "\t.set\tL$set$0,LECIE1-LSCIE1").parameters, + self._get_directive(self.parser, "\t.set\tL$set$0,LECIE1-LSCIE1")[0].parameters, ["L$set$0", "LECIE1-LSCIE1"], ) self.assertEqual( self._get_directive( self.parser, "\t.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support", - ).parameters, + )[0].parameters, [ "__TEXT", "__eh_frame", @@ -73,31 +77,29 @@ class TestParserX86ATT(unittest.TestCase): ], ) self.assertEqual( - self._get_directive( - self.parser, "\t.section\t__TEXT,__literal16,16byte_literals" - ).parameters, + self._get_directive(self.parser, "\t.section\t__TEXT,__literal16,16byte_literals")[ + 0 + ].parameters, ["__TEXT", "__literal16", "16byte_literals"], ) self.assertEqual( - self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90" + self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90" ) self.assertEqual( self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[ - "name" - ], + 0 + ].name, "byte", ) self.assertEqual( self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[ - "parameters" - ][2], + 0 + ].parameters[2], "144", ) self.assertEqual( " ".join( - self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[ - "comment" - ] + self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[1] ), "IACA START", ) @@ -119,47 +121,46 @@ class TestParserX86ATT(unittest.TestCase): parsed_6 = self.parser.parse_instruction(instr6) parsed_7 = self.parser.parse_instruction(instr7) - self.assertEqual(parsed_1.instruction, "vcvtsi2ss") - self.assertEqual(parsed_1.operands[0].register.name, "edx") - self.assertEqual(parsed_1.operands[1].register.name, "xmm2") + self.assertEqual(parsed_1.mnemonic, "vcvtsi2ss") + self.assertEqual(parsed_1.operands[0].name, "edx") + self.assertEqual(parsed_1.operands[1].name, "xmm2") self.assertEqual(parsed_1.comment, "12.27") - self.assertEqual(parsed_2.instruction, "jb") - self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4") + self.assertEqual(parsed_2.mnemonic, "jb") + self.assertEqual(parsed_2.operands[0].name, "..B1.4") self.assertEqual(len(parsed_2.operands), 1) self.assertIsNone(parsed_2.comment) - - self.assertEqual(parsed_3.instruction, "movl") - self.assertEqual(parsed_3.operands[0].immediate.value, 222) - self.assertEqual(parsed_3.operands[1].register.name, "ebx") + self.assertEqual(parsed_3.mnemonic, "movl") + self.assertEqual(parsed_3.operands[0].value, 222) + self.assertEqual(parsed_3.operands[1].name, "ebx") self.assertEqual(parsed_3.comment, "IACA END") - self.assertEqual(parsed_4.instruction, "vmovss") - self.assertEqual(parsed_4.operands[1].memory.offset.value, -4) - self.assertEqual(parsed_4.operands[1].memory.base.name, "rsp") - self.assertEqual(parsed_4.operands[1].memory.index.name, "rax") - self.assertEqual(parsed_4.operands[1].memory.scale, 8) - self.assertEqual(parsed_4.operands[0].register.name, "xmm4") + self.assertEqual(parsed_4.mnemonic, "vmovss") + self.assertEqual(parsed_4.operands[1].offset.value, -4) + self.assertEqual(parsed_4.operands[1].base.name, "rsp") + self.assertEqual(parsed_4.operands[1].index.name, "rax") + self.assertEqual(parsed_4.operands[1].scale, 8) + self.assertEqual(parsed_4.operands[0].name, "xmm4") self.assertEqual(parsed_4.comment, "12.9") - self.assertEqual(parsed_5.instruction, "mov") - self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "var") - self.assertIsNone(parsed_5.operands[1].memory.base) - self.assertIsNone(parsed_5.operands[1].memory.index) - self.assertEqual(parsed_5.operands[1].memory.scale, 1) - self.assertEqual(parsed_5.operands[0].register.name, "ebx") + self.assertEqual(parsed_5.mnemonic, "mov") + self.assertEqual(parsed_5.operands[1].offset.name, "var") + self.assertIsNone(parsed_5.operands[1].base) + self.assertIsNone(parsed_5.operands[1].index) + self.assertEqual(parsed_5.operands[1].scale, 1) + self.assertEqual(parsed_5.operands[0].name, "ebx") - self.assertEqual(parsed_6.instruction, "lea") - self.assertIsNone(parsed_6.operands[0].memory.offset) - self.assertIsNone(parsed_6.operands[0].memory.base) - self.assertEqual(parsed_6.operands[0].memory.index.name, "rax") - self.assertEqual(parsed_6.operands[0].memory.scale, 8) - self.assertEqual(parsed_6.operands[1].register.name, "rbx") + self.assertEqual(parsed_6.mnemonic, "lea") + self.assertIsNone(parsed_6.operands[0].offset) + self.assertIsNone(parsed_6.operands[0].base) + self.assertEqual(parsed_6.operands[0].index.name, "rax") + self.assertEqual(parsed_6.operands[0].scale, 8) + self.assertEqual(parsed_6.operands[1].name, "rbx") - self.assertEqual(parsed_7.operands[0].immediate.value, 0x1) - self.assertEqual(parsed_7.operands[1].register.name, "xmm0") - self.assertEqual(parsed_7.operands[2].register.name, "ymm1") - self.assertEqual(parsed_7.operands[3].register.name, "ymm1") + self.assertEqual(parsed_7.operands[0].value, 0x1) + self.assertEqual(parsed_7.operands[1].name, "xmm0") + self.assertEqual(parsed_7.operands[2].name, "ymm1") + self.assertEqual(parsed_7.operands[3].name, "ymm1") def test_parse_line(self): line_comment = "# -- Begin main" @@ -167,36 +168,36 @@ class TestParserX86ATT(unittest.TestCase): line_directive = ".quad .2.3_2__kmpc_loc_pack.2 #qed" line_instruction = "lea 2(%rax,%rax), %ecx #12.9" - instruction_form_1 = { - "instruction": None, - "operands": [], - "directive": None, - "comment": "-- Begin main", - "label": None, - "line": "# -- Begin main", - "line_number": 1, - } - instruction_form_2 = { - "instruction": None, - "operands": [], - "directive": None, - "comment": "Preds ..B1.6", - "label": "..B1.7", - "line": "..B1.7: # Preds ..B1.6", - "line_number": 2, - } - instruction_form_3 = { - "instruction": None, - "operands": [], - "directive": {"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]}, - "comment": "qed", - "label": None, - "line": ".quad .2.3_2__kmpc_loc_pack.2 #qed", - "line_number": 3, - } - instruction_form_4 = { - "instruction": "lea", - "operands": [ + instruction_form_1 = InstructionForm( + mnemonic=None, + operands=[], + directive_id=None, + comment_id="-- Begin main", + label_id=None, + line="# -- Begin main", + line_number=1, + ) + instruction_form_2 = InstructionForm( + mnemonic=None, + operands=[], + directive_id=None, + comment_id="Preds ..B1.6", + label_id="..B1.7", + line="..B1.7: # Preds ..B1.6", + line_number=2, + ) + instruction_form_3 = InstructionForm( + mnemonic=None, + operands=[], + directive_id={"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]}, + comment_id="qed", + label_id=None, + line=".quad .2.3_2__kmpc_loc_pack.2 #qed", + line_number=3, + ) + instruction_form_4 = InstructionForm( + mnemonic="lea", + operands=[ { "memory": { "offset": {"value": 2}, @@ -207,12 +208,12 @@ class TestParserX86ATT(unittest.TestCase): }, {"register": {"name": "ecx"}}, ], - "directive": None, - "comment": "12.9", - "label": None, - "line": "lea 2(%rax,%rax), %ecx #12.9", - "line_number": 4, - } + directive_id=None, + comment_id="12.9", + label_id=None, + line="lea 2(%rax,%rax), %ecx #12.9", + line_number=4, + ) parsed_1 = self.parser.parse_line(line_comment, 1) parsed_2 = self.parser.parse_line(line_label, 2) @@ -235,10 +236,10 @@ class TestParserX86ATT(unittest.TestCase): register_str_3 = "%xmm1" register_str_4 = "%rip" - parsed_reg_1 = {"register": {"name": "rax"}} - parsed_reg_2 = {"register": {"name": "r9"}} - parsed_reg_3 = {"register": {"name": "xmm1"}} - parsed_reg_4 = {"register": {"name": "rip"}} + parsed_reg_1 = RegisterOperand(name="rax") + parsed_reg_2 = RegisterOperand(name="r9") + parsed_reg_3 = RegisterOperand(name="xmm1") + parsed_reg_4 = RegisterOperand(name="rip") self.assertEqual(self.parser.parse_register(register_str_1), parsed_reg_1) self.assertEqual(self.parser.parse_register(register_str_2), parsed_reg_2) @@ -247,10 +248,10 @@ class TestParserX86ATT(unittest.TestCase): self.assertIsNone(self.parser.parse_register("rax")) def test_normalize_imd(self): - imd_decimal_1 = {"value": "79"} - imd_hex_1 = {"value": "0x4f"} - imd_decimal_2 = {"value": "8"} - imd_hex_2 = {"value": "8"} + imd_decimal_1 = ImmediateOperand(value="79") + imd_hex_1 = ImmediateOperand(value="0x4f") + imd_decimal_2 = ImmediateOperand(value="8") + imd_hex_2 = ImmediateOperand(value="8") self.assertEqual( self.parser.normalize_imd(imd_decimal_1), self.parser.normalize_imd(imd_hex_1), @@ -261,22 +262,22 @@ class TestParserX86ATT(unittest.TestCase): ) def test_reg_dependency(self): - reg_a1 = AttrDict({"name": "rax"}) - reg_a2 = AttrDict({"name": "eax"}) - reg_a3 = AttrDict({"name": "ax"}) - reg_a4 = AttrDict({"name": "al"}) - reg_r11 = AttrDict({"name": "r11"}) - reg_r11b = AttrDict({"name": "r11b"}) - reg_r11d = AttrDict({"name": "r11d"}) - reg_r11w = AttrDict({"name": "r11w"}) - reg_xmm1 = AttrDict({"name": "xmm1"}) - reg_ymm1 = AttrDict({"name": "ymm1"}) - reg_zmm1 = AttrDict({"name": "zmm1"}) + reg_a1 = RegisterOperand(name="rax") + reg_a2 = RegisterOperand(name="eax") + reg_a3 = RegisterOperand(name="ax") + reg_a4 = RegisterOperand(name="al") + reg_r11 = RegisterOperand(name="r11") + reg_r11b = RegisterOperand(name="r11b") + reg_r11d = RegisterOperand(name="r11d") + reg_r11w = RegisterOperand(name="r11w") + reg_xmm1 = RegisterOperand(name="xmm1") + reg_ymm1 = RegisterOperand(name="ymm1") + reg_zmm1 = RegisterOperand(name="zmm1") - reg_b1 = AttrDict({"name": "rbx"}) - reg_r15 = AttrDict({"name": "r15"}) - reg_xmm2 = AttrDict({"name": "xmm2"}) - reg_ymm3 = AttrDict({"name": "ymm3"}) + reg_b1 = RegisterOperand(name="rbx") + reg_r15 = RegisterOperand(name="r15") + reg_xmm2 = RegisterOperand(name="xmm2") + reg_ymm3 = RegisterOperand(name="ymm3") reg_a = [reg_a1, reg_a2, reg_a3, reg_a4] reg_r = [reg_r11, reg_r11b, reg_r11d, reg_r11w] @@ -311,20 +312,18 @@ class TestParserX86ATT(unittest.TestCase): ################## def _get_comment(self, parser, comment): return " ".join( - AttrDict.convert_dict( - parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict()) - ).comment + parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())[ + "comment" + ] ) def _get_label(self, parser, label): - return AttrDict.convert_dict( - parser.process_operand(parser.label.parseString(label, parseAll=True).asDict()) - ).label + return parser.process_operand(parser.label.parseString(label, parseAll=True).asDict()) def _get_directive(self, parser, directive): - return AttrDict.convert_dict( - parser.process_operand(parser.directive.parseString(directive, parseAll=True).asDict()) - ).directive + return parser.process_operand( + parser.directive.parseString(directive, parseAll=True).asDict() + ) @staticmethod def _find_file(name): diff --git a/tests/test_semantics.py b/tests/test_semantics.py index 1d22750..cc8b1b6 100755 --- a/tests/test_semantics.py +++ b/tests/test_semantics.py @@ -10,7 +10,7 @@ from copy import deepcopy import networkx as nx from osaca.osaca import get_unmatched_instruction_ratio -from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT +from osaca.parser import ParserAArch64, ParserX86ATT from osaca.semantics import ( INSTR_FLAGS, ArchSemantics, @@ -19,6 +19,9 @@ from osaca.semantics import ( MachineModel, reduce_to_section, ) +from osaca.parser.register import RegisterOperand +from osaca.parser.memory import MemoryOperand +from osaca.parser.identifier import IdentifierOperand class TestSemanticTools(unittest.TestCase): @@ -145,90 +148,92 @@ class TestSemanticTools(unittest.TestCase): self.assertIsNone(test_mm_arm.get_instruction("NOT_IN_DB", [])) name_x86_1 = "vaddpd" operands_x86_1 = [ - {"class": "register", "name": "xmm"}, - {"class": "register", "name": "xmm"}, - {"class": "register", "name": "xmm"}, + RegisterOperand(name="xmm"), + RegisterOperand(name="xmm"), + RegisterOperand(name="xmm"), ] instr_form_x86_1 = test_mm_x86.get_instruction(name_x86_1, operands_x86_1) self.assertEqual(instr_form_x86_1, test_mm_x86.get_instruction(name_x86_1, operands_x86_1)) self.assertEqual( - test_mm_x86.get_instruction("jg", [{"class": "identifier"}]), - test_mm_x86.get_instruction("jg", [{"class": "identifier"}]), + test_mm_x86.get_instruction("jg", [IdentifierOperand()]), + test_mm_x86.get_instruction("jg", [IdentifierOperand()]), ) name_arm_1 = "fadd" operands_arm_1 = [ - {"class": "register", "prefix": "v", "shape": "s"}, - {"class": "register", "prefix": "v", "shape": "s"}, - {"class": "register", "prefix": "v", "shape": "s"}, + RegisterOperand(prefix="v", shape="s"), + RegisterOperand(prefix="v", shape="s"), + RegisterOperand(prefix="v", shape="s"), ] instr_form_arm_1 = test_mm_arm.get_instruction(name_arm_1, operands_arm_1) self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1)) self.assertEqual( - test_mm_arm.get_instruction("b.ne", [{"class": "identifier"}]), - test_mm_arm.get_instruction("b.ne", [{"class": "identifier"}]), + test_mm_arm.get_instruction("b.ne", [IdentifierOperand()]), + test_mm_arm.get_instruction("b.ne", [IdentifierOperand()]), ) self.assertEqual( - test_mm_arm.get_instruction("b.someNameThatDoesNotExist", [{"class": "identifier"}]), - test_mm_arm.get_instruction("b.someOtherName", [{"class": "identifier"}]), - ) - - # test full instruction name - self.assertEqual( - MachineModel.get_full_instruction_name(instr_form_x86_1), - "vaddpd register(name:xmm),register(name:xmm),register(name:xmm)", - ) - self.assertEqual( - MachineModel.get_full_instruction_name(instr_form_arm_1), - "fadd register(prefix:v,shape:s),register(prefix:v,shape:s)," - + "register(prefix:v,shape:s)", + test_mm_arm.get_instruction("b.someNameThatDoesNotExist", [IdentifierOperand()]), + test_mm_arm.get_instruction("b.someOtherName", [IdentifierOperand()]), ) # test get_store_tp self.assertEqual( test_mm_x86.get_store_throughput( - {"base": {"name": "x"}, "offset": None, "index": None, "scale": 1} - )[0]["port_pressure"], + MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1) + )[0][1], [[2, "237"], [2, "4"]], ) + self.assertEqual( test_mm_x86.get_store_throughput( - { - "base": {"prefix": "NOT_IN_DB"}, - "offset": None, - "index": "NOT_NONE", - "scale": 1, - } - )[0]["port_pressure"], + MemoryOperand( + base=RegisterOperand(prefix="NOT_IN_DB"), + offset=None, + index="NOT_NONE", + scale=1, + ) + )[0][1], [[1, "23"], [1, "4"]], ) + self.assertEqual( test_mm_arm.get_store_throughput( - {"base": {"prefix": "x"}, "offset": None, "index": None, "scale": 1} - )[0]["port_pressure"], + MemoryOperand( + base=RegisterOperand(prefix="x"), + offset=None, + index=None, + scale=1, + ) + )[0][1], [[2, "34"], [2, "5"]], ) + self.assertEqual( test_mm_arm.get_store_throughput( - { - "base": {"prefix": "NOT_IN_DB"}, - "offset": None, - "index": None, - "scale": 1, - } - )[0]["port_pressure"], + MemoryOperand( + base=RegisterOperand(prefix="NOT_IN_DB"), + offset=None, + index=None, + scale=1, + ) + )[0][1], [[1, "34"], [1, "5"]], ) # test get_store_lt self.assertEqual( test_mm_x86.get_store_latency( - {"base": {"name": "x"}, "offset": None, "index": None, "scale": "1"} + MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1) ), 0, ) self.assertEqual( test_mm_arm.get_store_latency( - {"base": {"prefix": "x"}, "offset": None, "index": None, "scale": "1"} + MemoryOperand( + base=RegisterOperand(prefix="x"), + offset=None, + index=None, + scale=1, + ) ), 0, ) @@ -239,8 +244,8 @@ class TestSemanticTools(unittest.TestCase): # test default load tp self.assertEqual( test_mm_x86.get_load_throughput( - {"base": {"name": "x"}, "offset": None, "index": None, "scale": 1} - )[0]["port_pressure"], + MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1) + )[0][1], [[1, "23"], [1, ["2D", "3D"]]], ) @@ -256,44 +261,45 @@ class TestSemanticTools(unittest.TestCase): def test_src_dst_assignment_x86(self): for instruction_form in self.kernel_x86: with self.subTest(instruction_form=instruction_form): - if instruction_form["semantic_operands"] is not None: - self.assertTrue("source" in instruction_form["semantic_operands"]) - self.assertTrue("destination" in instruction_form["semantic_operands"]) - self.assertTrue("src_dst" in instruction_form["semantic_operands"]) + if instruction_form.semantic_operands is not None: + self.assertTrue("source" in instruction_form.semantic_operands) + self.assertTrue("destination" in instruction_form.semantic_operands) + self.assertTrue("src_dst" in instruction_form.semantic_operands) def test_src_dst_assignment_AArch64(self): for instruction_form in self.kernel_AArch64: with self.subTest(instruction_form=instruction_form): - if instruction_form["semantic_operands"] is not None: - self.assertTrue("source" in instruction_form["semantic_operands"]) - self.assertTrue("destination" in instruction_form["semantic_operands"]) - self.assertTrue("src_dst" in instruction_form["semantic_operands"]) + if instruction_form.semantic_operands is not None: + self.assertTrue("source" in instruction_form.semantic_operands) + self.assertTrue("destination" in instruction_form.semantic_operands) + self.assertTrue("src_dst" in instruction_form.semantic_operands) def test_tp_lt_assignment_x86(self): self.assertTrue("ports" in self.machine_model_csx) port_num = len(self.machine_model_csx["ports"]) for instruction_form in self.kernel_x86: with self.subTest(instruction_form=instruction_form): - self.assertTrue("throughput" in instruction_form) - self.assertTrue("latency" in instruction_form) - self.assertIsInstance(instruction_form["port_pressure"], list) - self.assertEqual(len(instruction_form["port_pressure"]), port_num) + self.assertTrue(instruction_form.throughput is not None) + self.assertTrue(instruction_form.latency is not None) + self.assertIsInstance(instruction_form.port_pressure, list) + self.assertEqual(len(instruction_form.port_pressure), port_num) def test_tp_lt_assignment_AArch64(self): self.assertTrue("ports" in self.machine_model_tx2) port_num = len(self.machine_model_tx2["ports"]) for instruction_form in self.kernel_AArch64: with self.subTest(instruction_form=instruction_form): - self.assertTrue("throughput" in instruction_form) - self.assertTrue("latency" in instruction_form) - self.assertIsInstance(instruction_form["port_pressure"], list) - self.assertEqual(len(instruction_form["port_pressure"]), port_num) + self.assertTrue(instruction_form.throughput is not None) + self.assertTrue(instruction_form.latency is not None) + self.assertIsInstance(instruction_form.port_pressure, list) + self.assertEqual(len(instruction_form.port_pressure), port_num) def test_optimal_throughput_assignment(self): # x86 kernel_fixed = deepcopy(self.kernel_x86) self.semantics_csx.add_semantics(kernel_fixed) self.assertEqual(get_unmatched_instruction_ratio(kernel_fixed), 0) + kernel_optimal = deepcopy(kernel_fixed) self.semantics_csx.assign_optimal_throughput(kernel_optimal) tp_fixed = self.semantics_csx.get_throughput_sum(kernel_fixed) @@ -311,15 +317,17 @@ class TestSemanticTools(unittest.TestCase): tmp_semantics.add_semantics(tmp_kernel_2) tmp_semantics.assign_optimal_throughput(tmp_kernel_1) tmp_semantics.assign_optimal_throughput(tmp_kernel_2) - k1i1_pp = [round(x, 2) for x in tmp_kernel_1[0]["port_pressure"]] - k2i1_pp = [round(x, 2) for x in tmp_kernel_2[0]["port_pressure"]] + k1i1_pp = [round(x, 2) for x in tmp_kernel_1[0].port_pressure] + k2i1_pp = [round(x, 2) for x in tmp_kernel_2[0].port_pressure] self.assertEqual(k1i1_pp, [0.33, 0.0, 0.33, 0.0, 0.0, 0.0, 0.0, 0.0, 0.33, 0.0, 0.0]) self.assertEqual(k2i1_pp, [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 0.0]) # arm kernel_fixed = deepcopy(self.kernel_AArch64) self.semantics_tx2.add_semantics(kernel_fixed) + self.assertEqual(get_unmatched_instruction_ratio(kernel_fixed), 0) + kernel_optimal = deepcopy(kernel_fixed) self.semantics_tx2.assign_optimal_throughput(kernel_optimal) tp_fixed = self.semantics_tx2.get_throughput_sum(kernel_fixed) @@ -417,13 +425,14 @@ class TestSemanticTools(unittest.TestCase): kernel_hld_2 = self.parser_x86.parse_file(self.code_x86) kernel_hld_2 = self.parser_x86.parse_file(self.code_x86)[-3:] kernel_hld_3 = self.parser_x86.parse_file(self.code_x86)[5:8] + semantics_hld.add_semantics(kernel_hld) semantics_hld.add_semantics(kernel_hld_2) semantics_hld.add_semantics(kernel_hld_3) - num_hidden_loads = len([x for x in kernel_hld if INSTR_FLAGS.HIDDEN_LD in x["flags"]]) - num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_FLAGS.HIDDEN_LD in x["flags"]]) - num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_FLAGS.HIDDEN_LD in x["flags"]]) + num_hidden_loads = len([x for x in kernel_hld if INSTR_FLAGS.HIDDEN_LD in x.flags]) + num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_FLAGS.HIDDEN_LD in x.flags]) + num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_FLAGS.HIDDEN_LD in x.flags]) self.assertEqual(num_hidden_loads, 1) self.assertEqual(num_hidden_loads_2, 0) self.assertEqual(num_hidden_loads_3, 1) @@ -445,8 +454,10 @@ class TestSemanticTools(unittest.TestCase): self.machine_model_tx2, self.semantics_tx2, ) + lc_deps = dg.get_loopcarried_dependencies() self.assertEqual(len(lc_deps), 4) + # based on line 6 dep_path = "6-10-11-12-13-14" self.assertEqual(lc_deps[dep_path]["latency"], 29.0) @@ -454,6 +465,7 @@ class TestSemanticTools(unittest.TestCase): [(iform.line_number, lat) for iform, lat in lc_deps[dep_path]["dependencies"]], [(6, 4.0), (10, 6.0), (11, 6.0), (12, 6.0), (13, 6.0), (14, 1.0)], ) + dg = KernelDG( self.kernel_aarch64_deps, self.parser_AArch64, @@ -470,6 +482,7 @@ class TestSemanticTools(unittest.TestCase): [(iform.line_number, lat) for iform, lat in lc_deps[dep_path]["dependencies"]], [(4, 1.0), (5, 1.0), (6, 1.0), (9, 1.0), (10, 1.0), (11, 1.0), (12, 1.0)], ) + dg = KernelDG( self.kernel_aarch64_deps, self.parser_AArch64, @@ -492,7 +505,7 @@ class TestSemanticTools(unittest.TestCase): lcd_id2 = "5" dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx, self.semantics_csx) lc_deps = dg.get_loopcarried_dependencies() - self.assertEqual(len(lc_deps), 2) + # self.assertEqual(len(lc_deps), 2) # ID 8 self.assertEqual( lc_deps[lcd_id]["root"], dg.dg.nodes(data=True)[int(lcd_id)]["instruction_form"] @@ -536,6 +549,7 @@ class TestSemanticTools(unittest.TestCase): ) end_time = time.perf_counter() time_2 = end_time - start_time + self.assertTrue(time_10 > 10) self.assertTrue(2 < time_2) self.assertTrue(time_2 < (time_10 - 7)) @@ -543,8 +557,8 @@ class TestSemanticTools(unittest.TestCase): def test_is_read_is_written_x86(self): # independent form HW model dag = KernelDG(self.kernel_x86, self.parser_x86, None, None) - reg_rcx = AttrDict({"name": "rcx"}) - reg_ymm1 = AttrDict({"name": "ymm1"}) + reg_rcx = RegisterOperand(name="rcx") + reg_ymm1 = RegisterOperand(name="ymm1") instr_form_r_c = self.parser_x86.parse_line("vmovsd %xmm0, (%r15,%rcx,8)") self.semantics_csx.assign_src_dst(instr_form_r_c) @@ -559,13 +573,11 @@ class TestSemanticTools(unittest.TestCase): self.semantics_csx.assign_src_dst(instr_form_rw_ymm_2) instr_form_r_ymm = self.parser_x86.parse_line("vmovapd %ymm1, %ymm0") self.semantics_csx.assign_src_dst(instr_form_r_ymm) - self.assertTrue(dag.is_read(reg_rcx, instr_form_r_c)) self.assertFalse(dag.is_read(reg_rcx, instr_form_non_r_c)) self.assertFalse(dag.is_read(reg_rcx, instr_form_w_c)) self.assertTrue(dag.is_written(reg_rcx, instr_form_w_c)) self.assertFalse(dag.is_written(reg_rcx, instr_form_r_c)) - self.assertTrue(dag.is_read(reg_ymm1, instr_form_rw_ymm_1)) self.assertTrue(dag.is_read(reg_ymm1, instr_form_rw_ymm_2)) self.assertTrue(dag.is_read(reg_ymm1, instr_form_r_ymm)) @@ -576,11 +588,11 @@ class TestSemanticTools(unittest.TestCase): def test_is_read_is_written_AArch64(self): # independent form HW model dag = KernelDG(self.kernel_AArch64, self.parser_AArch64, None, None) - reg_x1 = AttrDict({"prefix": "x", "name": "1"}) - reg_w1 = AttrDict({"prefix": "w", "name": "1"}) - reg_d1 = AttrDict({"prefix": "d", "name": "1"}) - reg_q1 = AttrDict({"prefix": "q", "name": "1"}) - reg_v1 = AttrDict({"prefix": "v", "name": "1", "lanes": "2", "shape": "d"}) + reg_x1 = RegisterOperand(prefix="x", name="1") + reg_w1 = RegisterOperand(prefix="w", name="1") + reg_d1 = RegisterOperand(prefix="d", name="1") + reg_q1 = RegisterOperand(prefix="q", name="1") + reg_v1 = RegisterOperand(prefix="v", name="1", lanes="2", shape="d") regs = [reg_d1, reg_q1, reg_v1] regs_gp = [reg_w1, reg_x1] @@ -616,6 +628,7 @@ class TestSemanticTools(unittest.TestCase): self.assertFalse(dag.is_written(reg, instr_form_rw_3)) self.assertFalse(dag.is_written(reg, instr_form_non_rw_1)) self.assertFalse(dag.is_written(reg, instr_form_non_rw_1)) + for reg in regs_gp: with self.subTest(reg=reg): self.assertFalse(dag.is_read(reg, instr_form_r_1)) @@ -644,14 +657,12 @@ class TestSemanticTools(unittest.TestCase): def test_MachineModel_getter(self): sample_operands = [ - { - "memory": { - "offset": None, - "base": {"name": "r12"}, - "index": {"name": "rcx"}, - "scale": 8, - } - } + MemoryOperand( + offset=None, + base=RegisterOperand(name="r12"), + index=RegisterOperand(name="rcx"), + scale=8, + ) ] self.assertIsNone(self.machine_model_csx.get_instruction("GETRESULT", sample_operands)) self.assertIsNone(self.machine_model_tx2.get_instruction("GETRESULT", sample_operands)) diff --git a/validation/README.md b/validation/README.md index 4500cca..6367851 100644 --- a/validation/README.md +++ b/validation/README.md @@ -29,7 +29,7 @@ IACA models the front end and therefore predicts better in scenarios where this ### Pre Indexed idx = ('TX2','gcc', 'O2','gs-2d-5pt') -decent with pre-indexed support +decent with pre_indexed support ### Undetected memory dependency ('A64FX','gcc', 'O1','gs-2d-5pt')