From ea59056f948e9a67cc9045fd72787504aabdd2b4 Mon Sep 17 00:00:00 2001
From: pleroy <pascal.h.leroy@gmail.com>
Date: Mon, 30 Dec 2024 19:55:20 +0100
Subject: [PATCH 1/3] Define comisd sources.

---
 osaca/data/isa/x86.yml | 75 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 74 insertions(+), 1 deletion(-)

diff --git a/osaca/data/isa/x86.yml b/osaca/data/isa/x86.yml
index bc1533b..31df792 100644
--- a/osaca/data/isa/x86.yml
+++ b/osaca/data/isa/x86.yml
@@ -2621,6 +2621,79 @@ instruction_forms:
           name: "ZF"
           source: true
           destination: true
+    - name: comisd
+      operands:
+        - class: "register"
+          name: "xmm"
+          source: true
+          destination: false
+        - class: "register"
+          name: "xmm"
+          source: true
+          destination: false
+      hidden_operands:
+        - class: "flag"
+          name: "CF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "OF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "SF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "ZF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "AF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "PF"
+          source: false
+          destination: true
+    - name: comisd
+      operands:
+        - class: "register"
+          name: "xmm"
+          source: true
+          destination: false
+        - class: "memory"
+          base: "*"
+          offset: "*"
+          index: "*"
+          scale: "*"
+          source: true
+          destination: false
+      hidden_operands:
+        - class: "flag"
+          name: "CF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "OF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "SF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "ZF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "AF"
+          source: false
+          destination: true
+        - class: "flag"
+          name: "PF"
+          source: false
+          destination: true
     - name: dec
       operands:
         - class: "register"
@@ -3613,7 +3686,7 @@ instruction_forms:
         - class: "register"
           name: "gpr"
           source: true
-          destination: true 
+          destination: true
     - name: sbb
       operands:
         - class: "register"

From d2b8b7771f30a04690dfdfcebab969d1f2605a6a Mon Sep 17 00:00:00 2001
From: Robin Leroy <egg.robin.leroy@gmail.com>
Date: Mon, 30 Dec 2024 22:50:03 +0100
Subject: [PATCH 2/3] ucomisd is like comisd

---
 osaca/data/isa/x86.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/osaca/data/isa/x86.yml b/osaca/data/isa/x86.yml
index 31df792..02ffd16 100644
--- a/osaca/data/isa/x86.yml
+++ b/osaca/data/isa/x86.yml
@@ -2621,7 +2621,7 @@ instruction_forms:
           name: "ZF"
           source: true
           destination: true
-    - name: comisd
+    - name: ["comisd", "ucomisd"]
       operands:
         - class: "register"
           name: "xmm"
@@ -2656,7 +2656,7 @@ instruction_forms:
           name: "PF"
           source: false
           destination: true
-    - name: comisd
+    - name: ["comisd", "ucomisd"]
       operands:
         - class: "register"
           name: "xmm"

From 939089030b624eeb228fd3f5481229d3b40f7176 Mon Sep 17 00:00:00 2001
From: pleroy <pascal.h.leroy@gmail.com>
Date: Sun, 29 Dec 2024 18:11:15 +0100
Subject: [PATCH 3/3] Fix the x86 ISA description to indicate that the register
 of SAR and SAL is read/write.

---
 osaca/data/isa/x86.yml  | 2 +-
 tests/test_semantics.py | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/osaca/data/isa/x86.yml b/osaca/data/isa/x86.yml
index 02ffd16..57bb5d5 100644
--- a/osaca/data/isa/x86.yml
+++ b/osaca/data/isa/x86.yml
@@ -4415,7 +4415,7 @@ instruction_forms:
           name: "xmm"
           source: true
           destination: true
-    - name: [shl, shr, shlq, shrq]
+    - name: [sal, sar, salq, sarq, shl, shr, shlq, shrq]
       operands:
         - class: "immediate"
           imd: "int"
diff --git a/tests/test_semantics.py b/tests/test_semantics.py
index 0748bfe..4f001a0 100755
--- a/tests/test_semantics.py
+++ b/tests/test_semantics.py
@@ -849,6 +849,9 @@ class TestSemanticTools(unittest.TestCase):
         instr_form_r_ymm = self.parser_x86_intel.parse_line("vmovapd ymm0, ymm1")
         self.semantics_csx_intel.normalize_instruction_form(instr_form_r_ymm)
         self.semantics_csx_intel.assign_src_dst(instr_form_r_ymm)
+        instr_form_rw_sar = self.parser_x86_intel.parse_line("sar rcx, 43")
+        self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_sar)
+        self.semantics_csx_intel.assign_src_dst(instr_form_rw_sar)
         self.assertTrue(dag.is_read(reg_rcx, instr_form_r_c))
         self.assertFalse(dag.is_read(reg_rcx, instr_form_non_r_c))
         self.assertFalse(dag.is_read(reg_rcx, instr_form_w_c))
@@ -860,6 +863,8 @@ class TestSemanticTools(unittest.TestCase):
         self.assertTrue(dag.is_written(reg_ymm1, instr_form_rw_ymm_1))
         self.assertTrue(dag.is_written(reg_ymm1, instr_form_rw_ymm_2))
         self.assertFalse(dag.is_written(reg_ymm1, instr_form_r_ymm))
+        self.assertTrue(dag.is_read(reg_rcx, instr_form_rw_sar))
+        self.assertTrue(dag.is_written(reg_rcx, instr_form_rw_sar))
 
     def test_is_read_is_written_AArch64(self):
         # independent form HW model