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Fixed issue with throughput assignment

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This commit is contained in:
stefandesouza
2023-10-30 19:32:05 +01:00
parent ebb973493b
commit 26d65750a6
5 changed files with 383 additions and 393 deletions
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1
osaca/semantics/arch_semantics.py
View File

@@ -191,7 +191,6 @@ class ArchSemantics(ISASemantics):
instruction_data = self._machine_model.get_instruction(
instruction_form.instruction, instruction_form.operands
)
if (
not instruction_data
and self._isa == "x86"

12
osaca/semantics/hw_model.py
View File

@@ -205,6 +205,8 @@ class MachineModel(object):
scale_id=o["scale"],
source=o["source"] if "source" in o else False,
destination=o["destination"] if "destination" in o else False,
pre_indexed=o["pre_indexed"] if "pre_indexed" in o else False,
post_indexed=o["post_indexed"] if "post_indexed" in o else False,
)
)
elif o["class"] == "immediate":
@@ -247,6 +249,7 @@ class MachineModel(object):
# For use with dict instead of list as DB
if name is None:
return None
name_matched_iforms = self._data["instruction_forms_dict"].get(name.upper(), [])
try:
return next(
@@ -650,9 +653,7 @@ class MachineModel(object):
def _check_operands(self, i_operand, operand):
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
# check for wildcard
if (isinstance(operand, Operand) and operand.name == self.WILDCARD) or (
not isinstance(operand, Operand) and self.WILDCARD in operand
):
if isinstance(operand, dict) and self.WILDCARD in operand:
if isinstance(i_operand, RegisterOperand):
return True
else:
@@ -877,12 +878,11 @@ class MachineModel(object):
or (mem.scale != 1 and i_mem.scale != 1)
)
# check pre-indexing
and (i_mem.pre_indexed == self.WILDCARD or (mem.pre_indexed) == (i_mem.pre_indexed))
# and (i_mem.pre_indexed == self.WILDCARD or (mem.pre_indexed == i_mem.pre_indexed))
# check post-indexing
and (i_mem.post_indexed == self.WILDCARD or (mem.post_indexed) == (i_mem.post_indexed))
# and (i_mem.post_indexed == self.WILDCARD or (mem.post_indexed == i_mem.post_indexed))
):
return True
return False
def _is_x86_mem_type(self, i_mem, mem):

1
osaca/semantics/isa_semantics.py
View File

@@ -209,6 +209,7 @@ class ISASemantics(object):
"ISA information for pre-indexed instruction {!r} has operation set."
"This is currently not supprted.".format(instruction_form.line)
)
base_name = o.base.prefix if o.base.prefix != None else "" + o.base.name
reg_operand_names = {base_name: "op1"}
operand_state = {"op1": {"name": base_name, "value": o.offset["value"]}}

2
osaca/semantics/kernel_dg.py
View File

@@ -386,7 +386,7 @@ class KernelDG(nx.DiGraph):
if isinstance(src, MemoryOperand):
if src.base is not None:
is_read = self.parser.is_reg_dependend_of(register, src.base) or is_read
if src.index is not None:
if src.index is not None and isinstance(src.index, RegisterOperand):
is_read = self.parser.is_reg_dependend_of(register, src.index) or is_read
# Check also if read in destination memory address
for dst in chain(