diff --git a/README.rst b/README.rst index 3d54f10..62e6cd1 100644 --- a/README.rst +++ b/README.rst @@ -95,7 +95,7 @@ The usage of OSACA can be listed as: --arch ARCH needs to be replaced with the target architecture abbreviation. Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX`` and ``ICL`` for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2`` for AMD Zen architectures. - Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse and ``A64FX`` for Fujitsu's HPC ARM architecture are available. + Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72 and ``A64FX`` for Fujitsu's HPC ARM architecture are available. If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64. --fixed Run the throughput analysis with fixed port utilization for all suitable ports per instruction. diff --git a/osaca/data/a72.yml b/osaca/data/a72.yml new file mode 100644 index 0000000..e0df92b --- /dev/null +++ b/osaca/data/a72.yml @@ -0,0 +1,4179 @@ +osaca_version: 0.3.11 +micro_architecture: Cortex A-72 +arch_code: a72 +isa: aarch64 +hidden_loads: false +load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0} +load_throughput: [] +load_throughput_default: [[1, '1']] +store_throughput: [] +store_throughput_default: [[2, '3']] +ports: ['0', '1', '2', '3', '4', '5', '6', '7'] +port_model_scheme: | + +-------------------------------------------------------------------------------------+ + | scheduler | + +-------------------------------------------------------------------------------------+ + 0 |I 1 |L 2 |M 3 |S 4 |F1 5 |I 6 |F0 7 |B + \/ \/ \/ \/ \/ \/ \/ \/ + +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+ + |INT ALU| | LOAD | | MUL | | STORE | | ASIMD | |INT ALU| | ASIMD | | Branch| + +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+ + +-------+ +-------+ +-----------+ +-------+ +---------+ + | AGU | | DIV | | FP ALU | | AGU | |ASIMD MUL| + +-------+ +-------+ +-----------+ +-------+ +---------+ + +-------+ +-----------+ +---------+ + | SHIFT | | FP MUL | | FP ALU | + +-------+ +-----------+ +---------+ + +-------+ +-----------+ +---------+ + | CRC | | FP DIV | | FP MUL | + +-------+ +-----------+ +---------+ + +-------+ +-----------+ +---------+ + | USAD | | FP SQRT | | FP DIV | + +-------+ +-----------+ +---------+ + +-----------+ +---------+ + |ASIMD SHIFT| | FP CONV | + +-----------+ +---------+ + +---------+ + | CRYPTO | + +---------+ +instruction_forms: +# Branch +- name: B + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: BNE + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: B.NE + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: BR + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: RET + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: BL + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '05'], [1, '7']] + throughput: 1.0 +- name: BLR + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05'], [1, '7']] + throughput: 1.0 + +# Load GPR +- name: LDR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Load FP d +- name: LDR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 + +# Load FP q +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 6.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 6.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 +- name: LDR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 6.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 + +# Store GPR +- name: STR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3']] + throughput: 1.0 +- name: STR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: STR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Store FP d +- name: STR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: STR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: STR + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Store FP q +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3']] + throughput: 2.0 +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: true + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [2, '05']] + throughput: 2.0 +- name: STR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[2, '3'], [2, '05']] + throughput: 2.0 + +# Load unscaled GPR +- name: LDUR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 + +# Load unscaled FP q +- name: LDUR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 + +# Store unscaled GPR +- name: STUR + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 1.0 + port_pressure: [[1, '3']] + throughput: 1.0 + +# Store unscaled FP q +- name: STUR + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 2.0 + port_pressure: [[2, '3']] + throughput: 2.0 + +# Load pair GPR +- name: LDP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: LDP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: LDP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 + +# Load pair FP q +- name: LDP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 6.0 + port_pressure: [[2, '1']] + throughput: 2.0 +- name: LDP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 6.0 + port_pressure: [[2, '1'], [1, '05']] + throughput: 2.0 +- name: LDP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 6.0 + port_pressure: [[2, '1'], [1, '05']] + throughput: 2.0 + +# Store pair GPR +- name: STP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 2.0 + port_pressure: [[2, '3']] + throughput: 2.0 +- name: STP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: STP + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 + +# Store pair FP q +- name: STP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 +- name: STP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 +- name: STP + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 + +# Fast-forward (measures 4 cycles, but can be 3) +# Lower bound is used in order to ensure no over-estimates are possible. +# Ports do not match documentation, but "fixing" requires also "fixing" almost +# the entire rest of the model. +- name: FADD + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: FADD + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: FADD + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: FADD + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: FSUB + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: FSUB + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: FSUB + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: FSUB + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + +# Automatically generated instructions +- name: abs + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: abs + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: add + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: add + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: add + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: add + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: addp + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: addv + operands: + - class: register + prefix: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: and + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: bfi + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + latency: 2.0 + port_pressure: [[1, '2']] + throughput: 1.0 + uops: ~ +- name: bic + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: bic + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: bics + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: bif + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: bit + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: bsl + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: clz + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: cmeq + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmeq + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmeq + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmeq + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmge + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmge + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmge + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmgt + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: cmgt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmgt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmgt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmgt + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmhi + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmhi + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmhi + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmhs + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: cmn + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: cmn + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.5 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: cmp + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.5 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: cmp + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: dup + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: eor + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: extr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '2']] + throughput: 0.5 + uops: ~ +- name: fabd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fabd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fabd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fabd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 4.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fabs + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fabs + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fabs + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fabs + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmeq + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmeq + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmeq + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmge + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmge + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmgt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmgt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmgt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmgt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmle + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmlt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmlt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fcmp + operands: + - class: register + prefix: s + - class: immediate + imd: float + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: fcmp + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: fcmp + operands: + - class: register + prefix: d + - class: immediate + imd: double + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: fcmp + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: fcmpe + operands: + - class: register + prefix: s + - class: immediate + imd: float + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: fcmpe + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: fcmpe + operands: + - class: register + prefix: d + - class: immediate + imd: double + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: fcmpe + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: fcvt + operands: + - class: register + prefix: s + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvt + operands: + - class: register + prefix: d + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtas + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: fcvtl2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtms + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: fcvtms + operands: + - class: register + prefix: x + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtms + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtmu + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtn2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtps + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtpu + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtzs + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: fcvtzs + operands: + - class: register + prefix: x + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtzs + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtzu + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: fcvtzu + operands: + - class: register + prefix: x + - class: register + prefix: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fcvtzu + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 6.0 + port_pressure: [[3, '0']] + throughput: 2.0 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 6.0 + port_pressure: [[4, '2']] + throughput: 4.0 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 8.0 + port_pressure: [[8, '4']] + throughput: 8.0 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 8.0 + port_pressure: [[8, '4']] + throughput: 8.0 + uops: ~ +- name: fmadd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fmla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fmls + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fmls + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fmov + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 0.5 + uops: ~ +- name: fmov + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 0.5 + uops: ~ +- name: fmsub + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmsub + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmul + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fmul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 4.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: fneg + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fneg + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: fneg + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fneg + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: fnmadd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fnmadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fnmsub + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fnmsub + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fnmul + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: fnmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: ~ +- name: frinta + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintm + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintm + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintp + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintp + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintp + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintx + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintz + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintz + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: frintz + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 9.0 + port_pressure: [[3, '4']] + throughput: 3.0 + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 9.0 + port_pressure: [[5, '4']] + throughput: 7.0 + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 14.0 + port_pressure: [[10, '4']] + throughput: 14.0 + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 14.0 + port_pressure: [[11, '4']] + throughput: 14.0 + uops: ~ +- name: ldr + operands: + - class: register + prefix: s + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: ldrsb + operands: + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: ldrsh + operands: + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: ldrsw + operands: + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: madd + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 5.0 + port_pressure: [[3, '2']] + throughput: 3.0 + uops: ~ +- name: mla + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mla + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mneg + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 5.0 + port_pressure: [[3, '2']] + throughput: 3.0 + uops: ~ +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: mov + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: movi + operands: + - class: register + prefix: d + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: movi + operands: + - class: register + prefix: v + shape: b + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: movi + operands: + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: movi + operands: + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: msub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 5.0 + port_pressure: [[3, '2']] + throughput: 3.0 + uops: ~ +- name: mul + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mul + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 4.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 5.0 + port_pressure: [[3, '2']] + throughput: 3.0 + uops: ~ +- name: mvn + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: mvni + operands: + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: mvni + operands: + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: neg + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: neg + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: neg + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: neg + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: neg + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: negs + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: not + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: orn + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: orr + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: rev + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: ror + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: sabd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: saddl2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: sbfiz + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: sbfx + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: scvtf + operands: + - class: register + prefix: s + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: scvtf + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: scvtf + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: scvtf + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: sdiv + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 4.0 + port_pressure: [[4, '2']] + throughput: 4.0 + uops: ~ +- name: shl + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: shl + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: shl + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: smax + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: smax + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: smax + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: smaxv + operands: + - class: register + prefix: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: smin + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: smin + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: smin + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: sminv + operands: + - class: register + prefix: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: smulh + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 6.0 + port_pressure: [[4, '2']] + throughput: 4.0 + uops: ~ +- name: smull2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: sshl + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[2, '6']] + throughput: 2.0 + uops: ~ +- name: sshl + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '6']] + throughput: 2.0 + uops: ~ +- name: sshll2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: sshll2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: sshll2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: b + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: sshr + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: sshr + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: sshr + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: ssubl2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: ssubw2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: str + operands: + - class: register + prefix: s + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 2.0 + port_pressure: [[2, '3']] + throughput: 2.0 + uops: ~ +- name: sub + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: sub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: sub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: sub + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: tst + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.5 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: tst + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: uaddl2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uaddl2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: ubfiz + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: ubfx + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: ucvtf + operands: + - class: register + prefix: s + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: ucvtf + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: ucvtf + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: ~ +- name: ucvtf + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: ~ +- name: udiv + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 4.0 + port_pressure: [[4, '2']] + throughput: 4.0 + uops: ~ +- name: umax + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: umax + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: umaxv + operands: + - class: register + prefix: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: umin + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: umlal2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: umulh + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 6.0 + port_pressure: [[4, '2']] + throughput: 4.0 + uops: ~ +- name: umull2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 1.0 + port_pressure: [[1, '4']] + throughput: 0.5 + uops: ~ +- name: ushl + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: ushll2 + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: s + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: ushll2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: ushll2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: b + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '6']] + throughput: 0.5 + uops: ~ +- name: ushr + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: ushr + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: ushr + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '6']] + throughput: 1.0 + uops: ~ +- name: usubl2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 1.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: usubw2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: uzp2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: xtn2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: h + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: xtn2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: d + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: xtn2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: s + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: ~ +- name: zip1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: zip1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: zip1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: zip2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: zip2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ +- name: zip2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 0.5 + uops: ~ diff --git a/osaca/data/a72/mapping_pmevo.json b/osaca/data/a72/mapping_pmevo.json new file mode 100644 index 0000000..f1f97c4 --- /dev/null +++ b/osaca/data/a72/mapping_pmevo.json @@ -0,0 +1,401 @@ +{ + "kind": "Mapping3", + "arch": { + "kind": "Architecture", + "ports": ["0", "1", "2", "3", "4", "5", "6"], + "name": "A72", + "insns": ["_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2", "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4", "_add_((REG:W:G:64)),_((REG:R:G:64)),_8", "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40", "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2", "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16", "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8", "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_clz_((REG:W:G:64)),_((REG:R:G:64))", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0", "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0", "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0", "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0", "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0", "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_cmn_((REG:R:G:64)),_#1", "_cmn_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth", "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_cmp_((REG:R:G:64)),_((REG:R:G:64))", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3", "_cmp_((REG:R:G:64)),_624", "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))", "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]", "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18", "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4", "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49", "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fabs_((REG:W:F:32)),_((REG:R:F:32))", "_fabs_((REG:W:F:64)),_((REG:R:F:64))", "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0", "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0", "_fcmp_((REG:R:F:32)),_#0.0", "_fcmp_((REG:R:F:32)),_((REG:R:F:32))", "_fcmp_((REG:R:F:64)),_#0.0", "_fcmp_((REG:R:F:64)),_((REG:R:F:64))", "_fcmpe_((REG:R:F:32)),_#0.0", "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))", "_fcmpe_((REG:R:F:64)),_#0.0", "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))", "_fcvt_((REG:W:F:32)),_((REG:R:F:64))", "_fcvt_((REG:W:F:64)),_((REG:R:F:32))", "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s", "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))", "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))", "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))", "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmov_((REG:W:F:32)),_((REG:R:F:32))", "_fmov_((REG:W:F:32)),_2.0e+1", "_fmov_((REG:W:F:64)),_((REG:R:F:64))", "_fmov_((REG:W:F:64)),_((REG:W:G:64))", "_fmov_((REG:W:F:64)),_1.0e+1", "_fmov_((REG:W:F:VEC)).2d,_1.0e+0", "_fmov_((REG:W:F:VEC)).4s,_1.0e+0", "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:64))", "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]", "_fneg_((REG:W:F:32)),_((REG:R:F:32))", "_fneg_((REG:W:F:64)),_((REG:R:F:64))", "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_frinta_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:32)),_((REG:R:F:32))", "_frintm_((REG:W:F:64)),_((REG:R:F:64))", "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_frintp_((REG:W:F:32)),_((REG:R:F:32))", "_frintp_((REG:W:F:64)),_((REG:R:F:64))", "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_frintx_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:32)),_((REG:R:F:32))", "_frintz_((REG:W:F:64)),_((REG:R:F:64))", "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))", "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))", "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))", "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]", "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))", "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32", "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_mov_((REG:W:G:64)),_((REG:R:G:64))", "_mov_((REG:W:G:64)),_2147483647", "_movi_((REG:W:F:64)),_-256", "_movi_((REG:W:F:VEC)).16b,_0xdf", "_movi_((REG:W:F:VEC)).4s,_0", "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8", "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8", "_movi_((REG:W:F:VEC)).8h,_0x53", "_movk_((REG:W:G:64)),_0x6c07,_lsl_16", "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64))", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2", "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6", "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8", "_mvni_((REG:W:F:VEC)).4s,_0", "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8", "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24", "_mvni_((REG:W:F:VEC)).8h,_0x40", "_neg_((REG:W:F:64)),_((REG:R:F:64))", "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_neg_((REG:W:G:64)),_((REG:R:G:64))", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3", "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2", "_negs_((REG:W:G:64)),_((REG:R:G:64))", "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9", "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296", "_rev_((REG:W:G:64)),_((REG:R:G:64))", "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14", "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32", "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32", "_scvtf_((REG:W:F:32)),_((REG:W:G:64))", "_scvtf_((REG:W:F:64)),_((REG:W:G:64))", "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3", "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h", "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3", "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56", "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10", "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s", "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]", "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]", "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3", "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5", "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b", "_tst_((REG:W:G:64)),_((REG:R:G:64))", "_tst_((REG:W:G:64)),_-3", "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6", "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2", "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))", "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d", "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s", "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b", "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]", "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))", "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b", "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))", "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s", "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0", "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0", "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0", "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0", "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0", "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0", "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63", "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19", "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1", "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8", "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h", "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h", "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h", "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d", "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d", "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s", "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h", "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h", "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b", "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s", "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h"] + }, + "assignment": { + "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], + "_saddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_mov_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fcvtzu_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_uzp1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_smulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_ldr_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_4": [["2"]], + "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_ubfx_((REG:W:G:64)),_((REG:R:G:64)),_5,_2": [["0", "5"]], + "_asr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_dup_((REG:W:F:32)),_((REG:R:F:VEC)).s[0]": [["4", "5"]], + "_frintm_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_bics_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ucvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_uzp1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4", "5"]], + "_fcvtms_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_frintp_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_sminv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_shl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_mvni_((REG:W:F:VEC)).4s,_0x7c,_msl_8": [["5"]], + "_mvni_((REG:W:F:VEC)).4s,_0x80,_lsl_24": [["5"]], + "_ushll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], + "_sub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fabd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsr_3": [["2"]], + "_shl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], + "_mneg_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_sub_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_fmls_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_dup_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_scvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fnmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_smin_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_#1824": [["0", "5"]], + "_fcvtzs_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_fabs_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_frintz_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_mvn_((REG:W:G:64)),_((REG:R:G:64)),_lsr_6": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb_3": [["2"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_ins_((REG:W:F:VEC)).d[1],_((REG:R:F:VEC)).d[0]": [["4", "5"]], + "_cmhi_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_ands_((REG:W:G:64)),_((REG:R:G:64)),_7": [["0", "5"]], + "_ldrsw_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_uaddl_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["5"]], + "_ushl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_8": [["0", "5"]], + "_fneg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_smaxv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], + "_str_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]], + "_sub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fabd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fabd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fneg_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_negs_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_rev_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_#0": [["5"]], + "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmhi_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_movi_((REG:W:F:VEC)).8h,_0x4,_lsl_8": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxth": [["2"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], + "_fcmp_((REG:R:F:32)),_((REG:R:F:32))": [["6"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]], + "_shl_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]], + "_fcvt_((REG:W:F:64)),_((REG:R:F:32))": [["4"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_fcmpe_((REG:R:F:32)),_#0.0": [["6"]], + "_fmov_((REG:W:G:64)),_((REG:W:F:64))": [["1"]], + "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_9": [["2"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxth_3": [["2"]], + "_fmov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]], + "_smin_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_-4294967296": [["0", "5"]], + "_ushll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]], + "_mla_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], + "_fcvtpu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_cmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]], + "_uminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_sminv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_2": [["2"]], + "_umin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_addv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_ldrsh_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_cmhi_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_cmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtb": [["2"]], + "_tst_((REG:W:G:64)),_-3": [["0", "5"]], + "_umax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fcvtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4"]], + "_fmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxth_3": [["2"]], + "_fdiv_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_sshll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_3": [["2"]], + "_fabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_624": [["0", "5"]], + "_sub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_cmgt_((REG:R:F:64)),_((REG:R:F:64)),_#0": [["4", "5"]], + "_fabs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:32)),_2.0e+1": [["4", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64)),_asr_2": [["2"]], + "_ushll2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_0": [["6"]], + "_ldr_((REG:W:F:8)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_sdiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_fsqrt_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_fsqrt_((REG:W:F:32)),_((REG:R:F:32))": [["4"], ["4"], ["4"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]], + "_fnmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_movi_((REG:W:F:64)),_-256": [["4", "5"]], + "_fadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_zip2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_usubw2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).8h": [["5"]], + "_umulh_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_fmov_((REG:W:F:64)),_((REG:W:G:64))": [["1"]], + "_sshr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_10": [["6"]], + "_fcvtl2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["4"]], + "_fcvtms_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_movk_((REG:W:G:64)),_0x6c07,_lsl_16": [["0", "5"]], + "_sshll2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_0": [["6"]], + "_mul_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["4"], ["4"]], + "_mvni_((REG:W:F:VEC)).4s,_0": [["5"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsr_2": [["2"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_40": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], + "_smax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_neg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_usubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn_((REG:W:F:VEC)).4h,_((REG:R:F:VEC)).4s": [["4", "5"]], + "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], + "_cmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_mul_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]], + "_fmla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_movi_((REG:W:F:VEC)).16b,_0xdf": [["5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]], + "_fabs_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcvtms_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_orr_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_ushl_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_mul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_5": [["2"]], + "_str_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_umlal_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_fcvtzu_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_fcmeq_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_cmgt_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_#0": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_fnmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fdiv_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["2"], ["2"], ["2"], ["2"]], + "_ushll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]], + "_lsl_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_abs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]], + "_fnmul_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ushr_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]], + "_not_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_sbfiz_((REG:W:G:64)),_((REG:R:G:64)),_6,_32": [["0", "5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_ushll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]], + "_saddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_ror_18": [["2"]], + "_ldr_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_fdiv_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_dup_((REG:W:F:VEC)).2d,_((REG:W:G:64))": [["5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sshr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_56": [["6"]], + "_fcvtps_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_usubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_umull2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_cmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_uzp2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_ushr_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_19": [["6"]], + "_fmadd_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_fcvtzu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_uaddl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_fcmlt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_ssubw2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).4s": [["5"]], + "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmov_((REG:W:F:VEC)).4s,_1.0e+0": [["5"]], + "_fcmle_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtw_2": [["2"]], + "_fcvtzs_((REG:W:G:64)),_((REG:W:F:32))": [["4"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_fcmp_((REG:R:F:32)),_#0.0": [["6"]], + "_fsub_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_xtn2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).4s": [["4", "5"]], + "_sshll_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_0": [["6"]], + "_bif_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_ands_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcmgt_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_mvn_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).d[0]": [["5"]], + "_mov_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4", "5"]], + "_fcvtzs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fmls_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmul_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_fmla_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_and_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintx_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_frintm_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_sabd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"]], + "_fnmsub_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_ucvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]], + "_movi_((REG:W:F:VEC)).4s,_0x4,_lsl_8": [["5"]], + "_umull_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8b,_((REG:R:F:VEC)).8b": [["4"]], + "_shl_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s,_1": [["6"]], + "_frintp_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_7": [["2"]], + "_lsr_((REG:W:G:64)),_((REG:R:G:64)),_32": [["0", "5"]], + "_sshll_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_0": [["6"]], + "_fdiv_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["0"], ["0"], ["0"]], + "_fcmp_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_sshll2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_0": [["6"]], + "_sshl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"], ["6"]], + "_str_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_bic_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_8": [["2"]], + "_ucvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_str_((REG:W:F:128)),_[((MEM:64)),_((MIMM:16))]": [["0"], ["0"]], + "_bsl_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_fneg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmn_((REG:R:G:64)),_#1": [["0", "5"]], + "_fmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_addp_((REG:W:F:64)),_((REG:R:F:VEC)).2d": [["4", "5"]], + "_movi_((REG:W:F:VEC)).4s,_0": [["5"]], + "_smax_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_add_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_ucvtf_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["4"]], + "_fcvt_((REG:W:F:32)),_((REG:R:F:64))": [["4"]], + "_fcvtn2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).2d": [["4"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_30": [["2"]], + "_movi_((REG:W:F:VEC)).4s,_0xff,_msl_8": [["5"]], + "_add_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_msub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_fcmeq_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_0": [["5"]], + "_uzp1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtw": [["2"]], + "_fsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_neg_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_str_((REG:W:F:16)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"], ["3"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_sshr_((REG:W:F:64)),_((REG:R:F:64)),_3": [["6"]], + "_addv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_fadd_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]], + "_neg_((REG:W:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_zip1_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_smax_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_umov_((REG:W:G:64)),_((REG:W:F:VEC)).d[1]": [["1"]], + "_scvtf_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_asr_((REG:W:G:64)),_((REG:R:G:64)),_2": [["0", "5"]], + "_xtn_((REG:W:F:VEC)).8b,_((REG:R:F:VEC)).8h": [["4", "5"]], + "_sshll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]], + "_orn_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_ssubl2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_scvtf_((REG:W:F:64)),_((REG:W:G:64))": [["4"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxth": [["2"]], + "_sshr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_ushll_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_0": [["6"]], + "_fmov_((REG:W:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_neg_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_smull_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_umax_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_cmeq_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_bfi_((REG:W:G:64)),_((REG:R:G:64)),_16,_16": [["2"]], + "_fcmp_((REG:R:F:64)),_#0.0": [["6"]], + "_smaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_cmhs_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_#0": [["5"]], + "_movi_((REG:W:F:VEC)).8h,_0x53": [["5"]], + "_fmul_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).s[1]": [["5"]], + "_fmov_((REG:W:F:64)),_1.0e+1": [["4", "5"]], + "_bic_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_zip1_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fadd_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_ror_((REG:W:G:64)),_((REG:R:G:64)),_14": [["0", "5"]], + "_sshl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["6"], ["6"]], + "_uzp2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fsub_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_tbl_((REG:W:F:VEC)).16b,_{((REG:R:F:VEC)).16b},_((REG:R:F:VEC)).16b": [["0"], ["0"]], + "_scvtf_((REG:W:F:32)),_((REG:W:G:64))": [["4"]], + "_ins_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]], + "_fcmpe_((REG:R:F:64)),_((REG:R:F:64))": [["6"]], + "_cmeq_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_neg_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_eor_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintm_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_dup_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).s[0]": [["5"]], + "_fcmgt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_fmadd_((REG:W:F:32)),_((REG:R:F:32)),_((REG:R:F:32)),_((REG:R:F:32))": [["4", "5"]], + "_fcvtas_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_fcmge_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["5"]], + "_adds_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw": [["2"]], + "_xtn2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).8h": [["4", "5"]], + "_abs_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2d": [["6"]], + "_fcvtl_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).2s": [["4"]], + "_fabs_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_ldr_((REG:W:F:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_ldrsb_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_add_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_fnmul_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_ubfiz_((REG:W:G:64)),_((REG:R:G:64)),_2,_6": [["0", "5"]], + "_fmov_((REG:W:F:VEC)).2d,_1.0e+0": [["5"]], + "_mvni_((REG:W:F:VEC)).4h,_0xfe,_lsl_8": [["4", "5"]], + "_mvni_((REG:W:F:VEC)).8h,_0x40": [["5"]], + "_fmsub_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_mla_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"], ["4"]], + "_fcmge_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_4": [["0", "5"]], + "_fsqrt_((REG:W:F:64)),_((REG:R:F:64))": [["4"], ["4"], ["4"], ["4"], ["4"]], + "_frinta_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_and_((REG:W:G:64)),_((REG:R:G:64)),_2147483648": [["0", "5"]], + "_uaddl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_fneg_((REG:W:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_smin_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_str_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["3"], ["3"]], + "_mul_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_ssubl_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4h,_((REG:R:F:VEC)).4h": [["5"]], + "_ushr_((REG:W:F:64)),_((REG:R:F:64)),_63": [["6"]], + "_zip2_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["5"]], + "_cmn_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_eor_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_11": [["2"]], + "_sbfx_((REG:W:G:64)),_((REG:R:G:64)),_32,_32": [["0", "5"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_3": [["2"]], + "_madd_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"]], + "_smull2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]], + "_mla_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_fcmpe_((REG:R:F:64)),_#0.0": [["6"]], + "_uaddl2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintz_((REG:W:F:64)),_((REG:R:F:64))": [["4"]], + "_fcmlt_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s,_0": [["5"]], + "_cmeq_((REG:R:F:VEC)).2s,_((REG:R:F:VEC)).2s,_#0": [["4", "5"]], + "_orr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fcvtmu_((REG:W:G:64)),_((REG:W:F:64))": [["4"]], + "_ldr_((REG:W:G:64)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_umlal2_((REG:W:F:VEC)).2d,_((REG:R:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"]], + "_ldr_((REG:W:F:32)),_[((MEM:64)),_((MIMM:16))]": [["1"]], + "_sminv_((REG:W:F:16)),_((REG:R:F:VEC)).8h": [["4"]], + "_umaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_extr_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_49": [["2"]], + "_fcvtzs_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2s": [["4"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsl_3": [["2"]], + "_udiv_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64))": [["2"], ["2"], ["2"], ["2"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_3": [["2"]], + "_uzp2_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_frintp_((REG:W:F:32)),_((REG:R:F:32))": [["4"]], + "_smaxv_((REG:W:F:8)),_((REG:R:F:VEC)).16b": [["6"], ["6"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_asr_63": [["2"]], + "_cmp_((REG:R:G:64)),_((REG:R:G:32)),_uxtb": [["2"]], + "_zip1_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["5"]], + "_umaxv_((REG:W:F:32)),_((REG:R:F:VEC)).4s": [["6"]], + "_ushr_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_8": [["6"]], + "_zip2_((REG:W:F:VEC)).8h,_((REG:R:F:VEC)).8h,_((REG:R:F:VEC)).8h": [["5"]], + "_xtn_((REG:W:F:VEC)).2s,_((REG:R:F:VEC)).2d": [["4", "5"]], + "_subs_((REG:W:G:64)),_((REG:R:G:64)),_#1": [["0", "5"]], + "_fsqrt_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"], ["4"]], + "_add_((REG:W:F:64)),_((REG:R:F:64)),_((REG:R:F:64))": [["4", "5"]], + "_bit_((REG:W:F:VEC)).16b,_((REG:R:F:VEC)).16b,_((REG:R:F:VEC)).16b": [["4"]], + "_tst_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_fmov_((REG:W:F:VEC)).d[1],_((REG:W:G:64))": [["1"]], + "_mov_((REG:W:G:64)),_2147483647": [["0", "5"]], + "_clz_((REG:W:G:64)),_((REG:R:G:64))": [["0", "5"]], + "_frintz_((REG:W:F:VEC)).4s,_((REG:R:F:VEC)).4s": [["4"], ["4"]], + "_add_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:32)),_sxtw_2": [["2"]], + "_sub_((REG:W:G:64)),_((REG:R:G:64)),_((REG:R:G:64)),_lsr_8": [["2"]], + "_fcmpe_((REG:R:F:32)),_((REG:R:F:32))": [["6"]] + } +} diff --git a/osaca/data/a72/template.yml b/osaca/data/a72/template.yml new file mode 100644 index 0000000..8a47f1e --- /dev/null +++ b/osaca/data/a72/template.yml @@ -0,0 +1,808 @@ +osaca_version: 0.3.11 +micro_architecture: Cortex A-72 +arch_code: a72 +isa: aarch64 +hidden_loads: false +ports: ['0', '1', '2', '3', '4', '5', '6', '7'] +port_model_scheme: | + +-------------------------------------------------------------------------------------+ + | scheduler | + +-------------------------------------------------------------------------------------+ + 0 |I 1 |L 2 |M 3 |S 4 |F1 5 |I 6 |F0 7 |B + \/ \/ \/ \/ \/ \/ \/ \/ + +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+ + |INT ALU| | LOAD | | MUL | | STORE | | ASIMD | |INT ALU| | ASIMD | | Branch| + +-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+ + +-------+ +-------+ +-----------+ +-------+ +---------+ + | AGU | | DIV | | FP ALU | | AGU | |ASIMD MUL| + +-------+ +-------+ +-----------+ +-------+ +---------+ + +-------+ +-----------+ +---------+ + | SHIFT | | FP MUL | | FP ALU | + +-------+ +-----------+ +---------+ + +-------+ +-----------+ +---------+ + | CRC | | FP DIV | | FP MUL | + +-------+ +-----------+ +---------+ + +-------+ +-----------+ +---------+ + | USAD | | FP SQRT | | FP DIV | + +-------+ +-----------+ +---------+ + +-----------+ +---------+ + |ASIMD SHIFT| | FP CONV | + +-----------+ +---------+ + +---------+ + | CRYPTO | + +---------+ +# The port pressues do not always correctly match this schema, because most +# instructions are imported from an experimentally determined mapping, which +# is not always correct. +load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0} +load_throughput: [] +load_throughput_default: [[1, '1']] +store_throughput: [] +store_throughput_default: [[2, '3']] +instruction_forms: + +# Branch +- name: b + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: bne + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: b.ne + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: br + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: ret + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '7']] + throughput: 1.0 +- name: bl + operands: + - class: identifier + latency: 1.0 + port_pressure: [[1, '05'], [1, '7']] + throughput: 1.0 +- name: blr + operands: + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '05'], [1, '7']] + throughput: 1.0 + +# Load GPR +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Load FP d +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 + +# Load FP q +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: true + pre-indexed: false + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: true + latency: 5.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 6.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 6.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 6.0 + port_pressure: [[1, '1'], [2, '05']] + throughput: 1.0 + +# Store GPR +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3']] + throughput: 1.0 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Store FP d +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 1.0 + port_pressure: [[1, '3'], [1, '05']] + throughput: 1.0 + +# Store FP q +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3']] + throughput: 2.0 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + post-indexed: false + pre-indexed: true + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[2, '3'], [2, '05']] + throughput: 2.0 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[2, '3'], [2, '05']] + throughput: 2.0 + +# Load unscaled GPR +- name: ldur + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 + +# Load unscaled FP q +- name: ldur + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 5.0 + port_pressure: [[1, '1']] + throughput: 1.0 + +# Store unscaled GPR +- name: stur + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 1.0 + port_pressure: [[1, '3']] + throughput: 1.0 + +# Store unscaled FP q +- name: stur + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: '*' + pre-indexed: '*' + latency: 2.0 + port_pressure: [[2, '3']] + throughput: 2.0 + +# Load pair GPR +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1']] + throughput: 1.0 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[1, '1'], [1, '05']] + throughput: 1.0 + +# Load pair FP q +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 6.0 + port_pressure: [[2, '1']] + throughput: 2.0 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 6.0 + port_pressure: [[2, '1'], [1, '05']] + throughput: 2.0 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 6.0 + port_pressure: [[2, '1'], [1, '05']] + throughput: 2.0 + +# Store pair GPR +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 2.0 + port_pressure: [[2, '3']] + throughput: 2.0 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 2.0 + port_pressure: [[2, '3'], [1, '05']] + throughput: 2.0 + +# Store pair FP q +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + latency: 4.0 + port_pressure: [[4, '3'], [1, '05']] + throughput: 4.0 + +# Fast-forward (measures 4 cycles, but can be 3) +# Lower bound is used in order to ensure no over-estimates are possible. +# Ports do not match documentation, but "fixing" requires also "fixing" almost +# the entire rest of the model. +- name: fadd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: fsub + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: fsub + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '5']] + throughput: 1.0 + +# Automatically generated instructions diff --git a/osaca/data/pmevo_importer.py b/osaca/data/pmevo_importer.py new file mode 100755 index 0000000..ba8d041 --- /dev/null +++ b/osaca/data/pmevo_importer.py @@ -0,0 +1,321 @@ +#!/usr/bin/env python3 +import argparse +import json +import math +import re +import sys + +from asmbench import bench, op +from osaca.semantics import MachineModel + + +def build_bench_instruction(name, operands): + # Converts an OSACA model instruction to an asmbench one. + # Returns `None` in case something went wrong. + asmbench_inst = name + direction = "dst" + separator = " " + shift = "" + for operand in operands: + if operand["class"] == "register" or operand["class"] == "register_shift": + if operand["prefix"] == "x": + shape = "i64" + constraint = "r" + elif operand["prefix"] == "s": + shape = "float" + constraint = "w" + elif operand["prefix"] == "d": + shape = "double" + constraint = "w" + elif operand["prefix"] == "v": + constraint = "w" + if operand["shape"] == "b": + shape = "<16 x i8>" + elif operand["shape"] == "h": + shape = "<8 x i16>" + elif operand["shape"] == "s": + shape = "<4 x float>" + elif operand["shape"] == "d": + shape = "<2 x double>" + else: + return None + else: + return None + if operand["class"] == "register_shift": + shift = ", {}".format(operand["shift_op"]) + if operand["shift"] is not None: + shift += " {}".format(operand["shift"]) + elif operand["class"] == "immediate" or operand["class"] == "immediate_shift": + shape = "i32" + # Different instructions have different ranges for literaly, + # so need to pick something "reasonable" for each. + if name in [ + "cmeq", + "cmge", + "cmgt", + "cmle", + "cmlt", + "fcmeq", + "fcmge", + "fcmgt", + "fcmle", + "fcmlt", + "fcmp", + ]: + constraint = "0" + elif name in ["and", "ands", "eor", "eors", "orr", "orrs"]: + constraint = "255" + elif name in ["bfi", "extr", "sbfiz", "sbfx", "shl", "sshr", "ubfiz", "ubfx", "ushr"]: + constraint = "7" + else: + constraint = "42" + if operand["class"] == "immediate_shift": + shift = ", {}".format(operand["shift_op"]) + if operand["shift"] is not None: + shift += " {}".format(operand["shift"]) + else: + return None + asmbench_inst += "{}{{{}:{}:{}}}{}".format(separator, direction, shape, constraint, shift) + direction = "src" + separator = ", " + return asmbench_inst + + +def bench_instruction(name, operands): + # Converts an OSACA model instruction to an asmbench one and benchmarks it. + # Returned tuple may contain a `None` in case something went wrong. + asmbench_inst = build_bench_instruction(name, operands) + if asmbench_inst is None: + return (None, None) + return bench.bench_instructions([op.Instruction.from_string(asmbench_inst)]) + + +def round_cycles(value): + if value < 0.9: + # Frequently found, so we might want to include them. + # Measurements over-estimate a lot here, hence the high bound. + return 0.5 + else: + # Measurements usually over-estimate, so usually round down, + # but still allow slightly smaller values. + return float(math.floor(value + 0.1)) + + +def operand_parse(op, state): + # Parses an operand from an PMEvo instruction and emits an OSACA model one. + # State object is used to keep track of types for future operands, e.g. literals. + # Future invocations may also modify previously returned objects. + parameter = {} + + if op.startswith("_((REG:"): + parts = op.split(".") + register = parts[0][7:-2] + read_write, register_type, bits = register.split(":") + + parameter["class"] = "register" + if register_type == "G": + if bits == "32": + parameter["prefix"] = "r" + elif bits == "64": + parameter["prefix"] = "x" + else: + raise ValueError("Invalid register bits for {} {}".format(register_type, bits)) + elif register_type == "F": + if bits == "32": + parameter["prefix"] = "s" + state["type"] = "float" + elif bits == "64": + parameter["prefix"] = "d" + state["type"] = "double" + elif bits == "128": + parameter["prefix"] = "q" + elif bits == "VEC": + vec_shape = parts[1] + parameter["prefix"] = "v" + if vec_shape == "16b": + parameter["shape"] = "b" + elif vec_shape == "8h": + parameter["shape"] = "h" + elif vec_shape == "4s": + parameter["shape"] = "s" + state["type"] = "float" + elif vec_shape == "2d": + parameter["shape"] = "d" + state["type"] = "double" + else: + raise ValueError("Invalid vector shape {}".format(vec_shape)) + else: + raise ValueError("Invalid register bits for {} {}".format(register_type, bits)) + else: + raise ValueError("Unknown register type {}".format(register_type)) + elif op.startswith("_[((MEM:"): + bits = op[8:-2].split(":")[0] + if bits == "64": + state["memory_base"] = "x" + else: + raise ValueError("Invalid register bits for MEM {}".format(bits)) + return None + elif op.startswith("_((MIMM:"): + bits = op[8:-3].split(":")[0] + if bits == "16": + parameter["class"] = "memory" + parameter["base"] = state["memory_base"] + parameter["offset"] = "imd" + parameter["index"] = "*" + parameter["scale"] = "*" + parameter["post-indexed"] = False + parameter["pre-indexed"] = False + else: + raise ValueError("Invalid register bits for MEM {}".format(bits)) + elif re.fullmatch("_#?-?(0x)?[0-9a-f]+", op): + parameter["class"] = "immediate" + parameter["imd"] = "int" + elif re.fullmatch("_#?-?[0-9]*\\.[0-9]*", op): + parameter["class"] = "immediate" + parameter["imd"] = state["type"] + elif re.fullmatch("_((sxt|uxt)[bhw]|lsl|lsr|asr|rol|ror)(_[0-9]+)?", op): + # split = op[1:].split('_') + # shift_op = split[0] + # shift = None + # if len(split) >= 2: + # shift = split[1] + # state['previous']['class'] += '_shift' + # state['previous']['shift_op'] = shift_op + # if shift != None: + # state['previous']['shift'] = shift + # return None + raise ValueError("Skipping instruction with shift operand: {}".format(op)) + else: + raise ValueError("Unknown operand {}".format(op)) + + state["previous"] = parameter + return parameter + + +def port_convert(ports): + # Try to merge repeated entries together and emit in OSACA's format. + # FIXME: This does not handle having more than 10 ports. + pressures = [] + previous = None + cycles = 0 + + for entry in ports: + possible_ports = "".join(entry) + + if possible_ports != previous: + if previous is not None: + pressures.append([cycles, previous]) + previous = possible_ports + cycles = 0 + + cycles += 1 + + if previous is not None: + pressures.append([cycles, previous]) + + return pressures + + +def throughput_guess(ports): + # Minimum amount of possible ports per cycle should determine throughput + # to some degree of accuracy. (THIS IS *NOT* ALWAYS TRUE!) + bottleneck_ports = min(map(lambda it: len(it), ports)) + return float(len(ports)) / bottleneck_ports + + +def latency_guess(ports): + # Each entry in the ports array equates to one cycle on any of the ports. + # So this is about as good as it is going to get. + return float(len(ports)) + + +def extract_model(mapping, arch, template_model, asmbench): + try: + isa = MachineModel.get_isa_for_arch(arch) + except ValueError: + print("Skipping...", file=sys.stderr) + return None + if template_model is None: + mm = MachineModel(isa=isa) + else: + mm = template_model + + for port in mapping["arch"]["ports"]: + mm.add_port(port) + + for insn in mapping["arch"]["insns"]: + try: + ports = mapping["assignment"][insn] + + # Parse instruction + insn_split = insn.split("_") + name = insn_split[1] + insn_parts = list(("_" + "_".join(insn_split[2:])).split(",")) + operands = [] + state = {} + for operand in insn_parts: + parsed = operand_parse(operand, state) + if parsed is not None: + operands.append(parsed) + + # Port pressures from mapping + port_pressure = port_convert(ports) + + # Initial guessed throughput and latency + throughput = throughput_guess(ports) + latency = latency_guess(ports) + + # Benchmark with asmbench + # print(build_bench_instruction(name, operands)) + if asmbench: + bench_latency, bench_throughput = bench_instruction(name, operands) + if bench_throughput is not None: + throughput = round_cycles(bench_throughput) + else: + print("Failed to measure throughput for instruction {}.".format(insn)) + if bench_latency is not None: + latency = round_cycles(bench_latency) + else: + print("Failed to measure latency for instruction {}.".format(insn)) + + # No u-ops data available + uops = None + + # Insert instruction if not already found (can happen with template) + if mm.get_instruction(name, operands) is None: + mm.set_instruction(name, operands, latency, port_pressure, throughput, uops) + except ValueError as e: + print("Failed to parse instruction {}: {}.".format(insn, e)) + + return mm + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("json", help="path of mapping.json") + parser.add_argument("yaml", help="path of template.yml", nargs="?") + parser.add_argument( + "--asmbench", help="Benchmark latency and throughput using asmbench.", action="store_true" + ) + args = parser.parse_args() + + json_file = open(args.json, "r") + mapping = json.load(json_file) + arch = mapping["arch"]["name"].lower() + json_file.close() + + template_model = None + if args.yaml is not None: + template_model = MachineModel(path_to_yaml=args.yaml) + + if args.asmbench: + bench.setup_llvm() + + model = extract_model(mapping, arch, template_model, args.asmbench) + + with open("{}.yml".format(arch.lower()), "w") as f: + f.write(model.dump()) + + +if __name__ == "__main__": + main() diff --git a/osaca/osaca.py b/osaca/osaca.py index 765cff7..44f9683 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -32,6 +32,7 @@ SUPPORTED_ARCHS = [ "TX2", "N1", "A64FX", + "A72", ] DEFAULT_ARCHS = { "aarch64": "A64FX", @@ -95,7 +96,7 @@ def create_parser(parser=None): "--arch", type=str, help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, " - "A64FX). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", + "A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", ) parser.add_argument( "--fixed", diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index 948c2de..1ee6968 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -266,11 +266,13 @@ class MachineModel(object): """Return ISA for given micro-arch ``arch``.""" arch_dict = { "a64fx": "aarch64", + "a72": "aarch64", "tx2": "aarch64", "n1": "aarch64", "zen1": "x86", "zen+": "x86", "zen2": "x86", + "icl": "x86", "con": "x86", # Intel Conroe "wol": "x86", # Intel Wolfdale "snb": "x86",