diff --git a/osaca/data/a72.yml b/osaca/data/a72.yml
index e0df92b..caef68c 100644
--- a/osaca/data/a72.yml
+++ b/osaca/data/a72.yml
@@ -1,4 +1,4 @@
-osaca_version: 0.3.11
+osaca_version: 0.5.0
 micro_architecture: Cortex A-72
 arch_code: a72
 isa: aarch64
@@ -9,6 +9,7 @@ load_throughput_default: [[1, '1']]
 store_throughput: []
 store_throughput_default: [[2, '3']]
 ports: ['0', '1', '2', '3', '4', '5', '6', '7']
+p_index_latency: 3
 port_model_scheme: |
   +-------------------------------------------------------------------------------------+
   |                                      scheduler                                      |
diff --git a/osaca/data/n1.yml b/osaca/data/n1.yml
index d189c44..c15be0c 100644
--- a/osaca/data/n1.yml
+++ b/osaca/data/n1.yml
@@ -1,4 +1,4 @@
-osaca_version: 0.3.4
+osaca_version: 0.5.0
 micro_architecture: Arm Neoverse N1 
 arch_code: n1
 isa: AArch64
@@ -7,6 +7,7 @@ retired_uOps_per_cycle: 8       # wikichip
 scheduler_size: 120             # wikichip
 hidden_loads: false
 load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 5.0, q: 6.0, v: 5.0, z: 4.0}
+p_index_latency: 1
 load_throughput:
 - {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure:   [[1, '67']]}
 - {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure:  [[1, '67'], [1, '123']]}
diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml
index d23b3a5..d0b1af9 100644
--- a/osaca/data/tsv110.yml
+++ b/osaca/data/tsv110.yml
@@ -1,4 +1,4 @@
-osaca_version: 0.4.8
+osaca_version: 0.5.0
 micro_architecture: TaiShan v110 # https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110
 arch_code: tsv110
 isa: AArch64
@@ -7,6 +7,7 @@ retired_uOps_per_cycle: 4
 scheduler_size: ~   # unknown
 hidden_loads: false
 load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
+p_index_latency: 1
 load_throughput: []
 load_throughput_default: [[1, '67']]
 store_throughput: []
diff --git a/osaca/data/tx2.yml b/osaca/data/tx2.yml
index 994a16f..cf35893 100644
--- a/osaca/data/tx2.yml
+++ b/osaca/data/tx2.yml
@@ -1,4 +1,4 @@
-osaca_version: 0.3.4
+osaca_version: 0.5.0
 micro_architecture: Thunder X2
 arch_code: tx2
 isa: AArch64
@@ -7,6 +7,7 @@ retired_uOps_per_cycle: 4
 scheduler_size: 60
 hidden_loads: false
 load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
+p_index_latency: 1
 load_throughput:
 - {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure:   [[1, '34'], [1, '012']]}
 - {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure:  [[1, '34'], [1, '012']]}
@@ -1214,4 +1215,4 @@ instruction_forms:
     imd: int
   throughput: 1.0
   latency: 6.0
-  port_pressure: [[1, '01']]
\ No newline at end of file
+  port_pressure: [[1, '01']]