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JanLJL
2024-05-02 21:17:57 +02:00
parent 764b22cebe
commit 2ba04e614a
3 changed files with 945 additions and 540 deletions
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313
osaca/data/spr.yml
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@@ -2946,7 +2946,7 @@ instruction_forms:
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 5 # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
@@ -2959,7 +2959,7 @@ instruction_forms:
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 5 # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
@@ -3338,7 +3338,7 @@ instruction_forms:
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
@@ -3353,7 +3353,7 @@ instruction_forms:
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench
throughput: 1.0 # ibench
uops: 9 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
@@ -3368,7 +3368,7 @@ instruction_forms:
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 16 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
@@ -3383,7 +3383,7 @@ instruction_forms:
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench
throughput: 3.0 # ibench
uops: 31 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
@@ -3397,7 +3397,7 @@ instruction_forms:
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench
throughput: 1.0 # ibench
uops: 9 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
@@ -3411,7 +3411,7 @@ instruction_forms:
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 16 # ibench
- name: vgatherdpd # with load # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
@@ -3520,7 +3520,7 @@ instruction_forms:
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 5 # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
@@ -3712,7 +3712,7 @@ instruction_forms:
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
@@ -3724,7 +3724,7 @@ instruction_forms:
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
@@ -3736,7 +3736,7 @@ instruction_forms:
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
@@ -3748,7 +3748,7 @@ instruction_forms:
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
@@ -3761,7 +3761,7 @@ instruction_forms:
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
@@ -3774,7 +3774,7 @@ instruction_forms:
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: vpaddd # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
@@ -4079,6 +4079,15 @@ instruction_forms:
port_pressure: [[1, ['0','1','5','6','11']]]
throughput: 0.20
uops: 1
- name: vcvtdq2pd # uops.info
operands: # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: zmm # uops.info
latency: 7 # uops.info
port_pressure: [[1, '0'], [1, '5']] # uops.info
throughput: 1 # uops.info
- name: vcvtss2si # uops.info
operands: # uops.info
- class: register # uops.info
@@ -4413,6 +4422,28 @@ instruction_forms:
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vcvtsi2sd
operands:
- class: register
name: gpr
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 3
- name: vcvtdq2pd
operands:
- class: register
name: xmm
- class: register
name: ymm
latency: 7
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 2
- name: vcvtsi2ss
operands:
- class: register
@@ -4421,9 +4452,9 @@ instruction_forms:
name: xmm
- class: register
name: xmm
latency: 2
port_pressure: [[1, '01'], [2, '5']]
throughput: 2.0
latency: 4
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 3
- name: [vextractf128, vextracti128]
operands:
@@ -4599,6 +4630,20 @@ instruction_forms:
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: vpinsrd # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: gpr # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '15'], [1, '1']] # asmbench
throughput: 1.0 # asmbench
uops: 2 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
@@ -4725,7 +4770,7 @@ instruction_forms:
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpermd # asmbench
- name: [vpermd, vpermt2q] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
@@ -4737,7 +4782,7 @@ instruction_forms:
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpermd # asmbench
- name: [vpermd, vpermt2q] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
@@ -4800,6 +4845,156 @@ instruction_forms:
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
@@ -5356,6 +5551,16 @@ instruction_forms:
port_pressure: [[1, ['0','1','5','6','11']]]
throughput: 0.20
uops: 1
- name: VPBROADCASTD
operands:
- class: register
name: gpr
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VBROADCASTSS
operands:
- class: register
@@ -5462,3 +5667,71 @@ instruction_forms:
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vmovd
operands:
- class: register
name: gpr
- class: register
name: xmm
latency: 1
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]]
throughput: 0.2
uops: 1.0
- name: vmov
operands:
- class: register
name: gpr
- class: register
name: xmm
latency: 1
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]]
throughput: 0.2
uops: 1.0
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.3333333
uops: 1
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.3333333
uops: 1
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: zmm
latency: 1
port_pressure: [[1, '05']]
throughput: 0.5
uops: 1
- name: [kxorb, kxorw, kxord, kxorq, kxnorb, kxnorw, kxnord, kxnorq]
operands:
- class: register
name: k
- class: register
name: k
- class: register
name: k
latency: 1
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1

358
osaca/data/v2.yml
View File

@@ -9,11 +9,17 @@ hidden_loads: false
load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 7.0, s: 6.0, d: 6.0, q: 6.0, v: 6.0, z: 6.0}
p_index_latency: 1
load_throughput:
- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]}
- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]}
- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]}
load_throughput_default: [[1, ['12', '13', '14']]]
store_throughput:
- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]}
- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]}
- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]}
@@ -1668,6 +1674,15 @@ instruction_forms:
throughput: 1.0
latency: 3.0 # 1*p6
port_pressure: [[1, '6']]
- name: [scvtf, ucvtf]
operands:
- class: register
prefix: d
- class: register
prefix: w
throughput: 1.0
latency: 3.0 # 1*p6
port_pressure: [[1, '6']]
- name: [scvtf, ucvtf]
operands:
- class: register
@@ -1719,6 +1734,8 @@ instruction_forms:
- class: register
prefix: w
throughput: 5.0
latency: 5.0 # 2*p67DV
port_pressure: [[1, '67'], [10, ['6DV', '7DV']]]
- name: [smaddl, smsubl, umaddl, umsubl]
operands:
- class: register
@@ -1778,7 +1795,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -1792,7 +1809,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -1806,7 +1823,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1+2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -1820,7 +1837,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1+2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -1834,7 +1851,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1+2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -1848,7 +1865,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1+2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1864,7 +1881,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1880,7 +1897,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1896,7 +1913,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1912,7 +1929,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1928,7 +1945,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1944,7 +1961,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1960,7 +1977,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1976,7 +1993,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -1992,7 +2009,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2008,7 +2025,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2024,7 +2041,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2040,7 +2057,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2056,7 +2073,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2072,7 +2089,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+1*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2088,7 +2105,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2104,7 +2121,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2120,7 +2137,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2136,7 +2153,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+1*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2152,7 +2169,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2168,7 +2185,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2184,7 +2201,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2200,7 +2217,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2216,7 +2233,7 @@ instruction_forms:
pre-indexed: true
throughput: 1.0
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2232,7 +2249,7 @@ instruction_forms:
pre-indexed: true
throughput: 1.0
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2248,7 +2265,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2264,7 +2281,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2280,7 +2297,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2296,7 +2313,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2312,7 +2329,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2322,7 +2339,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2332,7 +2349,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2342,7 +2359,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2352,7 +2369,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2362,7 +2379,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: [str, stur]
operands:
- class: register
@@ -2372,7 +2389,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2384,7 +2401,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2396,7 +2413,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2408,7 +2425,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2420,7 +2437,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2432,7 +2449,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2444,7 +2461,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2456,7 +2473,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2468,7 +2485,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2480,7 +2497,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2492,7 +2509,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2504,7 +2521,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2516,7 +2533,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2528,7 +2545,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2540,7 +2557,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2552,7 +2569,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2564,7 +2581,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2576,7 +2593,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2588,7 +2605,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2600,7 +2617,7 @@ instruction_forms:
pre-indexed: false
throughput: 1.0
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2612,7 +2629,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2624,7 +2641,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2636,7 +2653,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p12,13+2*p15,16
port_pressure: [[1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2648,7 +2665,7 @@ instruction_forms:
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2660,7 +2677,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: stp
operands:
- class: register
@@ -2676,7 +2693,7 @@ instruction_forms:
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p2367+1*p12,13+2*p15,16
port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]]
port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]]
- name: sub
operands:
- class: register
@@ -2823,7 +2840,22 @@ instruction_forms:
shape: '*'
width: '*'
- class: immediate
imd: int
imd: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]
- name: fadd
operands:
- class: register
prefix: '*'
shape: '*'
width: '*'
- class: register
prefix: '*'
shape: '*'
width: '*'
- class: immediate
imd: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]
@@ -2860,7 +2892,7 @@ instruction_forms:
- class: register
prefix: s
- class: immediate
imd: int
imd: '*'
- class: condition
ccode: "*"
throughput: 1.0
@@ -2928,7 +2960,7 @@ instruction_forms:
shape: d
width: '*'
throughput: 5.0
latency: 12.0 # 1*p67
latency: 12.0 # 1*p8,10
port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]]
- name: fdiv
operands:
@@ -4162,7 +4194,7 @@ instruction_forms:
post-indexed: false
throughput: 1.0
latency: 6.0 # 1*p12,13,14
port_pressure: [[3, ['12', '13', '14']]]
port_pressure: [[1, ['12', '13', '14']]]
- name: [ld1d, ld1sw, ld1sh, ld1sb]
operands:
- class: register
@@ -4180,7 +4212,7 @@ instruction_forms:
post-indexed: false
throughput: 1.0
latency: 6.0 # 1*p12,13,14
port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]]
port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]]
- name: [ld1d, ld1sw, ld1sh, ld1sb]
operands:
- class: register
@@ -4198,7 +4230,7 @@ instruction_forms:
post-indexed: true
throughput: 1.0
latency: 6.0 # 1*p12,13,14
port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]]
port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]]
- name: [ld1d, ld1w, ld1h, ld1b] # gather
operands:
- class: register
@@ -4216,7 +4248,7 @@ instruction_forms:
post-indexed: false
throughput: 1.0
latency: 9.0 # 1*p12,13,14
port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]]
port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]]
- name: [ld1d, ld1w, ld1h, ld1b] # gather
operands:
- class: register
@@ -4234,7 +4266,7 @@ instruction_forms:
post-indexed: false
throughput: 1.0
latency: 9.0 # 1*p12,13,14
port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]]
port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]]
- name: [ld1d, ld1w, ld1h, ld1b] # gather
operands:
- class: register
@@ -4252,15 +4284,15 @@ instruction_forms:
post-indexed: true
throughput: 1.0
latency: 9.0 # 1*p12,13,14
port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]]
port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]]
- name: [ld2d, ld2w, ld2h, ld2b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4277,11 +4309,11 @@ instruction_forms:
- name: [ld2d, ld2w, ld2h, ld2b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4298,11 +4330,11 @@ instruction_forms:
- name: [ld2d, ld2w, ld2h, ld2b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4319,11 +4351,11 @@ instruction_forms:
- name: [ld3d, ld3w, ld3h, ld3b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4340,11 +4372,11 @@ instruction_forms:
- name: [ld3d, ld3w, ld3h, ld3b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4361,11 +4393,11 @@ instruction_forms:
- name: [ld3d, ld3w, ld3h, ld3b]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4486,15 +4518,15 @@ instruction_forms:
post-indexed: false
throughput: 1.0
latency: 0 # 2*p89+2*p12,13
port_pressure: [[2, '89'], [1, ['12','13']]]
port_pressure: [[2, ['15','16']], [1, ['12','13']]]
- name: [st2d, st2w, st2b, st2h]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4507,15 +4539,15 @@ instruction_forms:
post-indexed: false
throughput: 2.0
latency: 0 # 2*p89+2*p12,13
port_pressure: [[2, '89'], [1, ['12','13']]]
port_pressure: [[2, ['15','16']], [1, ['12','13']]]
- name: [st3d, st3w, st3b, st3h]
operands:
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: 'z'
shape: 'd'
prefix: z
shape: d
- class: register
prefix: p
predication: '*'
@@ -4528,7 +4560,7 @@ instruction_forms:
post-indexed: false
throughput: 2.0
latency: 0 # 2*p89+2*p12,13
port_pressure: [[4, '89'], [1, ['12','13']]]
port_pressure: [[4, ['15','16']], [1, ['12','13']]]
- name: tbl
operands:
- class: register
@@ -4572,7 +4604,7 @@ instruction_forms:
throughput: 0.25
latency: 2.0 # 2*p89,10,11
port_pressure: [[1, ['8','9','10','11']]]
- name: scvtf
- name: [scvtf, ucvtf]
operands:
- class: register
prefix: z
@@ -4585,7 +4617,7 @@ instruction_forms:
throughput: 1.0
latency: 4.0
port_pressure: [[2, ['8','10']]]
- name: scvtf
- name: [scvtf, ucvtf]
operands:
- class: register
prefix: z
@@ -4598,7 +4630,7 @@ instruction_forms:
throughput: 2.0
latency: 6.0
port_pressure: [[4, ['8','10']]]
- name: scvtf
- name: [scvtf, ucvtf]
operands:
- class: register
prefix: z
@@ -4611,3 +4643,103 @@ instruction_forms:
throughput: 0.5
latency: 3.0
port_pressure: [[1, ['8','10']]]
- name: [scvtf, ucvtf]
operands:
- class: register
prefix: z
shape: d
- class: register
prefix: p
- class: register
prefix: z
shape: s
throughput: 0.5
latency: 3.0
port_pressure: [[1, ['8','10']]]
- name: [fdiv, fdivr]
operands:
- class: register
prefix: z
shape: d
width: '*'
- class: register
prefix: p
- class: register
prefix: z
shape: d
width: '*'
- class: register
prefix: z
shape: d
width: '*'
throughput: 3.0
latency: 7.0 # 1*p8,10
port_pressure: [[1, ['8', '10']], [6, ['8DV','10DV']]]
- name: fadd
operands:
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: p
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: z
shape: '*'
width: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]
- name: fadd
operands:
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: p
- class: register
prefix: z
shape: '*'
width: '*'
- class: immediate
imd: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]
- name: add
operands:
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: z
shape: '*'
width: '*'
- class: immediate
imd: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]
- name: add
operands:
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: z
shape: '*'
width: '*'
- class: register
prefix: z
shape: '*'
width: '*'
throughput: 0.25
latency: 2.0 # 1*p8,9,10,11
port_pressure: [[1, ['8', '9', '10', '11']]]