diff --git a/osaca/data/icl.yml b/osaca/data/icl.yml index e3fa4f9..a3c5398 100644 --- a/osaca/data/icl.yml +++ b/osaca/data/icl.yml @@ -129,6 +129,26 @@ instruction_forms: throughput: 0.25 # ./generate_mov_entries.py csx uops: 1 # ./generate_mov_entries.py csx ########################################## +- name: AND # model_importer.py instructions.xml ICL + operands: # model_importer.py instructions.xml ICL + - class: register # model_importer.py instructions.xml ICL + name: gpr # model_importer.py instructions.xml ICL + - class: register # model_importer.py instructions.xml ICL + name: gpr # model_importer.py instructions.xml ICL + latency: 1 # model_importer.py instructions.xml ICL + port_pressure: [[1, '0156']] # model_importer.py instructions.xml ICL + throughput: 0.25 # model_importer.py instructions.xml ICL + uops: 1 # model_importer.py instructions.xml ICL +- name: OR # model_importer.py instructions.xml ICL + operands: # model_importer.py instructions.xml ICL + - class: register # model_importer.py instructions.xml ICL + name: gpr # model_importer.py instructions.xml ICL + - class: register # model_importer.py instructions.xml ICL + name: gpr # model_importer.py instructions.xml ICL + latency: 1 # model_importer.py instructions.xml ICL + port_pressure: [[1, '0156']] # model_importer.py instructions.xml ICL + throughput: 0.25 # model_importer.py instructions.xml ICL + uops: 1 # model_importer.py instructions.xml ICL - name: ADCX # model_importer.py instructions.xml ICL operands: # model_importer.py instructions.xml ICL - class: register # model_importer.py instructions.xml ICL diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 8f2d071..8803d25 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -558,6 +558,18 @@ instruction_forms: throughput: 0.3333 latency: 1.0 port_pressure: [[1, '012']] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: w + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 - name: add operands: - class: register