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Merge branch 'master' into merge-branch

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This commit is contained in:
JanLJL
2025-03-07 14:45:44 +01:00
parent ff727223bb 4e3994fec1
commit 2cf2bf5cec
6 changed files with 100 additions and 6 deletions
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2
osaca/parser/__init__.py
View File

@@ -26,7 +26,7 @@ __all__ = [
def get_parser(isa, syntax="ATT"):
if isa.lower() == "x86":
return ParserX86ATT() if syntax == "ATT" else ParserX86Intel()
return ParserX86ATT() if syntax.upper() == "ATT" else ParserX86Intel()
elif isa.lower() == "aarch64":
return ParserAArch64()
else:

11
osaca/parser/parser_AArch64.py
View File

@@ -170,16 +170,18 @@ class ParserAArch64(BaseParser):
+ pp.Optional(immediate).setResultsName("shift")
).setResultsName(self.immediate_id)
# Register:
# scalar: [XWBHSDQ][0-9]{1,2} | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
# scalar: [XWBHSDQ][0-9]{1,2}! | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
# | predicate: P[0-9]{1,2}(/[ZM])?
# ignore vector len control ZCR_EL[123] for now
# define SP, ZR register aliases as regex, due to pyparsing does not support
# proper lookahead
alias_r31_sp = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(sp|SP))")
alias_r31_zr = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(zr|ZR))")
scalar = pp.Word("xwbhsdqXWBHSDQ", exact=1).setResultsName("prefix") + pp.Word(
pp.nums
).setResultsName("name")
scalar = (
pp.Word("xwbhsdqXWBHSDQ", exact=1).setResultsName("prefix")
+ pp.Word(pp.nums).setResultsName("name")
+ pp.Optional(pp.Literal("!")).setResultsName("pre_indexed")
)
index = pp.Literal("[") + pp.Word(pp.nums).setResultsName("index") + pp.Literal("]")
vector = (
pp.oneOf("v z", caseless=True).setResultsName("prefix")
@@ -463,6 +465,7 @@ class ParserAArch64(BaseParser):
lanes=operand["lanes"] if "lanes" in operand else None,
index=operand["index"] if "index" in operand else None,
predication=operand["predication"].lower() if "predication" in operand else None,
pre_indexed=True if "pre_indexed" in operand else False,
)
def process_memory_address(self, memory_address):

22
osaca/semantics/isa_semantics.py
View File

@@ -87,6 +87,22 @@ class ISASemantics(object):
instruction_form
)
op_dict["src_dst"] = []
# handle Xd! registers in aarch64
if any(
[
isinstance(op, RegisterOperand) and op.pre_indexed
for op in instruction_form.operands
]
):
src_dst_regs = [
op
for op in instruction_form.operands
if (isinstance(op, RegisterOperand) and op.pre_indexed)
]
for reg in src_dst_regs:
if reg in op_dict["source"]:
op_dict["source"].remove(reg)
op_dict["src_dst"].append(reg)
# post-process pre- and post-indexing for aarch64 memory operands
if self._parser.isa() == "aarch64":
for operand in [op for op in op_dict["source"] if isinstance(op, MemoryOperand)]:
@@ -178,7 +194,11 @@ class ISASemantics(object):
base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name
reg_operand_names = {base_name: "op1"}
operand_state = {"op1": {"name": base_name, "value": o.offset.value}}
if o.offset:
operand_state = {"op1": {"name": base_name, "value": o.offset.value}}
else:
# no offset (e.g., with Arm9 memops) -> base is updated
operand_state = {"op1": None}
if isa_data is not None and isa_data.operation is not None:
for i, o in enumerate(instruction_form.operands):