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changed reg scale value to int and added prefix x for sp

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This commit is contained in:
JanLJL
2019-07-03 12:55:42 +02:00
parent 2fffb07feb
commit 2e23820a55
4 changed files with 26 additions and 15 deletions
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15
osaca/parser/parser_AArch64v81.py
View File

@@ -306,6 +306,8 @@ class ParserAArch64v81(BaseParser):
): ):
# TODO: discuss if ranges should be converted to lists # TODO: discuss if ranges should be converted to lists
return self.substitute_register_list(operand[self.REGISTER_ID]) return self.substitute_register_list(operand[self.REGISTER_ID])
if self.REGISTER_ID in operand and operand[self.REGISTER_ID]['name'] == 'sp':
return self.substitute_sp_register(operand[self.REGISTER_ID])
# add value attribute to floating point immediates without exponent # add value attribute to floating point immediates without exponent
if self.IMMEDIATE_ID in operand: if self.IMMEDIATE_ID in operand:
return self.substitute_immediate(operand[self.IMMEDIATE_ID]) return self.substitute_immediate(operand[self.IMMEDIATE_ID])
@@ -318,12 +320,16 @@ class ParserAArch64v81(BaseParser):
offset = None if 'offset' not in memory_address else memory_address['offset'] offset = None if 'offset' not in memory_address else memory_address['offset']
base = None if 'base' not in memory_address else memory_address['base'] base = None if 'base' not in memory_address else memory_address['base']
index = None if 'index' not in memory_address else memory_address['index'] index = None if 'index' not in memory_address else memory_address['index']
scale = '1' scale = 1
if base is not None and 'name' in base and base['name'] == 'sp':
base['prefix'] = 'x'
if index is not None and 'name' in index and index['name'] == 'sp':
index['prefix'] = 'x'
valid_shift_ops = ['lsl', 'uxtw', 'sxtw'] valid_shift_ops = ['lsl', 'uxtw', 'sxtw']
if 'index' in memory_address: if 'index' in memory_address:
if 'shift' in memory_address['index']: if 'shift' in memory_address['index']:
if memory_address['index']['shift_op'].lower() in valid_shift_ops: if memory_address['index']['shift_op'].lower() in valid_shift_ops:
scale = str(2 ** int(memory_address['index']['shift']['value'])) scale = 2 ** int(memory_address['index']['shift']['value'])
new_dict = AttrDict({'offset': offset, 'base': base, 'index': index, 'scale': scale}) new_dict = AttrDict({'offset': offset, 'base': base, 'index': index, 'scale': scale})
if 'pre_indexed' in memory_address: if 'pre_indexed' in memory_address:
new_dict['pre_indexed'] = True new_dict['pre_indexed'] = True
@@ -331,6 +337,11 @@ class ParserAArch64v81(BaseParser):
new_dict['post_indexed'] = memory_address['post_indexed'] new_dict['post_indexed'] = memory_address['post_indexed']
return AttrDict({self.MEMORY_ID: new_dict}) return AttrDict({self.MEMORY_ID: new_dict})
def substitute_sp_register(self, register):
reg = register
reg['prefix'] = 'x'
return AttrDict({self.REGISTER_ID: reg})
def substitute_register_list(self, register_list): def substitute_register_list(self, register_list):
# Remove unnecessarily created dictionary entries during parsing # Remove unnecessarily created dictionary entries during parsing
vlist = [] vlist = []

2
osaca/parser/parser_x86att.py
View File

@@ -228,7 +228,7 @@ class ParserX86ATT(BaseParser):
offset = None if 'offset' not in memory_address else memory_address['offset'] offset = None if 'offset' not in memory_address else memory_address['offset']
base = None if 'base' not in memory_address else memory_address['base'] base = None if 'base' not in memory_address else memory_address['base']
index = None if 'index' not in memory_address else memory_address['index'] index = None if 'index' not in memory_address else memory_address['index']
scale = '1' if 'scale' not in memory_address else memory_address['scale'] scale = 1 if 'scale' not in memory_address else int(memory_address['scale'])
new_dict = AttrDict({'offset': offset, 'base': base, 'index': index, 'scale': scale}) new_dict = AttrDict({'offset': offset, 'base': base, 'index': index, 'scale': scale})
return AttrDict({self.MEMORY_ID: new_dict}) return AttrDict({self.MEMORY_ID: new_dict})

16
tests/test_parser_AArch64v81.py
View File

@@ -107,10 +107,10 @@ class TestParserAArch64v81(unittest.TestCase):
self.assertEqual(parsed_4.instruction, 'str') self.assertEqual(parsed_4.instruction, 'str')
self.assertIsNone(parsed_4.operands.destination[0].memory.offset) self.assertIsNone(parsed_4.operands.destination[0].memory.offset)
self.assertEqual(parsed_4.operands.destination[0].memory.base.name, 'sp') self.assertEqual(parsed_4.operands.destination[0].memory.base.name, 'sp')
self.assertIsNone(parsed_4.operands.destination[0].memory.base.prefix) self.assertEqual(parsed_4.operands.destination[0].memory.base.prefix, 'x')
self.assertEqual(parsed_4.operands.destination[0].memory.index.name, '1') self.assertEqual(parsed_4.operands.destination[0].memory.index.name, '1')
self.assertEqual(parsed_4.operands.destination[0].memory.index.prefix, 'x') self.assertEqual(parsed_4.operands.destination[0].memory.index.prefix, 'x')
self.assertEqual(parsed_4.operands.destination[0].memory.scale, '16') self.assertEqual(parsed_4.operands.destination[0].memory.scale, 16)
self.assertEqual(parsed_4.operands.source[0].register.name, '28') self.assertEqual(parsed_4.operands.source[0].register.name, '28')
self.assertEqual(parsed_4.operands.source[0].register.prefix, 'x') self.assertEqual(parsed_4.operands.source[0].register.prefix, 'x')
self.assertEqual(parsed_4.comment, '12.9') self.assertEqual(parsed_4.comment, '12.9')
@@ -125,7 +125,7 @@ class TestParserAArch64v81(unittest.TestCase):
self.assertEqual(parsed_5.operands.source[0].memory.base.name, '0') self.assertEqual(parsed_5.operands.source[0].memory.base.name, '0')
self.assertEqual(parsed_5.operands.source[0].memory.base.prefix, 'x') self.assertEqual(parsed_5.operands.source[0].memory.base.prefix, 'x')
self.assertIsNone(parsed_5.operands.source[0].memory.index) self.assertIsNone(parsed_5.operands.source[0].memory.index)
self.assertEqual(parsed_5.operands.source[0].memory.scale, '1') self.assertEqual(parsed_5.operands.source[0].memory.scale, 1)
self.assertEqual(parsed_6.instruction, 'adrp') self.assertEqual(parsed_6.instruction, 'adrp')
self.assertEqual(parsed_6.operands.destination[0].register.name, '0') self.assertEqual(parsed_6.operands.destination[0].register.name, '0')
@@ -181,7 +181,7 @@ class TestParserAArch64v81(unittest.TestCase):
'shift_op': 'sxtw', 'shift_op': 'sxtw',
'shift': {'value': '2'}, 'shift': {'value': '2'},
}, },
'scale': '4', 'scale': 4,
} }
} }
], ],
@@ -201,7 +201,7 @@ class TestParserAArch64v81(unittest.TestCase):
'offset': {'value': '2048'}, 'offset': {'value': '2048'},
'base': {'prefix': 'x', 'name': '26'}, 'base': {'prefix': 'x', 'name': '26'},
'index': None, 'index': None,
'scale': '1', 'scale': 1,
} }
} }
], ],
@@ -225,9 +225,9 @@ class TestParserAArch64v81(unittest.TestCase):
{ {
'memory': { 'memory': {
'offset': {'value': '-16'}, 'offset': {'value': '-16'},
'base': {'name': 'sp', 'prefix': None}, 'base': {'name': 'sp', 'prefix': 'x'},
'index': None, 'index': None,
'scale': '1', 'scale': 1,
'pre_indexed': True, 'pre_indexed': True,
} }
} }
@@ -247,7 +247,7 @@ class TestParserAArch64v81(unittest.TestCase):
'offset': None, 'offset': None,
'base': {'prefix': 'x', 'name': '11'}, 'base': {'prefix': 'x', 'name': '11'},
'index': None, 'index': None,
'scale': '1', 'scale': 1,
'post_indexed': {'value': '64'}, 'post_indexed': {'value': '64'},
} }
} }

8
tests/test_parser_x86att.py
View File

@@ -104,7 +104,7 @@ class TestParserX86ATT(unittest.TestCase):
self.assertEqual(parsed_4.operands.destination[0].memory.offset.value, '-4') self.assertEqual(parsed_4.operands.destination[0].memory.offset.value, '-4')
self.assertEqual(parsed_4.operands.destination[0].memory.base.name, 'rsp') self.assertEqual(parsed_4.operands.destination[0].memory.base.name, 'rsp')
self.assertEqual(parsed_4.operands.destination[0].memory.index.name, 'rax') self.assertEqual(parsed_4.operands.destination[0].memory.index.name, 'rax')
self.assertEqual(parsed_4.operands.destination[0].memory.scale, '8') self.assertEqual(parsed_4.operands.destination[0].memory.scale, 8)
self.assertEqual(parsed_4.operands.source[0].register.name, 'xmm4') self.assertEqual(parsed_4.operands.source[0].register.name, 'xmm4')
self.assertEqual(parsed_4.comment, '12.9') self.assertEqual(parsed_4.comment, '12.9')
@@ -112,14 +112,14 @@ class TestParserX86ATT(unittest.TestCase):
self.assertEqual(parsed_5.operands.destination[0].memory.offset.identifier.name, 'var') self.assertEqual(parsed_5.operands.destination[0].memory.offset.identifier.name, 'var')
self.assertIsNone(parsed_5.operands.destination[0].memory.base) self.assertIsNone(parsed_5.operands.destination[0].memory.base)
self.assertIsNone(parsed_5.operands.destination[0].memory.index) self.assertIsNone(parsed_5.operands.destination[0].memory.index)
self.assertEqual(parsed_5.operands.destination[0].memory.scale, '1') self.assertEqual(parsed_5.operands.destination[0].memory.scale, 1)
self.assertEqual(parsed_5.operands.source[0].register.name, 'ebx') self.assertEqual(parsed_5.operands.source[0].register.name, 'ebx')
self.assertEqual(parsed_6.instruction, 'lea') self.assertEqual(parsed_6.instruction, 'lea')
self.assertIsNone(parsed_6.operands.source[0].memory.offset) self.assertIsNone(parsed_6.operands.source[0].memory.offset)
self.assertIsNone(parsed_6.operands.source[0].memory.base) self.assertIsNone(parsed_6.operands.source[0].memory.base)
self.assertEqual(parsed_6.operands.source[0].memory.index.name, 'rax') self.assertEqual(parsed_6.operands.source[0].memory.index.name, 'rax')
self.assertEqual(parsed_6.operands.source[0].memory.scale, '8') self.assertEqual(parsed_6.operands.source[0].memory.scale, 8)
self.assertEqual(parsed_6.operands.destination[0].register.name, 'rbx') self.assertEqual(parsed_6.operands.destination[0].register.name, 'rbx')
self.assertEqual(parsed_7.operands.source[0].immediate.value, '0x1') self.assertEqual(parsed_7.operands.source[0].immediate.value, '0x1')
@@ -166,7 +166,7 @@ class TestParserX86ATT(unittest.TestCase):
'offset': {'value': '2'}, 'offset': {'value': '2'},
'base': {'name': 'rax'}, 'base': {'name': 'rax'},
'index': {'name': 'rax'}, 'index': {'name': 'rax'},
'scale': '1', 'scale': 1,
} }
} }
], ],