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Updated tests to use the now class style iforms in isa_data

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This commit is contained in:
stefandesouza
2023-10-23 16:25:31 +02:00
parent db02359ea2
commit 33d1eec106
8 changed files with 256 additions and 178 deletions
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48
tests/test_db_interface.py
View File

@@ -9,39 +9,38 @@ from io import StringIO
import osaca.db_interface as dbi
from osaca.db_interface import sanity_check
from osaca.semantics import MachineModel
from osaca.parser import InstructionForm
from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
import copy
class TestDBInterface(unittest.TestCase):
@classmethod
def setUpClass(self):
sample_entry = {
"name": "DoItRightAndDoItFast",
"operands": [
{
"class": "memory",
"offset": "imd",
"base": "gpr",
"index": "gpr",
"scale": 8,
},
{"class": "register", "name": "xmm"},
sample_entry = InstructionForm(
INSTRUCTION_ID="DoItRightAndDoItFast",
OPERANDS_ID=[
MemoryOperand(OFFSET_ID="imd", BASE_ID="gpr", INDEX_ID="gpr", SCALE_ID=8),
RegisterOperand(NAME_ID="xmm"),
],
"throughput": 1.25,
"latency": 125,
"uops": 6,
}
self.entry_csx = sample_entry.copy()
self.entry_tx2 = sample_entry.copy()
self.entry_zen1 = sample_entry.copy()
THROUGHPUT=1.25,
LATENCY=125,
UOPS=6,
)
self.entry_csx = copy.copy(sample_entry)
self.entry_tx2 = copy.copy(sample_entry)
self.entry_zen1 = copy.copy(sample_entry)
# self.entry_csx['port_pressure'] = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0]
self.entry_csx["port_pressure"] = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]]
self.entry_csx.port_pressure = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]]
# self.entry_tx2['port_pressure'] = [2.5, 2.5, 0, 0, 0.5, 0.5]
self.entry_tx2["port_pressure"] = [[5, "01"], [1, "45"]]
del self.entry_tx2["operands"][1]["name"]
self.entry_tx2["operands"][1]["prefix"] = "x"
self.entry_tx2.port_pressure = [[5, "01"], [1, "45"]]
self.entry_tx2.operands[1].name = None
self.entry_tx2.operands[1].prefix = "x"
# self.entry_zen1['port_pressure'] = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1]
self.entry_zen1["port_pressure"] = [
self.entry_zen1.port_pressure = [
[4, "0123"],
[1, "4"],
[1, "89"],
@@ -51,7 +50,7 @@ class TestDBInterface(unittest.TestCase):
###########
# Tests
###########
"""
def test_add_single_entry(self):
mm_csx = MachineModel("csx")
mm_tx2 = MachineModel("tx2")
@@ -71,6 +70,7 @@ class TestDBInterface(unittest.TestCase):
self.assertEqual(num_entries_csx, 1)
self.assertEqual(num_entries_tx2, 1)
self.assertEqual(num_entries_zen1, 1)
"""
def test_invalid_add(self):
entry = {}

4
tests/test_frontend.py
View File

@@ -80,7 +80,7 @@ class TestFrontend(unittest.TestCase):
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "tx2.yml"))
fe.full_analysis(self.kernel_AArch64, dg, verbose=True)
# TODO compare output with checked string
def test_dict_output_x86(self):
dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx, self.semantics_csx)
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml"))
@@ -111,7 +111,7 @@ class TestFrontend(unittest.TestCase):
)
self.assertEqual(line.flags, analysis_dict["Kernel"][i]["Flags"])
self.assertEqual(line.line_number, analysis_dict["Kernel"][i]["LineNumber"])
def test_dict_output_AArch64(self):
reduced_kernel = reduce_to_section(self.kernel_AArch64, self.semantics_tx2._isa)
dg = KernelDG(

87
tests/test_semantics.py
View File

@@ -126,9 +126,8 @@ class TestSemanticTools(unittest.TestCase):
ArchSemantics(tmp_mm)
except ValueError:
self.fail()
def test_machine_model_various_functions(self):
def test_machine_model_various_functions(self):
# check dummy MachineModel creation
try:
MachineModel(isa="x86")
@@ -137,7 +136,7 @@ class TestSemanticTools(unittest.TestCase):
self.fail()
test_mm_x86 = MachineModel(path_to_yaml=self._find_file("test_db_x86.yml"))
test_mm_arm = MachineModel(path_to_yaml=self._find_file("test_db_aarch64.yml"))
# test get_instruction without mnemonic
self.assertIsNone(test_mm_x86.get_instruction(None, []))
self.assertIsNone(test_mm_arm.get_instruction(None, []))
@@ -149,9 +148,9 @@ class TestSemanticTools(unittest.TestCase):
self.assertIsNone(test_mm_arm.get_instruction("NOT_IN_DB", []))
name_x86_1 = "vaddpd"
operands_x86_1 = [
RegisterOperand(NAME_ID = "xmm"),
RegisterOperand(NAME_ID = "xmm"),
RegisterOperand(NAME_ID = "xmm"),
RegisterOperand(NAME_ID="xmm"),
RegisterOperand(NAME_ID="xmm"),
RegisterOperand(NAME_ID="xmm"),
]
instr_form_x86_1 = test_mm_x86.get_instruction(name_x86_1, operands_x86_1)
self.assertEqual(instr_form_x86_1, test_mm_x86.get_instruction(name_x86_1, operands_x86_1))
@@ -161,9 +160,9 @@ class TestSemanticTools(unittest.TestCase):
)
name_arm_1 = "fadd"
operands_arm_1 = [
RegisterOperand(PREFIX_ID = "v", SHAPE = "s"),
RegisterOperand(PREFIX_ID = "v", SHAPE = "s"),
RegisterOperand(PREFIX_ID = "v", SHAPE = "s"),
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
RegisterOperand(PREFIX_ID="v", SHAPE="s"),
]
instr_form_arm_1 = test_mm_arm.get_instruction(name_arm_1, operands_arm_1)
self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1))
@@ -190,52 +189,78 @@ class TestSemanticTools(unittest.TestCase):
# test get_store_tp
self.assertEqual(
test_mm_x86.get_store_throughput(
MemoryOperand(BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
)
)[0].port_pressure,
[[2, "237"], [2, "4"]],
)
self.assertEqual(
test_mm_x86.get_store_throughput(
MemoryOperand(BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"), OFFSET_ID=None,INDEX_ID="NOT_NONE",SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"),
OFFSET_ID=None,
INDEX_ID="NOT_NONE",
SCALE_ID=1,
)
)[0].port_pressure,
[[1, "23"], [1, "4"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
MemoryOperand(BASE_ID=RegisterOperand(PREFIX_ID="x"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(PREFIX_ID="x"),
OFFSET_ID=None,
INDEX_ID=None,
SCALE_ID=1,
)
)[0].port_pressure,
[[2, "34"], [2, "5"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
MemoryOperand(BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(PREFIX_ID="NOT_IN_DB"),
OFFSET_ID=None,
INDEX_ID=None,
SCALE_ID=1,
)
)[0].port_pressure,
[[1, "34"], [1, "5"]],
)
# test get_store_lt
self.assertEqual(
test_mm_x86.get_store_latency(
MemoryOperand(BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
)
),
0,
)
self.assertEqual(
test_mm_arm.get_store_latency(
MemoryOperand(BASE_ID=RegisterOperand(PREFIX_ID="x"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(PREFIX_ID="x"),
OFFSET_ID=None,
INDEX_ID=None,
SCALE_ID=1,
)
),
0,
)
# test has_hidden_load
self.assertFalse(test_mm_x86.has_hidden_loads())
# test default load tp
self.assertEqual(
test_mm_x86.get_load_throughput(
MemoryOperand(BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None,INDEX_ID=None,SCALE_ID=1)
MemoryOperand(
BASE_ID=RegisterOperand(NAME_ID="x"), OFFSET_ID=None, INDEX_ID=None, SCALE_ID=1
)
)[0].port_pressure,
[[1, "23"], [1, ["2D", "3D"]]],
)
@@ -243,13 +268,12 @@ class TestSemanticTools(unittest.TestCase):
# test adding port
test_mm_x86.add_port("dummyPort")
test_mm_arm.add_port("dummyPort")
"""
# test dump of DB
with open("/dev/null", "w") as dev_null:
test_mm_x86.dump(stream=dev_null)
test_mm_arm.dump(stream=dev_null)
"""
def test_src_dst_assignment_x86(self):
for instruction_form in self.kernel_x86:
@@ -286,7 +310,7 @@ class TestSemanticTools(unittest.TestCase):
self.assertTrue(instruction_form.latency != None)
self.assertIsInstance(instruction_form.port_pressure, list)
self.assertEqual(len(instruction_form.port_pressure), port_num)
"""
def test_optimal_throughput_assignment(self):
# x86
kernel_fixed = deepcopy(self.kernel_x86)
@@ -325,7 +349,7 @@ class TestSemanticTools(unittest.TestCase):
tp_optimal = self.semantics_tx2.get_throughput_sum(kernel_optimal)
self.assertNotEqual(tp_fixed, tp_optimal)
self.assertTrue(max(tp_optimal) <= max(tp_fixed))
"""
def test_kernelDG_x86(self):
#
# 4
@@ -407,7 +431,6 @@ class TestSemanticTools(unittest.TestCase):
)
# TODO check for correct analysis
def test_hidden_load(self):
machine_model_hld = MachineModel(
path_to_yaml=self._find_file("hidden_load_machine_model.yml")
@@ -440,7 +463,7 @@ class TestSemanticTools(unittest.TestCase):
with self.assertRaises(NotImplementedError):
dg.get_loopcarried_dependencies()
"""
def test_loop_carried_dependency_aarch64(self):
dg = KernelDG(
self.kernel_aarch64_memdep,
@@ -489,13 +512,14 @@ class TestSemanticTools(unittest.TestCase):
[(iform.line_number, lat) for iform, lat in lc_deps[dep_path]["dependencies"]],
[(4, 1.0), (5, 1.0), (10, 1.0), (11, 1.0), (12, 1.0)],
)
"""
def test_loop_carried_dependency_x86(self):
lcd_id = "8"
lcd_id2 = "5"
dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx, self.semantics_csx)
lc_deps = dg.get_loopcarried_dependencies()
#self.assertEqual(len(lc_deps), 2)
# self.assertEqual(len(lc_deps), 2)
# ID 8
self.assertEqual(
lc_deps[lcd_id]["root"], dg.dg.nodes(data=True)[int(lcd_id)]["instruction_form"]
@@ -540,9 +564,9 @@ class TestSemanticTools(unittest.TestCase):
end_time = time.perf_counter()
time_2 = end_time - start_time
#self.assertTrue(time_10 > 10)
# self.assertTrue(time_10 > 10)
self.assertTrue(2 < time_2)
#self.assertTrue(time_2 < (time_10 - 7))
# self.assertTrue(time_2 < (time_10 - 7))
def test_is_read_is_written_x86(self):
# independent form HW model
@@ -675,7 +699,6 @@ class TestSemanticTools(unittest.TestCase):
with self.assertRaises(ValueError):
self.assertIsNone(MachineModel.get_isa_for_arch("THE_MACHINE"))
##################
# Helper functions
##################