Lerking/OSACA
1
0
Fork 0
mirror of https://github.com/RRZE-HPC/OSACA.git synced 2026-01-04 18:20:09 +01:00
Code Issues Packages Projects Releases Wiki Activity

initial support Neoverse V2

Browse Source
This commit is contained in:
JanLJL
2024-03-04 20:45:48 +01:00
parent a2b40b9d2c
commit 3435641451
4 changed files with 4662 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
README.rst
View File

@@ -101,7 +101,7 @@ The usage of OSACA can be listed as:
--arch ARCH --arch ARCH
needs to be replaced with the target architecture abbreviation. needs to be replaced with the target architecture abbreviation.
Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures. Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures.
Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available. Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, ``M1`` for the Apple M1-Firestorm performance core, and ``V2`` for the Neoverse V2 (used in NVIDIA's Grace CPU) are available.
If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64. If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64.
--fixed --fixed
Run the throughput analysis with fixed port utilization for all suitable ports per instruction. Run the throughput analysis with fixed port utilization for all suitable ports per instruction.
@@ -142,49 +142,53 @@ Supported microarchitectures
----------------------------- -----------------------------
**x86 CPUs** **x86 CPUs**
+---------+----------------+------------+ +----------+----------------+------------+
|Designer | Model/microarch| OSACA flag | | Designer | Model/microarch| OSACA flag |
+=========+================+============+ +==========+================+============+
| | | Sandy Bridge | ``SNB`` | | | | Sandy Bridge | ``SNB`` |
| | +----------------+------------+ | | +----------------+------------+
| | | Ivy Bridge | ``IVB`` | | | | Ivy Bridge | ``IVB`` |
| | +----------------+------------+ | | +----------------+------------+
| | | Haswell | ``HSW`` | | | | Haswell | ``HSW`` |
| | Intel +----------------+------------+ | | Intel +----------------+------------+
| | | Broadwell | ``BDW`` | | | | Broadwell | ``BDW`` |
| +----------------+------------+ | +----------------+------------+
| | Skylake-X | ``SKX`` | | | Skylake-X | ``SKX`` |
| +----------------+------------+ | +----------------+------------+
| | Cascadelake-X | ``CSX`` | | | Cascadelake-X | ``CSX`` |
| +----------------+------------+ | +----------------+------------+
| | Icelake client | ``ICL`` | | | Icelake client | ``ICL`` |
| +----------------+------------+ | +----------------+------------+
| | Icelake server | ``ICX`` | | | Icelake server | ``ICX`` |
+---------+----------------+------------+ +----------+----------------+------------+
| | | Naples / Zen 1 | ``ZEN1`` | | | | Naples / Zen 1 | ``ZEN1`` |
| +----------------+------------+ | +----------------+------------+
| | AMD | Rome / Zen 2 | ``ZEN2`` | | | AMD | Rome / Zen 2 | ``ZEN2`` |
| +----------------+------------+ | +----------------+------------+
| | | Milan / Zen 3 | ``ZEN3`` | | | | Milan / Zen 3 | ``ZEN3`` |
+---------+----------------+------------+ +----------+----------------+------------+
**ARM AArch64 CPUs** **ARM AArch64 CPUs**
+---------+----------------+------------+ +-----------+-------------------+-------------+
|Designer | Model/microarch| OSACA flag | | Designer | Model/microarch | OSACA flag |
+=========+================+============+ +===========+===================+=============+
| | | Cortex-A72 | ``A72`` | | | | Cortex-A72 | ``A72`` |
| +----------------+------------+ | +-------------------+-------------+
| | ARM | Neoverse N1 | ``N1`` | | | ARM | Neoverse N1 | ``N1`` |
+---------+----------------+------------+ | +-------------------+-------------+
| Marvell | ThunderX2 | ``TX2`` | | | | Neoverse V2 | ``V2`` |
+---------+----------------+------------+ +-----------+-------------------+-------------+
| Fujitsu | FX700/A64FX | ``A64FX`` | | Marvell | ThunderX2 | ``TX2`` |
+---------+----------------+------------+ +-----------+-------------------+-------------+
|HiSilicon| TaiShan v110 | ``TSV110``| | Fujitsu | FX700/A64FX | ``A64FX`` |
+---------+----------------+------------+ +-----------+-------------------+-------------+
| Apple | M1-Firestorm | ``M1`` | | HiSilicon | TaiShan v110 | ``TSV110`` |
+---------+----------------+------------+ +-----------+-------------------+-------------+
| Apple | M1-Firestorm | ``M1`` |
+-----------+-------------------+-------------+
| NVIDIA | Neoverse V2/Grace | ``V2`` |
+-----------+-------------------+-------------+
______________________ ______________________

4613
osaca/data/v2.yml Normal file
View File

File diff suppressed because it is too large Load Diff

4
osaca/osaca.py
View File

@@ -39,6 +39,7 @@ SUPPORTED_ARCHS = [
"TSV110", "TSV110",
"A72", "A72",
"M1", "M1",
"V2",
] ]
DEFAULT_ARCHS = { DEFAULT_ARCHS = {
"aarch64": "A64FX", "aarch64": "A64FX",
@@ -102,7 +103,8 @@ def create_parser(parser=None):
"--arch", "--arch",
type=str, type=str,
help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, " help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, "
"A64FX, TSV110, A72, M1). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", "A64FX, TSV110, A72, M1, V2). If no architecture is given, OSACA assumes a default uarch for "
"x86/AArch64.",
) )
parser.add_argument( parser.add_argument(
"--fixed", "--fixed",

1
osaca/semantics/hw_model.py
View File

@@ -282,6 +282,7 @@ class MachineModel(object):
"tx2": "aarch64", "tx2": "aarch64",
"n1": "aarch64", "n1": "aarch64",
"m1": "aarch64", "m1": "aarch64",
"v2": "aarch64",
"zen1": "x86", "zen1": "x86",
"zen+": "x86", "zen+": "x86",
"zen2": "x86", "zen2": "x86",