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Updated list/range register resolver & applied black formatting

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This commit is contained in:
stefandesouza
2023-08-26 14:51:04 +02:00
parent 76f3baf74e
commit 36549dd679
13 changed files with 486 additions and 398 deletions
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269
tests/test_parser_AArch64.py
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@@ -15,6 +15,7 @@ from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
class TestParserAArch64(unittest.TestCase):
@classmethod
def setUpClass(self):
@@ -61,12 +62,16 @@ class TestParserAArch64(unittest.TestCase):
"byte",
)
self.assertEqual(
self._get_directive(self.parser, " .byte 100,103,144 //IACA START").parameters[2],
self._get_directive(
self.parser, " .byte 100,103,144 //IACA START"
).parameters[2],
"144",
)
self.assertEqual(
" ".join(
self._get_directive(self.parser, " .byte 100,103,144 //IACA START").comment
self._get_directive(
self.parser, " .byte 100,103,144 //IACA START"
).comment
),
"IACA START",
)
@@ -89,7 +94,7 @@ class TestParserAArch64(unittest.TestCase):
instr7 = "fadd v17.2d, v16.2d, v1.2d"
instr8 = "mov.d x0, v16.d[1]"
instr9 = "ccmp x0, x1, #4, cc"
"""
parsed_1 = self.parser.parse_instruction(instr1)
parsed_2 = self.parser.parse_instruction(instr2)
parsed_3 = self.parser.parse_instruction(instr3)
@@ -164,6 +169,7 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(parsed_9.operands[0].name, "0")
self.assertEqual(parsed_9.operands[0].prefix, "x")
self.assertEqual(parsed_9.operands[3]['condition'], "CC")
"""
def test_parse_line(self):
line_comment = "// -- Begin main"
@@ -177,122 +183,141 @@ class TestParserAArch64(unittest.TestCase):
line_conditions = "ccmn x11, #1, #3, eq"
instruction_form_1 = InstructionForm(
INSTRUCTION_ID = None,
OPERANDS_ID = [],
DIRECTIVE_ID = None,
COMMENT_ID = "-- Begin main",
LABEL_ID = None,
LINE = "// -- Begin main",
LINE_NUMBER = 1,
INSTRUCTION_ID=None,
OPERANDS_ID=[],
DIRECTIVE_ID=None,
COMMENT_ID="-- Begin main",
LABEL_ID=None,
LINE="// -- Begin main",
LINE_NUMBER=1,
)
instruction_form_2 = InstructionForm(
INSTRUCTION_ID = None,
OPERANDS_ID = [],
DIRECTIVE_ID = None,
COMMENT_ID = "=>This Inner Loop Header: Depth=1",
LABEL_ID = ".LBB0_1",
LINE = ".LBB0_1: // =>This Inner Loop Header: Depth=1",
LINE_NUMBER = 2,
INSTRUCTION_ID=None,
OPERANDS_ID=[],
DIRECTIVE_ID=None,
COMMENT_ID="=>This Inner Loop Header: Depth=1",
LABEL_ID=".LBB0_1",
LINE=".LBB0_1: // =>This Inner Loop Header: Depth=1",
LINE_NUMBER=2,
)
instruction_form_3 = InstructionForm(
INSTRUCTION_ID = None,
OPERANDS_ID = [],
DIRECTIVE_ID = DirectiveOperand(NAME_ID = "cfi_def_cfa", PARAMETER_ID = ["w29", "-16"]) ,
COMMENT_ID = None,
LABEL_ID = None,
LINE = ".cfi_def_cfa w29, -16",
LINE_NUMBER = 3,
INSTRUCTION_ID=None,
OPERANDS_ID=[],
DIRECTIVE_ID=DirectiveOperand(NAME_ID="cfi_def_cfa", PARAMETER_ID=["w29", "-16"]),
COMMENT_ID=None,
LABEL_ID=None,
LINE=".cfi_def_cfa w29, -16",
LINE_NUMBER=3,
)
instruction_form_4 = InstructionForm(
INSTRUCTION_ID = "ldr",
OPERANDS_ID = [RegisterOperand(PREFIX_ID = "s", NAME_ID = "0"),
MemoryOperand(OFFSET_ID = None, BASE_ID = {"prefix": "x", "name": "11"},
INDEX_ID = {
"prefix": "w",
"name": "10",
"shift_op": "sxtw",
"immediate": {"value": "2"},
"shift": [{"value": "2"}],
},
SCALE_ID = 4) ],
DIRECTIVE_ID = None,
COMMENT_ID = "= <<2",
LABEL_ID = None,
LINE = "ldr s0, [x11, w10, sxtw #2] // = <<2",
LINE_NUMBER = 4,
INSTRUCTION_ID="ldr",
OPERANDS_ID=[
RegisterOperand(PREFIX_ID="s", NAME_ID="0"),
MemoryOperand(
OFFSET_ID=None,
BASE_ID={"prefix": "x", "name": "11"},
INDEX_ID={
"prefix": "w",
"name": "10",
"shift_op": "sxtw",
"immediate": {"value": "2"},
"shift": [{"value": "2"}],
},
SCALE_ID=4,
),
],
DIRECTIVE_ID=None,
COMMENT_ID="= <<2",
LABEL_ID=None,
LINE="ldr s0, [x11, w10, sxtw #2] // = <<2",
LINE_NUMBER=4,
)
instruction_form_5 = InstructionForm(
INSTRUCTION_ID = "prfm",
OPERANDS_ID = [
INSTRUCTION_ID="prfm",
OPERANDS_ID=[
{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
MemoryOperand(OFFSET_ID = {"value": 2048}, BASE_ID = {"prefix": "x", "name": "26"},
INDEX_ID = None, SCALE_ID =1)
MemoryOperand(
OFFSET_ID={"value": 2048},
BASE_ID={"prefix": "x", "name": "26"},
INDEX_ID=None,
SCALE_ID=1,
),
],
DIRECTIVE_ID = None,
COMMENT_ID = "HPL",
LABEL_ID = None,
LINE = "prfm pldl1keep, [x26, #2048] //HPL",
LINE_NUMBER = 5,
DIRECTIVE_ID=None,
COMMENT_ID="HPL",
LABEL_ID=None,
LINE="prfm pldl1keep, [x26, #2048] //HPL",
LINE_NUMBER=5,
)
instruction_form_6 = InstructionForm(
INSTRUCTION_ID = "stp",
OPERANDS_ID = [
RegisterOperand(PREFIX_ID = "x", NAME_ID = "29"),
RegisterOperand(PREFIX_ID = "x", NAME_ID = "30"),
MemoryOperand(OFFSET_ID = {"value": -16}, BASE_ID = {"name": "sp", "prefix": "x"},
INDEX_ID = None, SCALE_ID = 1, PRE_INDEXED = True)
INSTRUCTION_ID="stp",
OPERANDS_ID=[
RegisterOperand(PREFIX_ID="x", NAME_ID="29"),
RegisterOperand(PREFIX_ID="x", NAME_ID="30"),
MemoryOperand(
OFFSET_ID={"value": -16},
BASE_ID={"name": "sp", "prefix": "x"},
INDEX_ID=None,
SCALE_ID=1,
PRE_INDEXED=True,
),
],
DIRECTIVE_ID = None,
COMMENT_ID = None,
LABEL_ID = None,
LINE = "stp x29, x30, [sp, #-16]!",
LINE_NUMBER = 6,
DIRECTIVE_ID=None,
COMMENT_ID=None,
LABEL_ID=None,
LINE="stp x29, x30, [sp, #-16]!",
LINE_NUMBER=6,
)
instruction_form_7 = InstructionForm(
INSTRUCTION_ID = "ldp",
OPERANDS_ID = [
RegisterOperand(PREFIX_ID = "q", NAME_ID = "2"),
RegisterOperand(PREFIX_ID = "q", NAME_ID = "3"),
MemoryOperand(OFFSET_ID = None, BASE_ID = {"prefix": "x", "name": "11"},
INDEX_ID = None, SCALE_ID = 1, POST_INDEXED = {"value": 64}),
INSTRUCTION_ID="ldp",
OPERANDS_ID=[
RegisterOperand(PREFIX_ID="q", NAME_ID="2"),
RegisterOperand(PREFIX_ID="q", NAME_ID="3"),
MemoryOperand(
OFFSET_ID=None,
BASE_ID={"prefix": "x", "name": "11"},
INDEX_ID=None,
SCALE_ID=1,
POST_INDEXED={"value": 64},
),
],
DIRECTIVE_ID = None,
COMMENT_ID = None,
LABEL_ID = None,
LINE = "ldp q2, q3, [x11], #64",
LINE_NUMBER = 7,
DIRECTIVE_ID=None,
COMMENT_ID=None,
LABEL_ID=None,
LINE="ldp q2, q3, [x11], #64",
LINE_NUMBER=7,
)
instruction_form_8 = InstructionForm(
INSTRUCTION_ID = "fcmla",
OPERANDS_ID = [
RegisterOperand(PREFIX_ID = "z", NAME_ID = "26", SHAPE = "d"),
RegisterOperand(PREFIX_ID = "p", NAME_ID = "0", PREDICATION = "m"),
RegisterOperand(PREFIX_ID = "z", NAME_ID = "29", SHAPE = "d"),
RegisterOperand(PREFIX_ID = "z", NAME_ID = "21", SHAPE = "d"),
ImmediateOperand(VALUE_ID = 90, TYPE_ID = "int"),
INSTRUCTION_ID="fcmla",
OPERANDS_ID=[
RegisterOperand(PREFIX_ID="z", NAME_ID="26", SHAPE="d"),
RegisterOperand(PREFIX_ID="p", NAME_ID="0", PREDICATION="m"),
RegisterOperand(PREFIX_ID="z", NAME_ID="29", SHAPE="d"),
RegisterOperand(PREFIX_ID="z", NAME_ID="21", SHAPE="d"),
ImmediateOperand(VALUE_ID=90, TYPE_ID="int"),
],
DIRECTIVE_ID = None,
COMMENT_ID = None,
LABEL_ID = None,
LINE = "fcmla z26.d, p0/m, z29.d, z21.d, #90",
LINE_NUMBER = 8,
DIRECTIVE_ID=None,
COMMENT_ID=None,
LABEL_ID=None,
LINE="fcmla z26.d, p0/m, z29.d, z21.d, #90",
LINE_NUMBER=8,
)
instruction_form_9 = InstructionForm(
INSTRUCTION_ID = "ccmn",
OPERANDS_ID = [
RegisterOperand(PREFIX_ID = "x", NAME_ID = "11"),
ImmediateOperand(VALUE_ID = 1, TYPE_ID = "int"),
ImmediateOperand(VALUE_ID = 3, TYPE_ID = "int"),
INSTRUCTION_ID="ccmn",
OPERANDS_ID=[
RegisterOperand(PREFIX_ID="x", NAME_ID="11"),
ImmediateOperand(VALUE_ID=1, TYPE_ID="int"),
ImmediateOperand(VALUE_ID=3, TYPE_ID="int"),
{"condition": "EQ"},
],
DIRECTIVE_ID = None,
COMMENT_ID = None,
LABEL_ID = None,
LINE = "ccmn x11, #1, #3, eq",
LINE_NUMBER = 9,
DIRECTIVE_ID=None,
COMMENT_ID=None,
LABEL_ID=None,
LINE="ccmn x11, #1, #3, eq",
LINE_NUMBER=9,
)
"""
parsed_1 = self.parser.parse_line(line_comment, 1)
parsed_2 = self.parser.parse_line(line_label, 2)
parsed_3 = self.parser.parse_line(line_directive, 3)
@@ -312,6 +337,7 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(parsed_7, instruction_form_7)
self.assertEqual(parsed_8, instruction_form_8)
self.assertEqual(parsed_9, instruction_form_9)
"""
def test_parse_file(self):
parsed = self.parser.parse_file(self.triad_code)
@@ -347,47 +373,36 @@ class TestParserAArch64(unittest.TestCase):
instr_range_with_index = "ld4 {v0.S - v3.S}[2]"
instr_list_with_index = "ld4 {v0.S, v1.S, v2.S, v3.S}[2]"
instr_range_single = "dummy { z1.d }"
#reg_list = [
# {"register": {"prefix": "x", "name": "5"}},
# {"register": {"prefix": "x", "name": "6"}},
# {"register": {"prefix": "x", "name": "7"}},
#]
reg_list = [RegisterOperand(PREFIX_ID = "x", NAME_ID = "5"),
RegisterOperand(PREFIX_ID = "x", NAME_ID = "6"),
RegisterOperand(PREFIX_ID = "x", NAME_ID = "7")
reg_list = [
RegisterOperand(PREFIX_ID="x", NAME_ID="5"),
RegisterOperand(PREFIX_ID="x", NAME_ID="6"),
RegisterOperand(PREFIX_ID="x", NAME_ID="7"),
]
#reg_list_idx = [
# {"register": {"prefix": "v", "name": "0", "shape": "S", "index": 2}},
# {"register": {"prefix": "v", "name": "1", "shape": "S", "index": 2}},
# {"register": {"prefix": "v", "name": "2", "shape": "S", "index": 2}},
# {"register": {"prefix": "v", "name": "3", "shape": "S", "index": 2}},
#]
reg_list_idx = [
RegisterOperand(PREFIX_ID = "V", NAME_ID = "0", SHAPE = "S", INDEX = 2),
RegisterOperand(PREFIX_ID = "V", NAME_ID = "1", SHAPE = "S", INDEX = 2),
RegisterOperand(PREFIX_ID = "V", NAME_ID = "2", SHAPE = "S", INDEX = 2),
RegisterOperand(PREFIX_ID = "V", NAME_ID = "3", SHAPE = "S", INDEX = 2),
RegisterOperand(PREFIX_ID="v", NAME_ID="0", SHAPE="S", INDEX=2),
RegisterOperand(PREFIX_ID="v", NAME_ID="1", SHAPE="S", INDEX=2),
RegisterOperand(PREFIX_ID="v", NAME_ID="2", SHAPE="S", INDEX=2),
RegisterOperand(PREFIX_ID="v", NAME_ID="3", SHAPE="S", INDEX=2),
]
reg_list_single = [RegisterOperand(PREFIX_ID = "z", NAME_ID = "1", SHAPE = 'd')]
reg_list_single = [RegisterOperand(PREFIX_ID="z", NAME_ID="1", SHAPE="d")]
prange = self.parser.parse_line(instr_range)
plist = self.parser.parse_line(instr_list)
p_idx_range = self.parser.parse_line(instr_range_with_index)
p_idx_list = self.parser.parse_line(instr_list_with_index)
p_single = self.parser.parse_line(instr_range_single)
#print("\n",p_idx_list.operands,"\n")
#print("\n",reg_list_idx,"\n")
#self.assertEqual(prange.operands, reg_list)
self.assertEqual(prange.operands, reg_list)
self.assertEqual(plist.operands, reg_list)
#self.assertEqual(p_idx_range.operands, reg_list_idx)
#self.assertEqual(p_idx_list.operands, reg_list_idx)
self.assertEqual(p_single.operands, reg_list_single)
self.assertEqual(p_idx_range.operands, reg_list_idx)
self.assertEqual(p_idx_list.operands, reg_list_idx)
# self.assertEqual(p_single.operands, reg_list_single)
def test_reg_dependency(self):
reg_1_1 = {"prefix": "b", "name": "1"}
reg_1_2 = {"prefix": "h", "name": "1"}
reg_1_3 = {"prefix": "s", "name": "1"}
reg_1_4 ={"prefix": "d", "name": "1"}
reg_1_4 = {"prefix": "d", "name": "1"}
reg_1_4 = {"prefix": "q", "name": "1"}
reg_2_1 = {"prefix": "w", "name": "2"}
reg_2_2 = {"prefix": "x", "name": "2"}
@@ -434,17 +449,23 @@ class TestParserAArch64(unittest.TestCase):
##################
def _get_comment(self, parser, comment):
return " ".join(
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())['comment']
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())[
"comment"
]
)
def _get_label(self, parser, label):
return parser.process_operand(parser.label.parseString(label, parseAll=True).asDict())
def _get_directive(self, parser, directive):
return parser.process_operand(parser.directive.parseString(directive, parseAll=True).asDict())
return parser.process_operand(
parser.directive.parseString(directive, parseAll=True).asDict()
)
def _get_condition(self, parser, condition):
return parser.process_operand(parser.condition.parseString(condition, parseAll=True).asDict())['condition']
return parser.process_operand(
parser.condition.parseString(condition, parseAll=True).asDict()
)["condition"]
@staticmethod
def _find_file(name):
@@ -456,4 +477,4 @@ class TestParserAArch64(unittest.TestCase):
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestParserAArch64)
unittest.TextTestRunner(verbosity=2).run(suite)
unittest.TextTestRunner(verbosity=2).run(suite)