From 3b0dfc714181df59c539c2294fd6f2bc8ad1482b Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 16:33:22 +0800 Subject: [PATCH] formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers --- osaca/data/tsv110.yml | 1437 +++++++++++++++++++++-------------------- 1 file changed, 721 insertions(+), 716 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index c8b168f..8441557 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -41,21 +41,230 @@ instruction_forms: throughput: 0.3333 latency: 1.0 port_pressure: [[1, '012']] -# memory instructions: ldur (data from AArch64SchedTSV110.td) -- name: ldur +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench) +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench) +- name: sub operands: - class: register prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] throughput: 0.5 + uops: 1 +# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x latency: 4.0 - port_pressure: [[1, '67']] + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +# arithmetic instructions: fsub (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +# arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fmul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 40.0 + port_pressure: [[1, '45']] + throughput: 36.0 + uops: 1 +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 26.0 + port_pressure: [[1, '45']] + throughput: 22.0 + uops: 1 # arithmetic instructions: fmla (latency and throughput from ibench, port data missed) - name: fmla operands: @@ -72,23 +281,37 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: fdiv +- name: fmla operands: - class: register prefix: v - shape: s + shape: d - class: register prefix: v - shape: s + shape: d - class: register prefix: v - shape: s - latency: 26.0 - port_pressure: [[1, '45']] - throughput: 22.0 - uops: 1 + shape: d + latency: 5.0 + port_pressure: ~ + throughput: 1.322 + uops: ~ # arithmetic instructions: fsqrt (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 64.0 + uops: 1 - name: fsqrt operands: - class: register @@ -104,76 +327,7 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 34.0 uops: ~ -# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: fadd - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: add - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: immediate - imd: int - latency: 1 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -- name: fsub - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fmul - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: register - prefix: d - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 0.5 - uops: 1 -- name: fdiv - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 40.0 - port_pressure: [[1, '45']] - throughput: 36.0 - uops: 1 +# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: frecpe operands: - class: register @@ -186,19 +340,492 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.0 uops: 1 -# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: subs +- name: frecpe + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: mov + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: q + - class: register + prefix: q + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [2, '45'] + throughput: 0.667 + uops: 2 +# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) +- name: cmp operands: - class: register prefix: x - class: register prefix: x - - class: immediate - imd: int latency: 1.0 - port_pressure: [[1, '12']] + port_pressure: [1, '12'] throughput: 0.5 uops: 1 +- name: cmp + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: fmov + operands: + - class: register + prefix: s + - class: immediate + imd: int + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# memory instructions: ldur (data from AArch64SchedTSV110.td) + - name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: str (data from AArch64SchedTSV110.td) +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: ldur (data from AArch64SchedTSV110.td) +- name: ldur + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] # memory instructions: stur (data from AArch64SchedTSV110.td) - name: stur operands: @@ -215,154 +842,6 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 -# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) -- name: fmla - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 5.0 - port_pressure: ~ - throughput: 1.322 - uops: ~ -- name: mov - operands: - - class: register - prefix: w - - class: register - prefix: w - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: d - - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: q - - class: register - prefix: q - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: sub - operands: - - class: register - prefix: w - - class: register - prefix: w - - class: immediate - imd: int - latency: 1.0 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: dup - operands: - - class: register - prefix: d - - class: register - prefix: v - shape: d - latency: 2.0 - port_pressure: [2, '45'] - throughput: 0.667 - uops: 2 -# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: frecpe - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 3.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fmul - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fadd - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: register - prefix: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 0.5 - uops: 1 -- name: fsqrt - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 22.0 - port_pressure: [[1, '45']] - throughput: 64.0 - uops: 1 -# arithmetic instructions: adds (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: adds - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: immediate - imd: int - latency: 1.0 - port_pressure: [[1, '12']] - throughput: 0.5 - uops: 1 - name: stur operands: - class: register @@ -378,120 +857,6 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 -- name: fsub - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.321 - uops: 1 -- name: fmul - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: mul - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: register - prefix: x - latency: 4.0 - port_pressure: [[1, '3']] - throughput: 1.0 - uops: 1 -- name: fadd - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.321 - uops: 1 -- name: add - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: register - prefix: x - latency: 1 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -- name: mov - operands: - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) -- name: cmp - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 1.0 - port_pressure: [1, '12'] - throughput: 0.5 - uops: 1 -# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) -- name: fmov - operands: - - class: register - prefix: s - - class: immediate - imd: int - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: cmp - operands: - - class: register - prefix: w - - class: register - prefix: w - latency: 1.0 - port_pressure: [1, '12'] - throughput: 0.5 - uops: 1 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp operands: @@ -800,363 +1165,3 @@ instruction_forms: latency: 2.0 port_pressure: [[2, '67'], [1, '012']] uops: 3 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2