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stefandesouza
2023-09-12 12:45:28 +02:00
parent a8e5a6ad46
commit 42f96753c1
10 changed files with 200 additions and 152 deletions
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15
osaca/semantics/arch_semantics.py
View File

@@ -169,9 +169,7 @@ class ArchSemantics(ISASemantics):
if INSTR_FLAGS.HIDDEN_LD not in load_instr.flags
]
)
load = [instr for instr in kernel if instr.line_number == min_distance_load[1]][
0
]
load = [instr for instr in kernel if instr.line_number == min_distance_load[1]][0]
# Hide load
load.flags += [INSTR_FLAGS.HIDDEN_LD]
load.port_pressure = self._nullify_data_ports(load.port_pressure)
@@ -263,7 +261,7 @@ class ArchSemantics(ISASemantics):
operands.index(self._create_reg_wildcard())
]
)
#dummy_reg = {"class": "register", "name": reg_type}
# dummy_reg = {"class": "register", "name": reg_type}
dummy_reg = RegisterOperand(NAME_ID=reg_type)
data_port_pressure = [0.0 for _ in range(port_number)]
data_port_uops = []
@@ -274,14 +272,14 @@ class ArchSemantics(ISASemantics):
x
for x in instruction_form.semantic_operands["source"]
+ instruction_form.semantic_operands["src_dst"]
if isinstance(x,MemoryOperand)
if isinstance(x, MemoryOperand)
][0]
)
# if multiple options, choose based on reg type
data_port_uops = [
ldp.port_pressure
for ldp in load_perf_data
if ldp.dst!=None
if ldp.dst != None
and self._machine_model._check_operands(
dummy_reg, RegisterOperand(NAME_ID=ldp.dst)
)
@@ -305,7 +303,8 @@ class ArchSemantics(ISASemantics):
+ instruction_form.semantic_operands["src_dst"]
)
store_perf_data = self._machine_model.get_store_throughput(
[x for x in destinations if isinstance(x,MemoryOperand)][0], dummy_reg
[x for x in destinations if isinstance(x, MemoryOperand)][0],
dummy_reg,
)
st_data_port_uops = store_perf_data[0].port_pressure
@@ -454,7 +453,7 @@ class ArchSemantics(ISASemantics):
else:
register = RegisterOperand(NAME_ID=reg_type + reg_id)
elif self._isa == "aarch64":
register = RegisterOperand(NAME_ID=reg_id,PREFIX_ID=reg_type)
register = RegisterOperand(NAME_ID=reg_id, PREFIX_ID=reg_type)
return register
def _nullify_data_ports(self, port_pressure):

126
osaca/semantics/hw_model.py
View File

@@ -20,6 +20,7 @@ from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.identifier import IdentifierOperand
class MachineModel(object):
WILDCARD = "*"
INTERNAL_VERSION = 1 # increase whenever self._data format changes to invalidate cache!
@@ -102,32 +103,55 @@ class MachineModel(object):
self._data["instruction_forms_dict"] = defaultdict(list)
for iform in self._data["instruction_forms"]:
iform["name"] = iform["name"].upper()
if iform["operands"]!=[]:
new_operands =[]
if iform["operands"] != []:
new_operands = []
for o in iform["operands"]:
if o["class"] == "register":
new_operands.append(RegisterOperand(NAME_ID=o["name"] if "name" in o else None,
PREFIX_ID=o["prefix"] if "prefix" in o else None,
MASK=o["mask"] if "mask" in o else False)
)
new_operands.append(
RegisterOperand(
NAME_ID=o["name"] if "name" in o else None,
PREFIX_ID=o["prefix"] if "prefix" in o else None,
MASK=o["mask"] if "mask" in o else False,
)
)
elif o["class"] == "memory":
new_operands.append(MemoryOperand(BASE_ID=o["base"],
OFFSET_ID=o["offset"],
INDEX_ID=o["index"],
SCALE_ID=o["scale"])
)
new_operands.append(
MemoryOperand(
BASE_ID=o["base"],
OFFSET_ID=o["offset"],
INDEX_ID=o["index"],
SCALE_ID=o["scale"],
)
)
iform["operands"] = new_operands
self._data["instruction_forms_dict"][iform["name"]].append(iform)
new_throughputs =[]
if 'load_throughput' in self._data:
new_throughputs = []
if "load_throughput" in self._data:
for m in self._data["load_throughput"]:
new_throughputs.append(MemoryOperand(BASE_ID=m['base'],OFFSET_ID=m['offset'],SCALE_ID=m['scale'],INDEX_ID=m['index'],PORT_PRESSURE=m['port_pressure'],DST=m['dst'] if 'dst' in m else None))
new_throughputs.append(
MemoryOperand(
BASE_ID=m["base"],
OFFSET_ID=m["offset"],
SCALE_ID=m["scale"],
INDEX_ID=m["index"],
PORT_PRESSURE=m["port_pressure"],
DST=m["dst"] if "dst" in m else None,
)
)
self._data["load_throughput"] = new_throughputs
new_throughputs =[]
if 'store_throughput' in self._data:
new_throughputs = []
if "store_throughput" in self._data:
for m in self._data["store_throughput"]:
new_throughputs.append(MemoryOperand(BASE_ID=m['base'],OFFSET_ID=m['offset'],SCALE_ID=m['scale'],INDEX_ID=m['index'],PORT_PRESSURE=m['port_pressure']))
new_throughputs.append(
MemoryOperand(
BASE_ID=m["base"],
OFFSET_ID=m["offset"],
SCALE_ID=m["scale"],
INDEX_ID=m["index"],
PORT_PRESSURE=m["port_pressure"],
)
)
self._data["store_throughput"] = new_throughputs
self._data["internal_version"] = self.INTERNAL_VERSION
@@ -491,14 +515,16 @@ class MachineModel(object):
elif operand in "wxbhsdq":
return RegisterOperand(PREFIX_ID=operand)
elif operand.startswith("v"):
return RegisterOperand(PREFIX_ID="v",SHAPE=operand[1:2])
return RegisterOperand(PREFIX_ID="v", SHAPE=operand[1:2])
elif operand.startswith("m"):
return MemoryOperand(BASE_ID = "x" if "b" in operand else None,
OFFSET_ID = "imd" if "o" in operand else None,
INDEX_ID = "gpr" if "i" in operand else None,
SCALE_ID =8 if "s" in operand else 1,
PRE_INDEXED = True if "r" in operand else False,
POST_INDEXED = True if "p" in operand else False)
return MemoryOperand(
BASE_ID="x" if "b" in operand else None,
OFFSET_ID="imd" if "o" in operand else None,
INDEX_ID="gpr" if "i" in operand else None,
SCALE_ID=8 if "s" in operand else 1,
PRE_INDEXED=True if "r" in operand else False,
POST_INDEXED=True if "p" in operand else False,
)
else:
raise ValueError("Parameter {} is not a valid operand code".format(operand))
@@ -511,10 +537,12 @@ class MachineModel(object):
elif operand == "i":
return ImmediateOperand(TYPE_ID="int")
elif operand.startswith("m"):
return MemoryOperand(BASE_ID = "gpr" if "b" in operand else None,
OFFSET_ID = "imd" if "o" in operand else None,
INDEX_ID = "gpr" if "i" in operand else None,
SCALE_ID = 8 if "s" in operand else 1,)
return MemoryOperand(
BASE_ID="gpr" if "b" in operand else None,
OFFSET_ID="imd" if "o" in operand else None,
INDEX_ID="gpr" if "i" in operand else None,
SCALE_ID=8 if "s" in operand else 1,
)
else:
raise ValueError("Parameter {} is not a valid operand code".format(operand))
@@ -553,10 +581,10 @@ class MachineModel(object):
def _check_operands(self, i_operand, operand):
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
# check for wildcard
if (isinstance(operand, Operand) and operand.name == self.WILDCARD) or (not isinstance(operand, Operand) and self.WILDCARD in operand):
if (
isinstance(i_operand, RegisterOperand)
):
if (isinstance(operand, Operand) and operand.name == self.WILDCARD) or (
not isinstance(operand, Operand) and self.WILDCARD in operand
):
if isinstance(i_operand, RegisterOperand):
return True
else:
return False
@@ -626,8 +654,8 @@ class MachineModel(object):
def _check_x86_operands(self, i_operand, operand):
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
#if "class" in operand.name:
# compare two DB entries
# if "class" in operand.name:
# compare two DB entries
# return self._compare_db_entries(i_operand, operand)
# register
if isinstance(operand, RegisterOperand):
@@ -641,7 +669,7 @@ class MachineModel(object):
return self._is_x86_mem_type(i_operand, operand)
# immediate
if isinstance(operand, ImmediateOperand):
#if "immediate" in operand.name or operand.value != None:
# if "immediate" in operand.name or operand.value != None:
return i_operand["class"] == "immediate" and i_operand["imd"] == "int"
# identifier (e.g., labels)
if isinstance(operand, IdentifierOperand):
@@ -733,10 +761,7 @@ class MachineModel(object):
# one instruction is missing zeroing while the other has it
zero_ok = False
# check for wildcard
if (
i_reg.zeroing == self.WILDCARD
or reg.zeroing == self.WILDCARD
):
if i_reg.zeroing == self.WILDCARD or reg.zeroing == self.WILDCARD:
zero_ok = True
if not mask_ok or not zero_ok:
return False
@@ -766,11 +791,7 @@ class MachineModel(object):
and "identifier" in mem.offset
and i_mem.offset == "identifier"
)
or (
mem.offset is not None
and "value" in mem.offset
and i_mem.offset == "imd"
)
or (mem.offset is not None and "value" in mem.offset and i_mem.offset == "imd")
)
# check index
and (
@@ -778,7 +799,7 @@ class MachineModel(object):
or i_mem.index == self.WILDCARD
or (
mem.index is not None
and mem["index"].prefix!=None
and mem["index"].prefix != None
and mem.index["prefix"] == i_mem.index
)
)
@@ -790,13 +811,12 @@ class MachineModel(object):
)
# check pre-indexing
and (
i_mem.pre-indexed == self.WILDCARD
or (mempre-indexed) == (i_mem.pre-indexed)
i_mem.pre - indexed == self.WILDCARD or (mempre - indexed) == (i_mem.pre - indexed)
)
# check post-indexing
and (
i_mem.post-indexed == self.WILDCARD
or (mem.post-indexed) == (i_mem.post-indexed)
i_mem.post - indexed == self.WILDCARD
or (mem.post - indexed) == (i_mem.post - indexed)
)
):
return True
@@ -828,11 +848,7 @@ class MachineModel(object):
or (i_mem.offset is None and mem.offset["value"] == "0")
)
)
or (
mem.offset is not None
and "identifier" in mem.offset
and i_mem.offset == "id"
)
or (mem.offset is not None and "identifier" in mem.offset and i_mem.offset == "id")
)
# check index
and (
@@ -840,7 +856,7 @@ class MachineModel(object):
or i_mem.index == self.WILDCARD
or (
mem.index is not None
and mem.index.name!=None
and mem.index.name != None
and self._is_x86_reg_type(i_mem.index, mem.index)
)
)

8
osaca/semantics/isa_semantics.py
View File

@@ -182,7 +182,7 @@ class ISASemantics(object):
isa_data = self._isa_model.get_instruction(
instruction_form.instruction[:suffix_start], instruction_form.operands
)
'''
"""
if only_postindexed:
for o in instruction_form.operands:
if isinstance(o, MemoryOperand) and o.base!=None:
@@ -194,7 +194,7 @@ class ISASemantics(object):
}
}
return {}
'''
"""
reg_operand_names = {} # e.g., {'rax': 'op1'}
operand_state = {} # e.g., {'op1': {'name': 'rax', 'value': 0}} 0 means unchanged
@@ -206,7 +206,7 @@ class ISASemantics(object):
"ISA information for pre-indexed instruction {!r} has operation set."
"This is currently not supprted.".format(instruction_form.line)
)
base_name = o.base.prefix if o.base.prefix!=None else "" + o.base.name
base_name = o.base.prefix if o.base.prefix != None else "" + o.base.name
reg_operand_names = {base_name: "op1"}
operand_state = {"op1": {"name": base_name, "value": o.offset["value"]}}
@@ -214,7 +214,7 @@ class ISASemantics(object):
for i, o in enumerate(instruction_form.operands):
operand_name = "op{}".format(i + 1)
if isinstance(o, RegisterOperand):
o_reg_name = o.prefix if o.prefix!=None else "" + o.name
o_reg_name = o.prefix if o.prefix != None else "" + o.name
reg_operand_names[o_reg_name] = operand_name
operand_state[operand_name] = {"name": o_reg_name, "value": 0}
elif "immediate" in o:

28
osaca/semantics/kernel_dg.py
View File

@@ -13,6 +13,7 @@ from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
class KernelDG(nx.DiGraph):
# threshold for checking dependency graph sequential or in parallel
INSTRUCTION_THRESHOLD = 50
@@ -285,9 +286,9 @@ class KernelDG(nx.DiGraph):
if isinstance(dst, RegisterOperand):
# read of register
if self.is_read(dst, instr_form):
#if dst.pre_indexed or dst.post_indexed:
#yield instr_form, ["p_indexed"]
#else:
# if dst.pre_indexed or dst.post_indexed:
# yield instr_form, ["p_indexed"]
# else:
yield instr_form, []
# write to register -> abort
if self.is_written(dst, instr_form):
@@ -410,7 +411,7 @@ class KernelDG(nx.DiGraph):
# Here we check for mem dependecies only
if not isinstance(src, MemoryOperand):
continue
#src = src.memory
# src = src.memory
# determine absolute address change
addr_change = 0
@@ -420,13 +421,20 @@ class KernelDG(nx.DiGraph):
addr_change -= mem.offset["value"]
if mem.base and src.base:
base_change = register_changes.get(
src.base.prefix if src.base.prefix!=None else "" + src.base.name,
{"name": src.base.prefix if src.base.prefix!=None else "" + src.base.name, "value": 0},
src.base.prefix if src.base.prefix != None else "" + src.base.name,
{
"name": src.base.prefix if src.base.prefix != None else "" + src.base.name,
"value": 0,
},
)
if base_change is None:
# Unknown change occurred
continue
if mem.base.prefix if mem.base.prefix!=None else "" + mem.base.name != base_change["name"]:
if (
mem.base.prefix
if mem.base.prefix != None
else "" + mem.base.name != base_change["name"]
):
# base registers do not match
continue
addr_change += base_change["value"]
@@ -444,7 +452,11 @@ class KernelDG(nx.DiGraph):
if mem.scale != src.scale:
# scale factors do not match
continue
if mem.index.prefix if mem.index.prefix!=None else "" + mem.index.name != index_change["name"]:
if (
mem.index.prefix
if mem.index.prefix != None
else "" + mem.index.name != index_change["name"]
):
# index registers do not match
continue
addr_change += index_change["value"] * src.scale