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add some instructions for tsv110

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Qingcai Jiang
2021-12-15 21:51:59 +08:00
parent a87c077654
commit 4e10491fcb
1 changed files with 241 additions and 0 deletions
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osaca/data/tsv110.yml
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@@ -42,6 +42,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: and
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: and
operands:
- class: register
@@ -54,6 +66,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: and
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: ands
operands:
@@ -67,6 +91,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '12']]
uops: 1
- name: ands
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.5
latency: 1.0
port_pressure: [[1, '12']]
uops: 1
- name: ands
operands:
- class: register
@@ -79,6 +115,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '12']]
uops: 1
- name: ands
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.5
latency: 1.0
port_pressure: [[1, '12']]
uops: 1
# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: orr
operands:
@@ -92,6 +140,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: orr
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: orr
operands:
- class: register
@@ -104,6 +164,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: orr
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: eor
operands:
@@ -117,6 +189,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: eor
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: eor
operands:
- class: register
@@ -129,6 +213,18 @@ instruction_forms:
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
- name: eor
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.3333
latency: 1.0
port_pressure: [[1, '012']]
uops: 1
# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
- name: bic
operands:
@@ -253,7 +349,73 @@ instruction_forms:
port_pressure: [[1, '012']]
throughput: 0.33333
uops: 1
- name: add
operands:
- class: register
prefix: v
shape: s
- class: register
prefix: v
shape: s
- class: register
prefix: v
shape: s
throughput: 0.5
latency: 2.0
port_pressure: [[1, '45']]
- name: add
operands:
- class: register
prefix: v
shape: d
- class: register
prefix: v
shape: d
- class: register
prefix: v
shape: d
throughput: 0.5
latency: 2.0
port_pressure: [[1, '45']]
- name: add
operands:
- class: register
prefix: v
shape: h
- class: register
prefix: v
shape: h
- class: register
prefix: v
shape: h
throughput: 0.5
latency: 2.0
port_pressure: [[1, '45']]
# arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench)
- name: adds
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: adds
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: adds
operands:
- class: register
@@ -266,6 +428,44 @@ instruction_forms:
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
- name: adds
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
latency: 1.0
port_pressure: [[1, '12']]
throughput: 0.5
uops: 1
# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
- name: adc
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
latency: 1.0
port_pressure: [[1, '012']]
throughput: 0.33333
uops: 1
# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench)
- name: adc
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
latency: 1.0
port_pressure: [[1, '012']]
throughput: 0.33333
uops: 1
# arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench)
- name: sub
operands:
@@ -894,6 +1094,47 @@ instruction_forms:
port_pressure: [1, '12']
throughput: 0.5
uops: 1
- name: cmp
operands:
- class: register
prefix: x
- class: immediate
imd: int
latency: 1.0
port_pressure: [1, '12']
throughput: 0.5
uops: 1
- name: cmp
operands:
- class: register
prefix: w
- class: immediate
imd: int
latency: 1.0
port_pressure: [1, '12']
throughput: 0.5
uops: 1
# miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: dup
operands:
- class: register
prefix: v
shape: d
- class: register
prefix: x
throughput: 0.667
latency: 2.0
port_pressure: [[1, '5']]
- name: dup
operands:
- class: register
prefix: v
shape: s
- class: register
prefix: w
throughput: 0.667
latency: 2.0
port_pressure: [[1, '5']]
# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td)
- name: zip1
operands: