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added support for <Xd>! registers and [<Xd>]! mem addresses in Arm

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This commit is contained in:
JanLJL
2025-03-07 11:49:14 +01:00
parent 785a365c63
commit 4e3994fec1
5 changed files with 97 additions and 5 deletions
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11
osaca/parser/parser_AArch64.py
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@@ -124,16 +124,18 @@ class ParserAArch64(BaseParser):
+ pp.Optional(immediate).setResultsName("shift")
).setResultsName(self.immediate_id)
# Register:
# scalar: [XWBHSDQ][0-9]{1,2} | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
# scalar: [XWBHSDQ][0-9]{1,2}! | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
# | predicate: P[0-9]{1,2}(/[ZM])?
# ignore vector len control ZCR_EL[123] for now
# define SP, ZR register aliases as regex, due to pyparsing does not support
# proper lookahead
alias_r31_sp = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(sp|SP))")
alias_r31_zr = pp.Regex("(?P<prefix>[a-zA-Z])?(?P<name>(zr|ZR))")
scalar = pp.Word("xwbhsdqXWBHSDQ", exact=1).setResultsName("prefix") + pp.Word(
pp.nums
).setResultsName("name")
scalar = (
pp.Word("xwbhsdqXWBHSDQ", exact=1).setResultsName("prefix")
+ pp.Word(pp.nums).setResultsName("name")
+ pp.Optional(pp.Literal("!")).setResultsName("pre_indexed")
)
index = pp.Literal("[") + pp.Word(pp.nums).setResultsName("index") + pp.Literal("]")
vector = (
pp.oneOf("v z", caseless=True).setResultsName("prefix")
@@ -417,6 +419,7 @@ class ParserAArch64(BaseParser):
lanes=operand["lanes"] if "lanes" in operand else None,
index=operand["index"] if "index" in operand else None,
predication=operand["predication"].lower() if "predication" in operand else None,
pre_indexed=True if "pre_indexed" in operand else False,
)
def process_memory_address(self, memory_address):