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added support for <Xd>! registers and [<Xd>]! mem addresses in Arm

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This commit is contained in:
JanLJL
2025-03-07 11:49:14 +01:00
parent 785a365c63
commit 4e3994fec1
5 changed files with 97 additions and 5 deletions
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9
tests/test_parser_AArch64.py
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@@ -23,6 +23,9 @@ class TestParserAArch64(unittest.TestCase):
self.parser = ParserAArch64()
with open(self._find_file("triad_arm_iaca.s")) as f:
self.triad_code = f.read()
with open(self._find_file("mops_aarch64.s")) as f:
self.mops_1_code = f.read()
self.mops_2_code = self.mops_1_code.replace("//ALT1 ", "")
##################
# Test
@@ -173,6 +176,12 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(parsed_9.operands[0].prefix, "x")
self.assertEqual(parsed_9.operands[3].ccode, "CC")
def test_mops(self):
parsed_1 = self.parser.parse_file(self.mops_1_code)
parsed_2 = self.parser.parse_file(self.mops_1_code)
self.assertEqual(len(parsed_1), 8)
self.assertEqual(len(parsed_2), 8)
def test_parse_line(self):
line_comment = "// -- Begin main"
line_label = ".LBB0_1: // =>This Inner Loop Header: Depth=1"