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stefandesouza
2024-03-05 12:14:05 +01:00
parent 18da151bbf
commit 4fd59eb0d0
14 changed files with 109 additions and 90 deletions
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6
osaca/parser/directive.py
View File

@@ -24,13 +24,9 @@ class DirectiveOperand(Operand):
def parameters(self, parameters):
self._parameters = parameters
def __eq__(self, other):
if isinstance(other, DirectiveOperand):
return (
self._name == other._name
and self._parameters == other._parameters
)
return self._name == other._name and self._parameters == other._parameters
elif isinstance(other, dict):
return self._name == other["name"] and self._parameters == other["parameters"]
return False

4
osaca/parser/flag.py
View File

@@ -17,9 +17,7 @@ class FlagOperand(Operand):
self._name = name
def __str__(self):
return (
f"Flag(name={self._name}, source={self._source}, relocation={self._destination})"
)
return f"Flag(name={self._name}, source={self._source}, relocation={self._destination})"
def __repr__(self):
return self.__str__()

20
osaca/parser/parser_AArch64.py
View File

@@ -392,10 +392,13 @@ class ParserAArch64(BaseParser):
return operand
def process_directive_operand(self, operand):
return DirectiveOperand(
return (
DirectiveOperand(
name=operand["name"],
parameters=operand["parameters"],
), operand["comment"] if "comment" in operand else None
),
operand["comment"] if "comment" in operand else None,
)
def process_register_operand(self, operand):
return RegisterOperand(
@@ -524,9 +527,7 @@ class ParserAArch64(BaseParser):
# normal integer value
immediate["type"] = "int"
# convert hex/bin immediates to dec
new_immediate = ImmediateOperand(
imd_type=immediate["type"], value=immediate["value"]
)
new_immediate = ImmediateOperand(imd_type=immediate["type"], value=immediate["value"])
new_immediate.value = self.normalize_imd(new_immediate)
return new_immediate
if "base_immediate" in immediate:
@@ -547,9 +548,7 @@ class ParserAArch64(BaseParser):
dict_name = "double"
if "exponent" in immediate[dict_name]:
immediate["type"] = dict_name
return ImmediateOperand(
imd_type=immediate["type"], value=immediate[immediate["type"]]
)
return ImmediateOperand(imd_type=immediate["type"], value=immediate[immediate["type"]])
else:
# change 'mantissa' key to 'value'
return ImmediateOperand(value=immediate[dict_name]["mantissa"], imd_type=dict_name)
@@ -557,7 +556,10 @@ class ParserAArch64(BaseParser):
def process_label(self, label):
"""Post-process label asm line"""
# remove duplicated 'name' level due to identifier
return LabelOperand(name=label["name"]["name"]), label["comment"] if self.comment_id in label else None
return (
LabelOperand(name=label["name"]["name"]),
label["comment"] if self.comment_id in label else None,
)
def process_identifier(self, identifier):
"""Post-process identifier operand"""

9
osaca/parser/parser_x86att.py
View File

@@ -317,7 +317,10 @@ class ParserX86ATT(BaseParser):
)
def process_directive(self, directive):
directive_new = DirectiveOperand(name=directive["name"], parameters=directive["parameters"] if "parameters" in directive else [])
directive_new = DirectiveOperand(
name=directive["name"],
parameters=directive["parameters"] if "parameters" in directive else [],
)
return directive_new, directive["comment"] if "comment" in directive else None
def process_memory_address(self, memory_address):
@@ -346,9 +349,7 @@ class ParserX86ATT(BaseParser):
)
if isinstance(offset, dict) and "identifier" in offset:
offset = IdentifierOperand(name=offset["identifier"]["name"])
new_dict = MemoryOperand(
offset=offset, base=baseOp, index=indexOp, scale=scale
)
new_dict = MemoryOperand(offset=offset, base=baseOp, index=indexOp, scale=scale)
# Add segmentation extension if existing
if self.segment_ext in memory_address:
new_dict.segment_ext = memory_address[self.segment_ext]

55
osaca/semantics/hw_model.py
View File

@@ -136,7 +136,9 @@ class MachineModel(object):
uops=iform["uops"] if "uops" in iform else None,
port_pressure=iform["port_pressure"] if "port_pressure" in iform else None,
operation=iform["operation"] if "operation" in iform else None,
breaks_dependency_on_equal_operands=iform["breaks_dependency_on_equal_operands"]
breaks_dependency_on_equal_operands=iform[
"breaks_dependency_on_equal_operands"
]
if "breaks_dependency_on_equal_operands" in iform
else False,
semantic_operands=iform["semantic_operands"]
@@ -151,33 +153,36 @@ class MachineModel(object):
new_throughputs = []
if "load_throughput" in self._data:
for m in self._data["load_throughput"]:
new_throughputs.append((
new_throughputs.append(
(
MemoryOperand(
base=m["base"],
offset=m["offset"],
scale=m["scale"],
index=m["index"],
dst=m["dst"] if "dst" in m else None,
),
m["port_pressure"],
)
, m["port_pressure"])
)
self._data["load_throughput"] = new_throughputs
new_throughputs = []
if "store_throughput" in self._data:
for m in self._data["store_throughput"]:
new_throughputs.append((
new_throughputs.append(
(
MemoryOperand(
base=m["base"],
offset=m["offset"],
scale=m["scale"],
index=m["index"],
),
m["port_pressure"],
)
, m["port_pressure"])
)
self._data["store_throughput"] = new_throughputs
if not lazy:
# cache internal representation for future use
self._write_in_cache(self._path)
@@ -386,12 +391,15 @@ class MachineModel(object):
def get_store_throughput(self, memory, src_reg=None):
"""Return store throughput for a given destination and register type."""
st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m[0])]
st_tp = [
m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m[0])
]
if src_reg is not None:
st_tp = [
tp
for tp in st_tp
if "src" in tp[0] and self._check_operands(src_reg, RegisterOperand(name=tp[0]["src"]))
if "src" in tp[0]
and self._check_operands(src_reg, RegisterOperand(name=tp[0]["src"]))
]
if len(st_tp) > 0:
return st_tp.copy()
@@ -465,25 +473,44 @@ class MachineModel(object):
def class_to_dict(self, op):
"""Need to convert operand classes to dicts for the dump. Memory operand types may have their index/base/offset as a register operand/"""
if isinstance(op, Operand):
dict_op = dict((key.lstrip('_'), value) for key, value in op.__dict__.items() if not callable(value) and not key.startswith('__'))
dict_op = dict(
(key.lstrip("_"), value)
for key, value in op.__dict__.items()
if not callable(value) and not key.startswith("__")
)
if isinstance(op, MemoryOperand):
if isinstance(dict_op["index"], Operand):
dict_op["index"] = dict((key.lstrip('_'), value) for key, value in dict_op["index"].__dict__.items() if not callable(value) and not key.startswith('__'))
dict_op["index"] = dict(
(key.lstrip("_"), value)
for key, value in dict_op["index"].__dict__.items()
if not callable(value) and not key.startswith("__")
)
if isinstance(dict_op["offset"], Operand):
dict_op["offset"] = dict((key.lstrip('_'), value) for key, value in dict_op["offset"].__dict__.items() if not callable(value) and not key.startswith('__'))
dict_op["offset"] = dict(
(key.lstrip("_"), value)
for key, value in dict_op["offset"].__dict__.items()
if not callable(value) and not key.startswith("__")
)
if isinstance(dict_op["base"], Operand):
dict_op["base"] = dict((key.lstrip('_'), value) for key, value in dict_op["base"].__dict__.items() if not callable(value) and not key.startswith('__'))
dict_op["base"] = dict(
(key.lstrip("_"), value)
for key, value in dict_op["base"].__dict__.items()
if not callable(value) and not key.startswith("__")
)
return dict_op
return op
def dump(self, stream=None):
"""Dump machine model to stream or return it as a ``str`` if no stream is given."""
# Replace instruction form's port_pressure with styled version for RoundtripDumper
formatted_instruction_forms = []
for instruction_form in self._data["instruction_forms"]:
if isinstance(instruction_form, InstructionForm):
instruction_form = dict((key.lstrip('_'), value) for key, value in instruction_form.__dict__.items() if not callable(value) and not key.startswith('__'))
instruction_form = dict(
(key.lstrip("_"), value)
for key, value in instruction_form.__dict__.items()
if not callable(value) and not key.startswith("__")
)
if instruction_form["port_pressure"] is not None:
cs = ruamel.yaml.comments.CommentedSeq(instruction_form["port_pressure"])
cs.fa.set_flow_style()

5
osaca/semantics/kernel_dg.py
View File

@@ -300,10 +300,7 @@ class KernelDG(nx.DiGraph):
# write to register -> abort
if self.is_written(dst, instr_form):
break
if (
isinstance(dst, FlagOperand)
and flag_dependencies
):
if isinstance(dst, FlagOperand) and flag_dependencies:
# read of flag
if self.is_read(dst, instr_form):
yield instr_form, []

18
tests/test_parser_AArch64.py
View File

@@ -53,25 +53,27 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text")
self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0)
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align")
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2)
self.assertEqual(
len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2
)
self.assertEqual(
self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90"
)
self.assertEqual(
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[0].name,
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
0
].name,
"byte",
)
self.assertEqual(
self._get_directive(
self.parser, " .byte 100,103,144 //IACA START"
)[0].parameters[2],
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
0
].parameters[2],
"144",
)
self.assertEqual(
" ".join(
self._get_directive(
self.parser, " .byte 100,103,144 //IACA START"
)[1]
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[1]
),
"IACA START",
)

24
tests/test_parser_x86att.py
View File

@@ -48,7 +48,9 @@ class TestParserX86ATT(unittest.TestCase):
self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text")
self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0)
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align")
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2)
self.assertEqual(
len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2
)
self.assertEqual(len(self._get_directive(self.parser, ".text")[0].parameters), 0)
self.assertEqual(
len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"')[0].parameters),
@@ -75,29 +77,29 @@ class TestParserX86ATT(unittest.TestCase):
],
)
self.assertEqual(
self._get_directive(
self.parser, "\t.section\t__TEXT,__literal16,16byte_literals"
)[0].parameters,
self._get_directive(self.parser, "\t.section\t__TEXT,__literal16,16byte_literals")[
0
].parameters,
["__TEXT", "__literal16", "16byte_literals"],
)
self.assertEqual(
self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90"
)
self.assertEqual(
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[0].name,
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[
0
].name,
"byte",
)
self.assertEqual(
self._get_directive(
self.parser, " .byte 100,103,144 #IACA START"
)[0].parameters[2],
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[
0
].parameters[2],
"144",
)
self.assertEqual(
" ".join(
self._get_directive(
self.parser, " .byte 100,103,144 #IACA START"
)[1]
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[1]
),
"IACA START",
)

12
tests/test_semantics.py
View File

@@ -189,9 +189,7 @@ class TestSemanticTools(unittest.TestCase):
# test get_store_tp
self.assertEqual(
test_mm_x86.get_store_throughput(
MemoryOperand(
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1)
)[0][1],
[[2, "237"], [2, "4"]],
)
@@ -235,9 +233,7 @@ class TestSemanticTools(unittest.TestCase):
# test get_store_lt
self.assertEqual(
test_mm_x86.get_store_latency(
MemoryOperand(
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1)
),
0,
)
@@ -259,9 +255,7 @@ class TestSemanticTools(unittest.TestCase):
# test default load tp
self.assertEqual(
test_mm_x86.get_load_throughput(
MemoryOperand(
base=RegisterOperand(name="x"), offset=None, index=None, scale=1
)
MemoryOperand(base=RegisterOperand(name="x"), offset=None, index=None, scale=1)
)[0][1],
[[1, "23"], [1, ["2D", "3D"]]],
)