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https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 18:50:08 +01:00
fixed formatting with correct line length
This commit is contained in:
JanLJL
@@ -54,9 +54,7 @@ class KernelDG(nx.DiGraph):
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dg = nx.DiGraph()
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for i, instruction_form in enumerate(kernel):
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dg.add_node(instruction_form["line_number"])
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dg.nodes[instruction_form["line_number"]][
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"instruction_form"
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] = instruction_form
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dg.nodes[instruction_form["line_number"]]["instruction_form"] = instruction_form
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# add load as separate node if existent
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if (
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INSTR_FLAGS.HAS_LD in instruction_form["flags"]
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@@ -71,16 +69,12 @@ class KernelDG(nx.DiGraph):
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dg.add_edge(
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instruction_form["line_number"] + 0.1,
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instruction_form["line_number"],
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latency=instruction_form["latency"]
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- instruction_form["latency_wo_load"],
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latency=instruction_form["latency"] - instruction_form["latency_wo_load"],
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)
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for dep, dep_flags in self.find_depending(
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instruction_form, kernel[i + 1 :]
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):
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for dep, dep_flags in self.find_depending(instruction_form, kernel[i + 1 :]):
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edge_weight = (
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instruction_form["latency"]
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if "mem_dep" in dep_flags
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or "latency_wo_load" not in instruction_form
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if "mem_dep" in dep_flags or "latency_wo_load" not in instruction_form
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else instruction_form["latency_wo_load"]
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)
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if "storeload_dep" in dep_flags:
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@@ -312,9 +306,7 @@ class KernelDG(nx.DiGraph):
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# store to same location (presumed)
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if self.is_memstore(dst.memory, instr_form, register_changes):
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break
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self._update_reg_changes(
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instr_form, register_changes, only_postindexed=True
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)
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self._update_reg_changes(instr_form, register_changes, only_postindexed=True)
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def _update_reg_changes(self, iform, reg_state=None, only_postindexed=False):
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if self.arch_sem is None:
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@@ -322,9 +314,7 @@ class KernelDG(nx.DiGraph):
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return {}
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if reg_state is None:
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reg_state = {}
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for reg, change in self.arch_sem.get_reg_changes(
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iform, only_postindexed
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).items():
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for reg, change in self.arch_sem.get_reg_changes(iform, only_postindexed).items():
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if change is None or reg_state.get(reg, {}) is None:
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reg_state[reg] = None
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else:
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@@ -362,23 +352,15 @@ class KernelDG(nx.DiGraph):
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instruction_form.semantic_operands.src_dst,
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):
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if "register" in src:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.register) or is_read
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)
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is_read = self.parser.is_reg_dependend_of(register, src.register) or is_read
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if "flag" in src:
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is_read = (
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self.parser.is_flag_dependend_of(register, src.flag) or is_read
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)
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is_read = self.parser.is_flag_dependend_of(register, src.flag) or is_read
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if "memory" in src:
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if src.memory.base is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.memory.base)
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or is_read
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)
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is_read = self.parser.is_reg_dependend_of(register, src.memory.base) or is_read
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if src.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.memory.index)
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or is_read
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self.parser.is_reg_dependend_of(register, src.memory.index) or is_read
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)
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# Check also if read in destination memory address
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for dst in chain(
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@@ -387,14 +369,10 @@ class KernelDG(nx.DiGraph):
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):
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if "memory" in dst:
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if dst.memory.base is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, dst.memory.base)
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or is_read
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)
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is_read = self.parser.is_reg_dependend_of(register, dst.memory.base) or is_read
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if dst.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, dst.memory.index)
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or is_read
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self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read
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)
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return is_read
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@@ -443,10 +421,7 @@ class KernelDG(nx.DiGraph):
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if mem.scale != src.scale:
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# scale factors do not match
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continue
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if (
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mem.index.get("prefix", "") + mem.index["name"]
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!= index_change["name"]
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):
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if mem.index.get("prefix", "") + mem.index["name"] != index_change["name"]:
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# index registers do not match
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continue
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addr_change += index_change["value"] * src.scale
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@@ -468,19 +443,13 @@ class KernelDG(nx.DiGraph):
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instruction_form.semantic_operands.src_dst,
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):
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if "register" in dst:
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is_written = (
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self.parser.is_reg_dependend_of(register, dst.register)
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or is_written
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)
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is_written = self.parser.is_reg_dependend_of(register, dst.register) or is_written
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if "flag" in dst:
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is_written = (
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self.parser.is_flag_dependend_of(register, dst.flag) or is_written
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)
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is_written = self.parser.is_flag_dependend_of(register, dst.flag) or is_written
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if "memory" in dst:
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if "pre_indexed" in dst.memory or "post_indexed" in dst.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, dst.memory.base)
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or is_written
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self.parser.is_reg_dependend_of(register, dst.memory.base) or is_written
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)
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# Check also for possible pre- or post-indexing in memory addresses
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for src in chain(
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@@ -490,8 +459,7 @@ class KernelDG(nx.DiGraph):
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if "memory" in src:
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if "pre_indexed" in src.memory or "post_indexed" in src.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, src.memory.base)
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or is_written
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self.parser.is_reg_dependend_of(register, src.memory.base) or is_written
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)
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return is_written
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@@ -522,9 +490,7 @@ class KernelDG(nx.DiGraph):
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lcd = self.get_loopcarried_dependencies()
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lcd_line_numbers = {}
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for dep in lcd:
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lcd_line_numbers[dep] = [
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x["line_number"] for x, lat in lcd[dep]["dependencies"]
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]
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lcd_line_numbers[dep] = [x["line_number"] for x, lat in lcd[dep]["dependencies"]]
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# add color scheme
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graph.graph["node"] = {"colorscheme": "accent8"}
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graph.graph["edge"] = {"colorscheme": "accent8"}
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@@ -535,9 +501,7 @@ class KernelDG(nx.DiGraph):
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max_line_number = max(lcd_line_numbers[dep])
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graph.add_edge(max_line_number, min_line_number)
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graph.edges[max_line_number, min_line_number]["latency"] = [
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lat
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for x, lat in lcd[dep]["dependencies"]
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if x["line_number"] == max_line_number
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lat for x, lat in lcd[dep]["dependencies"] if x["line_number"] == max_line_number
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]
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# add label to edges
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@@ -546,9 +510,7 @@ class KernelDG(nx.DiGraph):
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# add CP values to graph
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for n in cp:
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graph.nodes[n["line_number"]]["instruction_form"]["latency_cp"] = n[
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"latency_cp"
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]
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graph.nodes[n["line_number"]]["instruction_form"]["latency_cp"] = n["latency_cp"]
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# color CP and LCD
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for n in graph.nodes:
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@@ -568,8 +530,7 @@ class KernelDG(nx.DiGraph):
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for e in graph.edges:
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if (
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graph.nodes[e[0]]["instruction_form"]["line_number"] in cp_line_numbers
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and graph.nodes[e[1]]["instruction_form"]["line_number"]
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in cp_line_numbers
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and graph.nodes[e[1]]["instruction_form"]["line_number"] in cp_line_numbers
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and e[0] < e[1]
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):
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bold_edge = True
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@@ -581,8 +542,7 @@ class KernelDG(nx.DiGraph):
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graph.edges[e]["penwidth"] = 3
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for dep in lcd_line_numbers:
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if (
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graph.nodes[e[0]]["instruction_form"]["line_number"]
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in lcd_line_numbers[dep]
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graph.nodes[e[0]]["instruction_form"]["line_number"] in lcd_line_numbers[dep]
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and graph.nodes[e[1]]["instruction_form"]["line_number"]
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in lcd_line_numbers[dep]
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):
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