mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 02:30:08 +01:00
Updated db_interface files to work with class objects
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@@ -449,7 +449,7 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True):
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):
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):
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# Missing at least one key necessary for memory operands
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# Missing at least one key necessary for memory operands
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bad_operand.append(instr_form)
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bad_operand.append(instr_form)
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elif isinstance(operand, ImmediateOperand) and operand.imd == None:
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elif isinstance(operand, ImmediateOperand) and operand.type == None:
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# Missing 'imd' key
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# Missing 'imd' key
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bad_operand.append(instr_form)
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bad_operand.append(instr_form)
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# every entry exists twice --> uniquify
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# every entry exists twice --> uniquify
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@@ -276,11 +276,11 @@ class MachineModel(object):
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):
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):
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"""Import instruction form information."""
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"""Import instruction form information."""
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# If it already exists. Overwrite information.
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# If it already exists. Overwrite information.
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instr_data = self.get_instruction(name, operands)
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instr_data = self.get_instruction(instruction, operands)
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if instr_data is None:
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if instr_data is None:
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instr_data = {}
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instr_data = InstructionForm()
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self._data["instruction_forms"].append(instr_data)
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self._data["instruction_forms"].append(instr_data)
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self._data["instruction_forms_dict"][name].append(instr_data)
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self._data["instruction_forms_dict"][instruction].append(instr_data)
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instr_data.instruction = instruction
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instr_data.instruction = instruction
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instr_data.operands = operands
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instr_data.operands = operands
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@@ -291,13 +291,15 @@ class MachineModel(object):
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def set_instruction_entry(self, entry):
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def set_instruction_entry(self, entry):
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"""Import instruction as entry object form information."""
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"""Import instruction as entry object form information."""
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if entry.instruction == None and entry.operands == []:
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raise KeyError
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self.set_instruction(
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self.set_instruction(
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entry.instruction,
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entry.instruction,
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entry.operands if "operands" in entry else None,
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entry.operands,
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entry["latency"] if "latency" in entry else None,
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entry.latency,
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entry["port_pressure"] if "port_pressure" in entry else None,
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entry.port_pressure,
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entry["throughput"] if "throughput" in entry else None,
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entry.throughput,
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entry["uops"] if "uops" in entry else None,
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entry.uops,
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)
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)
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def add_port(self, port):
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def add_port(self, port):
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@@ -690,7 +692,7 @@ class MachineModel(object):
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if isinstance(operand, IdentifierOperand) or (
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if isinstance(operand, IdentifierOperand) or (
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isinstance(operand, ImmediateOperand) and operand.identifier != None
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isinstance(operand, ImmediateOperand) and operand.identifier != None
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):
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):
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return i_operand["class"] == "identifier"
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return isinstance(i_operand, IdentifierOperand)
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# prefetch option
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# prefetch option
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if not isinstance(operand, Operand) and "prfop" in operand:
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if not isinstance(operand, Operand) and "prfop" in operand:
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return i_operand["class"] == "prfop"
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return i_operand["class"] == "prfop"
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@@ -724,10 +726,10 @@ class MachineModel(object):
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# immediate
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# immediate
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if isinstance(operand, ImmediateOperand):
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if isinstance(operand, ImmediateOperand):
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# if "immediate" in operand.name or operand.value != None:
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# if "immediate" in operand.name or operand.value != None:
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return i_operand["class"] == "immediate" and i_operand["imd"] == "int"
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return isinstance(i_operand, ImmediateOperand) and i_operand.type == "int"
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# identifier (e.g., labels)
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# identifier (e.g., labels)
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if isinstance(operand, IdentifierOperand):
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if isinstance(operand, IdentifierOperand):
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return i_operand["class"] == "identifier"
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return isinstance(i_operand, IdentifierOperand)
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return self._compare_db_entries(i_operand, operand)
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return self._compare_db_entries(i_operand, operand)
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def _compare_db_entries(self, operand_1, operand_2):
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def _compare_db_entries(self, operand_1, operand_2):
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@@ -830,12 +832,13 @@ class MachineModel(object):
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def _is_AArch64_mem_type(self, i_mem, mem):
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def _is_AArch64_mem_type(self, i_mem, mem):
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"""Check if memory addressing type match."""
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"""Check if memory addressing type match."""
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print(mem)
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if (
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if (
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# check base
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# check base
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(
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(
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(mem.base is None and i_mem.base is None)
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(mem.base is None and i_mem.base is None)
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or i_mem.base == self.WILDCARD
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or i_mem.base == self.WILDCARD
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or mem.base.prefix == i_mem.base
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or (isinstance(mem.base, RegisterOperand) and (mem.base.prefix == i_mem.base))
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)
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)
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# check offset
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# check offset
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and (
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and (
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@@ -50,7 +50,7 @@ class TestDBInterface(unittest.TestCase):
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###########
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###########
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# Tests
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# Tests
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###########
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###########
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"""
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def test_add_single_entry(self):
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def test_add_single_entry(self):
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mm_csx = MachineModel("csx")
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mm_csx = MachineModel("csx")
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mm_tx2 = MachineModel("tx2")
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mm_tx2 = MachineModel("tx2")
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@@ -61,7 +61,7 @@ class TestDBInterface(unittest.TestCase):
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mm_csx.set_instruction_entry(self.entry_csx)
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mm_csx.set_instruction_entry(self.entry_csx)
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mm_tx2.set_instruction_entry(self.entry_tx2)
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mm_tx2.set_instruction_entry(self.entry_tx2)
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mm_zen1.set_instruction_entry({"name": "empty_operation"})
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mm_zen1.set_instruction_entry(InstructionForm(INSTRUCTION_ID="empty_operation"))
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num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx
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num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx
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num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2
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num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2
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@@ -70,12 +70,11 @@ class TestDBInterface(unittest.TestCase):
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self.assertEqual(num_entries_csx, 1)
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self.assertEqual(num_entries_csx, 1)
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self.assertEqual(num_entries_tx2, 1)
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self.assertEqual(num_entries_tx2, 1)
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self.assertEqual(num_entries_zen1, 1)
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self.assertEqual(num_entries_zen1, 1)
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"""
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def test_invalid_add(self):
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def test_invalid_add(self):
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entry = {}
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entry = InstructionForm()
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with self.assertRaises(KeyError):
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# with self.assertRaises(KeyError):
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MachineModel("csx").set_instruction_entry(entry)
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# MachineModel("csx").set_instruction_entry(entry)
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with self.assertRaises(TypeError):
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with self.assertRaises(TypeError):
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MachineModel("csx").set_instruction()
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MachineModel("csx").set_instruction()
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