From 596a323dfbebf570488061f51413d4d8be505f7c Mon Sep 17 00:00:00 2001
From: JanLJL <jan.laukemann@fau.de>
Date: Sat, 21 Nov 2020 21:00:58 +0100
Subject: [PATCH] bugfixes

---
 osaca/parser/parser_x86att.py | 9 +++++----
 osaca/semantics/hw_model.py   | 8 ++++----
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/osaca/parser/parser_x86att.py b/osaca/parser/parser_x86att.py
index 24f9639..bcc22e8 100755
--- a/osaca/parser/parser_x86att.py
+++ b/osaca/parser/parser_x86att.py
@@ -406,7 +406,10 @@ class ParserX86ATT(BaseParser):
 
     def is_basic_gpr(self, register):
         """Check if register is a basic general purpose register (ebi, rax, ...)"""
-        if any(char.isdigit() for char in register['name']):
+        if (
+            any(char.isdigit() for char in register['name'])
+            or any(register['name'].lower().startswith(x) for x in ['mm', 'xmm', 'ymm', 'zmm'])
+        ):
             return False
         return True
 
@@ -414,10 +417,8 @@ class ParserX86ATT(BaseParser):
         """Check if register is a general purpose register"""
         if register is None:
             return False
-
         if self.is_basic_gpr(register):
             return True
-
         return re.match(r'R([0-9]+)[DWB]?', register['name'], re.IGNORECASE)
 
     def is_vector_register(self, register):
@@ -429,7 +430,7 @@ class ParserX86ATT(BaseParser):
         return False
 
     def get_reg_type(self, register):
-        """Ger register type"""
+        """Get register type"""
         if register is None:
             return False
         if self.is_gpr(register):
diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py
index 97e6fe8..9968e43 100755
--- a/osaca/semantics/hw_model.py
+++ b/osaca/semantics/hw_model.py
@@ -187,8 +187,8 @@ class MachineModel(object):
         """Return load thorughput for given register type."""
         ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)]
         if len(ld_tp) > 0:
-            return ld_tp[0]['port_pressure']
-        return self._data['load_throughput_default']
+            return ld_tp[0]['port_pressure'].copy()
+        return self._data['load_throughput_default'].copy()
 
     def get_store_latency(self, reg_type):
         """Return store latency for given register type."""
@@ -199,8 +199,8 @@ class MachineModel(object):
         """Return store throughput for given register type."""
         st_tp = [m for m in self._data['store_throughput'] if self._match_mem_entries(memory, m)]
         if len(st_tp) > 0:
-            return st_tp[0]['port_pressure']
-        return self._data['store_throughput_default']
+            return st_tp[0]['port_pressure'].copy()
+        return self._data['store_throughput_default'].copy()
 
     def _match_mem_entries(self, mem, i_mem):
         """Check if memory addressing ``mem`` and ``i_mem`` are of the same type."""