diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml
index 86aaff6..0058b69 100644
--- a/osaca/data/tsv110.yml
+++ b/osaca/data/tsv110.yml
@@ -835,6 +835,18 @@ instruction_forms:
   port_pressure: [[1, '3']]
   throughput: 1.0
   uops: 1
+- name: mul
+  operands:
+  - class: register
+    prefix: w
+  - class: register
+    prefix: w
+  - class: register
+    prefix: w
+  latency: 4.0
+  port_pressure: [[1, '3']]
+  throughput: 1.0
+  uops: 1
 - name: mul
   operands:
   - class: register
@@ -894,7 +906,7 @@ instruction_forms:
   throughput: 1.0
   uops: 1
 # arithmetic instructions: [s|u]mull (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
-- name: [smulh, umulh]
+- name: [smull, umull]
   operands:
   - class: register
     prefix: x
@@ -2724,6 +2736,22 @@ instruction_forms:
   latency: 5.0
   port_pressure: [[1, '67'], [1, '012']]
   uops: 2
+# memory instructions: ldrb (data from AArch64SchedTSV110.td)
+- name: ldrb
+  operands:
+  - class: register
+    prefix: w
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: false
+  throughput: 0.5
+  latency: 4.0
+  port_pressure: [[1, '67']]
+  uops: 1
 # memory instructions: ldur (data from AArch64SchedTSV110.td)
 - name: ldur
   operands:
@@ -3166,6 +3194,23 @@ instruction_forms:
   latency: 9.0
   port_pressure: [[2, '67'], [2, '012']]
   uops: 4
+- name: ldp
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: x
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: false
+  throughput: 1.0
+  latency: 9.0
+  port_pressure: [[2, '67'], [2, '012']]
+  uops: 4
 - name: ldp
   operands:
   - class: register