mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 18:50:08 +01:00
migrate code style to Black
This commit is contained in:
Julian Hammer
@@ -30,34 +30,34 @@ class KernelDG(nx.DiGraph):
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# 3. get LT value and set as edge weight
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dg = nx.DiGraph()
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for i, instruction_form in enumerate(kernel):
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dg.add_node(instruction_form['line_number'])
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dg.nodes[instruction_form['line_number']]['instruction_form'] = instruction_form
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dg.add_node(instruction_form["line_number"])
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dg.nodes[instruction_form["line_number"]]["instruction_form"] = instruction_form
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# add load as separate node if existent
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if (
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INSTR_FLAGS.HAS_LD in instruction_form['flags']
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and INSTR_FLAGS.LD not in instruction_form['flags']
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INSTR_FLAGS.HAS_LD in instruction_form["flags"]
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and INSTR_FLAGS.LD not in instruction_form["flags"]
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):
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# add new node
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dg.add_node(instruction_form['line_number'] + 0.1)
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dg.nodes[instruction_form['line_number'] + 0.1][
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'instruction_form'
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dg.add_node(instruction_form["line_number"] + 0.1)
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dg.nodes[instruction_form["line_number"] + 0.1][
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"instruction_form"
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] = instruction_form
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# and set LD latency as edge weight
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dg.add_edge(
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instruction_form['line_number'] + 0.1,
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instruction_form['line_number'],
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latency=instruction_form['latency'] - instruction_form['latency_wo_load'],
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instruction_form["line_number"] + 0.1,
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instruction_form["line_number"],
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latency=instruction_form["latency"] - instruction_form["latency_wo_load"],
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)
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for dep in self.find_depending(instruction_form, kernel[i + 1 :]):
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edge_weight = (
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instruction_form['latency']
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if 'latency_wo_load' not in instruction_form
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else instruction_form['latency_wo_load']
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instruction_form["latency"]
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if "latency_wo_load" not in instruction_form
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else instruction_form["latency_wo_load"]
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)
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dg.add_edge(
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instruction_form['line_number'], dep['line_number'], latency=edge_weight
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instruction_form["line_number"], dep["line_number"], latency=edge_weight
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)
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dg.nodes[dep['line_number']]['instruction_form'] = dep
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dg.nodes[dep["line_number"]]["instruction_form"] = dep
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return dg
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def check_for_loopcarried_dep(self, kernel):
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@@ -109,17 +109,17 @@ class KernelDG(nx.DiGraph):
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for dep in loopcarried_deps:
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nodes = []
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for n in dep[1]:
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self._get_node_by_lineno(int(n))['latency_lcd'] = 0
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self._get_node_by_lineno(int(n))["latency_lcd"] = 0
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for n in dep[1]:
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node = self._get_node_by_lineno(int(n))
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if int(n) != n and int(n) in dep[1]:
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node['latency_lcd'] += node['latency'] - node['latency_wo_load']
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node["latency_lcd"] += node["latency"] - node["latency_wo_load"]
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else:
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node['latency_lcd'] += node['latency_wo_load']
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node["latency_lcd"] += node["latency_wo_load"]
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nodes.append(node)
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loopcarried_deps_dict[dep[0]] = {
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'root': self._get_node_by_lineno(dep[0]),
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'dependencies': nodes,
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"root": self._get_node_by_lineno(dep[0]),
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"dependencies": nodes,
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}
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return loopcarried_deps_dict
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@@ -131,30 +131,30 @@ class KernelDG(nx.DiGraph):
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def get_critical_path(self):
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"""Find and return critical path after the creation of a directed graph."""
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if nx.algorithms.dag.is_directed_acyclic_graph(self.dg):
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longest_path = nx.algorithms.dag.dag_longest_path(self.dg, weight='latency')
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longest_path = nx.algorithms.dag.dag_longest_path(self.dg, weight="latency")
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for line_number in longest_path:
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self._get_node_by_lineno(int(line_number))['latency_cp'] = 0
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self._get_node_by_lineno(int(line_number))["latency_cp"] = 0
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# add LD latency to instruction
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for line_number in longest_path:
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node = self._get_node_by_lineno(int(line_number))
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if line_number != int(line_number) and int(line_number) in longest_path:
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node['latency_cp'] += self.dg.edges[(line_number, int(line_number))]['latency']
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node["latency_cp"] += self.dg.edges[(line_number, int(line_number))]["latency"]
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elif (
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line_number == int(line_number)
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and 'mem_dep' in node
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and self.dg.has_edge(node['mem_dep']['line_number'], line_number)
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and "mem_dep" in node
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and self.dg.has_edge(node["mem_dep"]["line_number"], line_number)
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):
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node['latency_cp'] += node['latency']
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node["latency_cp"] += node["latency"]
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else:
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node['latency_cp'] += (
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node['latency']
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if 'latency_wo_load' not in node
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else node['latency_wo_load']
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node["latency_cp"] += (
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node["latency"]
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if "latency_wo_load" not in node
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else node["latency_wo_load"]
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)
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return [x for x in self.kernel if x['line_number'] in longest_path]
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return [x for x in self.kernel if x["line_number"] in longest_path]
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else:
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# split to DAG
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raise NotImplementedError('Kernel is cyclic.')
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raise NotImplementedError("Kernel is cyclic.")
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def get_loopcarried_dependencies(self):
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"""
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@@ -164,7 +164,7 @@ class KernelDG(nx.DiGraph):
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return self.loopcarried_deps
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else:
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# split to DAG
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raise NotImplementedError('Kernel is cyclic.')
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raise NotImplementedError("Kernel is cyclic.")
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def find_depending(
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self, instruction_form, kernel, include_write=False, flag_dependencies=False
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@@ -186,7 +186,7 @@ class KernelDG(nx.DiGraph):
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instruction_form.semantic_operands.destination,
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instruction_form.semantic_operands.src_dst,
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):
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if 'register' in dst:
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if "register" in dst:
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# Check for read of register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.register, instr_form):
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@@ -200,7 +200,7 @@ class KernelDG(nx.DiGraph):
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if include_write:
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yield instr_form
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break
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if 'flag' in dst and flag_dependencies:
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if "flag" in dst and flag_dependencies:
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# Check for read of flag until overwrite
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for instr_form in kernel:
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if self.is_read(dst.flag, instr_form):
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@@ -214,23 +214,23 @@ class KernelDG(nx.DiGraph):
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if include_write:
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yield instr_form
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break
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elif 'memory' in dst:
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elif "memory" in dst:
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# Check if base register is altered during memory access
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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if "pre_indexed" in dst.memory or "post_indexed" in dst.memory:
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# Check for read of base register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.memory.base, instr_form):
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instr_form['mem_dep'] = instruction_form
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instr_form["mem_dep"] = instruction_form
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yield instr_form
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if self.is_written(dst.memory.base, instr_form):
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# operand in src_dst list
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if include_write:
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instr_form['mem_dep'] = instruction_form
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instr_form["mem_dep"] = instruction_form
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yield instr_form
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break
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elif self.is_written(dst.memory.base, instr_form):
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if include_write:
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instr_form['mem_dep'] = instruction_form
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instr_form["mem_dep"] = instruction_form
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yield instr_form
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break
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@@ -239,8 +239,8 @@ class KernelDG(nx.DiGraph):
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Returns iterator
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"""
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if not instr_form and not line_number:
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raise ValueError('Either instruction form or line_number required.')
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line_number = line_number if line_number else instr_form['line_number']
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raise ValueError("Either instruction form or line_number required.")
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line_number = line_number if line_number else instr_form["line_number"]
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if self.dg.has_node(line_number):
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return self.dg.successors(line_number)
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return iter([])
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@@ -253,29 +253,25 @@ class KernelDG(nx.DiGraph):
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for src in chain(
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instruction_form.semantic_operands.source, instruction_form.semantic_operands.src_dst
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):
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if 'register' in src:
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if "register" in src:
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is_read = self.parser.is_reg_dependend_of(register, src.register) or is_read
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if 'flag' in src:
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if "flag" in src:
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is_read = self.parser.is_flag_dependend_of(register, src.flag) or is_read
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if 'memory' in src:
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if "memory" in src:
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if src.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, src.memory.base) or is_read
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if src.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.memory.index) or is_read
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)
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is_read = self.parser.is_reg_dependend_of(register, src.memory.index) or is_read
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# Check also if read in destination memory address
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for dst in chain(
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instruction_form.semantic_operands.destination,
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instruction_form.semantic_operands.src_dst,
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):
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if 'memory' in dst:
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if "memory" in dst:
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if dst.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, dst.memory.base) or is_read
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if dst.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read
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)
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is_read = self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read
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return is_read
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def is_written(self, register, instruction_form):
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@@ -287,12 +283,12 @@ class KernelDG(nx.DiGraph):
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instruction_form.semantic_operands.destination,
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instruction_form.semantic_operands.src_dst,
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):
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if 'register' in dst:
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if "register" in dst:
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is_written = self.parser.is_reg_dependend_of(register, dst.register) or is_written
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if 'flag' in dst:
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if "flag" in dst:
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is_written = self.parser.is_flag_dependend_of(register, dst.flag) or is_written
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if 'memory' in dst:
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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if "memory" in dst:
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if "pre_indexed" in dst.memory or "post_indexed" in dst.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, dst.memory.base) or is_written
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)
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@@ -300,8 +296,8 @@ class KernelDG(nx.DiGraph):
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for src in chain(
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instruction_form.semantic_operands.source, instruction_form.semantic_operands.src_dst
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):
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if 'memory' in src:
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if 'pre_indexed' in src.memory or 'post_indexed' in src.memory:
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if "memory" in src:
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if "pre_indexed" in src.memory or "post_indexed" in src.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, src.memory.base) or is_written
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)
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@@ -317,51 +313,51 @@ class KernelDG(nx.DiGraph):
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"""
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graph = copy.deepcopy(self.dg)
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cp = self.get_critical_path()
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cp_line_numbers = [x['line_number'] for x in cp]
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cp_line_numbers = [x["line_number"] for x in cp]
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lcd = self.get_loopcarried_dependencies()
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lcd_line_numbers = {}
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for dep in lcd:
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lcd_line_numbers[dep] = [x['line_number'] for x in lcd[dep]['dependencies']]
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lcd_line_numbers[dep] = [x["line_number"] for x in lcd[dep]["dependencies"]]
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# add color scheme
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graph.graph['node'] = {'colorscheme': 'accent8'}
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graph.graph['edge'] = {'colorscheme': 'accent8'}
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graph.graph["node"] = {"colorscheme": "accent8"}
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graph.graph["edge"] = {"colorscheme": "accent8"}
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# create LCD edges
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for dep in lcd_line_numbers:
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min_line_number = min(lcd_line_numbers[dep])
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max_line_number = max(lcd_line_numbers[dep])
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graph.add_edge(max_line_number, min_line_number)
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graph.edges[max_line_number, min_line_number]['latency'] = [
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x for x in lcd[dep]['dependencies'] if x['line_number'] == max_line_number
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][0]['latency_lcd']
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graph.edges[max_line_number, min_line_number]["latency"] = [
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x for x in lcd[dep]["dependencies"] if x["line_number"] == max_line_number
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][0]["latency_lcd"]
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# add label to edges
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for e in graph.edges:
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graph.edges[e]['label'] = graph.edges[e]['latency']
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graph.edges[e]["label"] = graph.edges[e]["latency"]
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# add CP values to graph
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for n in cp:
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graph.nodes[n['line_number']]['instruction_form']['latency_cp'] = n['latency_cp']
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graph.nodes[n["line_number"]]["instruction_form"]["latency_cp"] = n["latency_cp"]
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# color CP and LCD
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for n in graph.nodes:
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if n in cp_line_numbers:
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# graph.nodes[n]['color'] = 1
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graph.nodes[n]['style'] = 'bold'
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graph.nodes[n]['penwidth'] = 4
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graph.nodes[n]["style"] = "bold"
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graph.nodes[n]["penwidth"] = 4
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for col, dep in enumerate(lcd):
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if n in lcd_line_numbers[dep]:
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if 'style' not in graph.nodes[n]:
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graph.nodes[n]['style'] = 'filled'
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if "style" not in graph.nodes[n]:
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graph.nodes[n]["style"] = "filled"
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else:
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graph.nodes[n]['style'] += ',filled'
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graph.nodes[n]['fillcolor'] = 2 + col
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graph.nodes[n]["style"] += ",filled"
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graph.nodes[n]["fillcolor"] = 2 + col
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# color edges
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for e in graph.edges:
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if (
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graph.nodes[e[0]]['instruction_form']['line_number'] in cp_line_numbers
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and graph.nodes[e[1]]['instruction_form']['line_number'] in cp_line_numbers
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graph.nodes[e[0]]["instruction_form"]["line_number"] in cp_line_numbers
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and graph.nodes[e[1]]["instruction_form"]["line_number"] in cp_line_numbers
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and e[0] < e[1]
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):
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bold_edge = True
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@@ -369,38 +365,38 @@ class KernelDG(nx.DiGraph):
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if i in cp_line_numbers:
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bold_edge = False
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if bold_edge:
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graph.edges[e]['style'] = 'bold'
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graph.edges[e]['penwidth'] = 3
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graph.edges[e]["style"] = "bold"
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graph.edges[e]["penwidth"] = 3
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for dep in lcd_line_numbers:
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if (
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graph.nodes[e[0]]['instruction_form']['line_number'] in lcd_line_numbers[dep]
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and graph.nodes[e[1]]['instruction_form']['line_number']
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graph.nodes[e[0]]["instruction_form"]["line_number"] in lcd_line_numbers[dep]
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and graph.nodes[e[1]]["instruction_form"]["line_number"]
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in lcd_line_numbers[dep]
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):
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graph.edges[e]['color'] = graph.nodes[e[1]]['fillcolor']
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graph.edges[e]["color"] = graph.nodes[e[1]]["fillcolor"]
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# rename node from [idx] to [idx mnemonic] and add shape
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mapping = {}
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for n in graph.nodes:
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if int(n) != n:
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mapping[n] = '{}: LOAD'.format(int(n))
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graph.nodes[n]['fontname'] = 'italic'
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graph.nodes[n]['fontsize'] = 11.0
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mapping[n] = "{}: LOAD".format(int(n))
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graph.nodes[n]["fontname"] = "italic"
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graph.nodes[n]["fontsize"] = 11.0
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else:
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node = graph.nodes[n]['instruction_form']
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if node['instruction'] is not None:
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mapping[n] = '{}: {}'.format(n, node['instruction'])
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node = graph.nodes[n]["instruction_form"]
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if node["instruction"] is not None:
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mapping[n] = "{}: {}".format(n, node["instruction"])
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else:
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label = 'label' if node['label'] else None
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label = 'directive' if node['directive'] else label
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label = 'comment' if node['comment'] and label is None else label
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mapping[n] = '{}: {}'.format(n, label)
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graph.nodes[n]['fontname'] = 'italic'
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graph.nodes[n]['fontsize'] = 11.0
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graph.nodes[n]['shape'] = 'rectangle'
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label = "label" if node["label"] else None
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label = "directive" if node["directive"] else label
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label = "comment" if node["comment"] and label is None else label
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mapping[n] = "{}: {}".format(n, label)
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graph.nodes[n]["fontname"] = "italic"
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graph.nodes[n]["fontsize"] = 11.0
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graph.nodes[n]["shape"] = "rectangle"
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nx.relabel.relabel_nodes(graph, mapping, copy=False)
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if filepath:
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nx.drawing.nx_agraph.write_dot(graph, filepath)
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else:
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nx.drawing.nx_agraph.write_dot(graph, 'osaca_dg.dot')
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nx.drawing.nx_agraph.write_dot(graph, "osaca_dg.dot")
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