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migrate code style to Black

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This commit is contained in:
Julian Hammer
2021-03-11 12:02:45 +01:00
parent 1ebe5ecfbd
commit 6204c90934
33 changed files with 3045 additions and 2960 deletions
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20
tests/all_tests.py
View File

@@ -3,18 +3,18 @@
import sys
import unittest
sys.path[0:0] = ['.', '..']
sys.path[0:0] = [".", ".."]
suite = unittest.TestLoader().loadTestsFromNames(
[
'test_base_parser',
'test_parser_x86att',
'test_parser_AArch64',
'test_marker_utils',
'test_semantics',
'test_frontend',
'test_db_interface',
'test_kerncraftAPI',
'test_cli',
"test_base_parser",
"test_parser_x86att",
"test_parser_AArch64",
"test_marker_utils",
"test_semantics",
"test_frontend",
"test_db_interface",
"test_kerncraftAPI",
"test_cli",
]
)

32
tests/test_base_parser.py
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@@ -16,13 +16,13 @@ class TestBaseParser(unittest.TestCase):
self.parser = BaseParser()
except NotImplementedError:
pass
with open(self._find_file('triad_x86_iaca.s')) as f:
with open(self._find_file("triad_x86_iaca.s")) as f:
self.triad_code = f.read()
with open(self._find_file('triad_arm_iaca.s')) as f:
with open(self._find_file("triad_arm_iaca.s")) as f:
self.triad_code_arm = f.read()
with open(self._find_file('kernel_x86.s')) as f:
with open(self._find_file("kernel_x86.s")) as f:
self.x86_code = f.read()
with open(self._find_file('kernel_aarch64.s')) as f:
with open(self._find_file("kernel_aarch64.s")) as f:
self.aarch64_code = f.read()
##################
@@ -34,19 +34,19 @@ class TestBaseParser(unittest.TestCase):
self.parser.parse_file(self.triad_code)
def test_parse_line(self):
line_instruction = '\t\tlea 2(%rax,%rax), %ecx #12.9'
line_instruction = "\t\tlea 2(%rax,%rax), %ecx #12.9"
with self.assertRaises(NotImplementedError):
self.parser.parse_line(line_instruction)
def test_parse_instruction(self):
instr1 = '\t\tvcvtsi2ss %edx, %xmm2, %xmm2\t\t\t#12.27'
instr1 = "\t\tvcvtsi2ss %edx, %xmm2, %xmm2\t\t\t#12.27"
with self.assertRaises(NotImplementedError):
self.parser.parse_instruction(instr1)
def test_register_funcs(self):
reg_a1 = AttrDict({'name': 'rax'})
reg_a2 = AttrDict({'name': 'eax'})
register_string = 'v1.2d'
reg_a1 = AttrDict({"name": "rax"})
reg_a2 = AttrDict({"name": "eax"})
register_string = "v1.2d"
with self.assertRaises(NotImplementedError):
self.parser.is_reg_dependend_of(reg_a1, reg_a2)
with self.assertRaises(NotImplementedError):
@@ -61,15 +61,15 @@ class TestBaseParser(unittest.TestCase):
self.parser.get_full_reg_name(reg_a1)
def test_normalize_imd(self):
imd_hex_1 = {'value': '0x4f'}
imd_hex_1 = {"value": "0x4f"}
with self.assertRaises(NotImplementedError):
self.parser.normalize_imd(imd_hex_1)
def test_detect_ISA(self):
self.assertEqual(BaseParser.detect_ISA(self.triad_code), 'x86')
self.assertEqual(BaseParser.detect_ISA(self.triad_code_arm), 'aarch64')
self.assertEqual(BaseParser.detect_ISA(self.x86_code), 'x86')
self.assertEqual(BaseParser.detect_ISA(self.aarch64_code), 'aarch64')
self.assertEqual(BaseParser.detect_ISA(self.triad_code), "x86")
self.assertEqual(BaseParser.detect_ISA(self.triad_code_arm), "aarch64")
self.assertEqual(BaseParser.detect_ISA(self.x86_code), "x86")
self.assertEqual(BaseParser.detect_ISA(self.aarch64_code), "aarch64")
##################
# Helper functions
@@ -78,11 +78,11 @@ class TestBaseParser(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestBaseParser)
unittest.TextTestRunner(verbosity=2).run(suite)

153
tests/test_cli.py
View File

@@ -29,11 +29,11 @@ class TestCLI(unittest.TestCase):
def test_check_arguments(self):
parser = osaca.create_parser(parser=ErrorRaisingArgumentParser())
args = parser.parse_args(['--arch', 'WRONG_ARCH', self._find_file('gs', 'csx', 'gcc')])
args = parser.parse_args(["--arch", "WRONG_ARCH", self._find_file("gs", "csx", "gcc")])
with self.assertRaises(ValueError):
osaca.check_arguments(args, parser)
args = parser.parse_args(
['--arch', 'csx', '--import', 'WRONG_BENCH', self._find_file('gs', 'csx', 'gcc')]
["--arch", "csx", "--import", "WRONG_BENCH", self._find_file("gs", "csx", "gcc")]
)
with self.assertRaises(ValueError):
osaca.check_arguments(args, parser)
@@ -42,22 +42,22 @@ class TestCLI(unittest.TestCase):
parser = osaca.create_parser(parser=ErrorRaisingArgumentParser())
args = parser.parse_args(
[
'--arch',
'tx2',
'--import',
'ibench',
self._find_test_file('ibench_import_aarch64.dat'),
"--arch",
"tx2",
"--import",
"ibench",
self._find_test_file("ibench_import_aarch64.dat"),
]
)
output = StringIO()
osaca.run(args, output_file=output)
args = parser.parse_args(
[
'--arch',
'tx2',
'--import',
'asmbench',
self._find_test_file('asmbench_import_aarch64.dat'),
"--arch",
"tx2",
"--import",
"asmbench",
self._find_test_file("asmbench_import_aarch64.dat"),
]
)
osaca.run(args, output_file=output)
@@ -65,28 +65,28 @@ class TestCLI(unittest.TestCase):
def test_check_db(self):
parser = osaca.create_parser(parser=ErrorRaisingArgumentParser())
args = parser.parse_args(
['--arch', 'tx2', '--db-check', '--verbose', self._find_test_file('triad_x86_iaca.s')]
["--arch", "tx2", "--db-check", "--verbose", self._find_test_file("triad_x86_iaca.s")]
)
output = StringIO()
osaca.run(args, output_file=output)
def test_get_parser(self):
self.assertTrue(isinstance(osaca.get_asm_parser('csx'), ParserX86ATT))
self.assertTrue(isinstance(osaca.get_asm_parser('tx2'), ParserAArch64))
self.assertTrue(isinstance(osaca.get_asm_parser("csx"), ParserX86ATT))
self.assertTrue(isinstance(osaca.get_asm_parser("tx2"), ParserAArch64))
with self.assertRaises(ValueError):
osaca.get_asm_parser('UNKNOWN')
osaca.get_asm_parser("UNKNOWN")
def test_marker_insert_x86(self):
# copy file to add markers
name = self._find_test_file('kernel_x86.s')
name_copy = name + '.copy.s'
name = self._find_test_file("kernel_x86.s")
name_copy = name + ".copy.s"
copyfile(name, name_copy)
user_input = ['.L10']
user_input = [".L10"]
output = StringIO()
parser = osaca.create_parser()
args = parser.parse_args(['--arch', 'csx', '--insert-marker', name_copy])
with patch('builtins.input', side_effect=user_input):
args = parser.parse_args(["--arch", "csx", "--insert-marker", name_copy])
with patch("builtins.input", side_effect=user_input):
osaca.run(args, output_file=output)
lines_orig = len(open(name).readlines())
@@ -97,14 +97,14 @@ class TestCLI(unittest.TestCase):
def test_marker_insert_aarch64(self):
# copy file to add markers
name = self._find_test_file('kernel_aarch64.s')
name_copy = name + '.copy.s'
name = self._find_test_file("kernel_aarch64.s")
name_copy = name + ".copy.s"
copyfile(name, name_copy)
user_input = ['.LBB0_32', '64']
user_input = [".LBB0_32", "64"]
parser = osaca.create_parser()
args = parser.parse_args(['--arch', 'tx2', '--insert-marker', name_copy])
with patch('builtins.input', side_effect=user_input):
args = parser.parse_args(["--arch", "tx2", "--insert-marker", name_copy])
with patch("builtins.input", side_effect=user_input):
osaca.run(args)
lines_orig = len(open(name).readlines())
@@ -115,18 +115,18 @@ class TestCLI(unittest.TestCase):
def test_examples(self):
kernels = [
'add',
'copy',
'daxpy',
'gs',
'j2d',
'striad',
'sum_reduction',
'triad',
'update',
"add",
"copy",
"daxpy",
"gs",
"j2d",
"striad",
"sum_reduction",
"triad",
"update",
]
archs = ['csx', 'tx2', 'zen1']
comps = {'csx': ['gcc', 'icc'], 'tx2': ['gcc', 'clang'], 'zen1': ['gcc']}
archs = ["csx", "tx2", "zen1"]
comps = {"csx": ["gcc", "icc"], "tx2": ["gcc", "clang"], "zen1": ["gcc"]}
parser = osaca.create_parser()
# Analyze all asm files resulting out of kernels, archs and comps
for k in kernels:
@@ -134,11 +134,11 @@ class TestCLI(unittest.TestCase):
for c in comps[a]:
with self.subTest(kernel=k, arch=a, comp=c):
args = parser.parse_args(
['--arch', a, self._find_file(k, a, c), '--export-graph', '/dev/null']
["--arch", a, self._find_file(k, a, c), "--export-graph", "/dev/null"]
)
output = StringIO()
osaca.run(args, output_file=output)
self.assertTrue('WARNING' not in output.getvalue())
self.assertTrue("WARNING" not in output.getvalue())
def test_architectures(self):
parser = osaca.create_parser()
@@ -147,10 +147,8 @@ class TestCLI(unittest.TestCase):
for arch in archs:
with self.subTest(micro_arch=arch):
isa = MachineModel.get_isa_for_arch(arch)
kernel = 'kernel_{}.s'.format(isa)
args = parser.parse_args(
['--arch', arch, self._find_test_file(kernel)]
)
kernel = "kernel_{}.s".format(isa)
args = parser.parse_args(["--arch", arch, self._find_test_file(kernel)])
output = StringIO()
osaca.run(args, output_file=output)
@@ -168,59 +166,68 @@ class TestCLI(unittest.TestCase):
# Run test kernels without --arch flag
parser = osaca.create_parser()
# x86
kernel_x86 = 'kernel_x86.s'
kernel_x86 = "kernel_x86.s"
args = parser.parse_args([self._find_test_file(kernel_x86)])
output = StringIO()
osaca.run(args, output_file=output)
# AArch64
kernel_aarch64 = 'kernel_aarch64.s'
kernel_aarch64 = "kernel_aarch64.s"
args = parser.parse_args([self._find_test_file(kernel_aarch64)])
osaca.run(args, output_file=output)
def test_user_warnings(self):
parser = osaca.create_parser()
kernel = 'triad_x86_unmarked.s'
kernel = "triad_x86_unmarked.s"
args = parser.parse_args(
['--arch', 'csx', '--ignore-unknown', self._find_test_file(kernel)]
["--arch", "csx", "--ignore-unknown", self._find_test_file(kernel)]
)
output = StringIO()
osaca.run(args, output_file=output)
# WARNING for length
self.assertTrue(output.getvalue().count('WARNING') == 1)
self.assertTrue(output.getvalue().count("WARNING") == 1)
args = parser.parse_args(
['--lines', '100-199', '--ignore-unknown', self._find_test_file(kernel)]
["--lines", "100-199", "--ignore-unknown", self._find_test_file(kernel)]
)
output = StringIO()
osaca.run(args, output_file=output)
# WARNING for arch
self.assertTrue(output.getvalue().count('WARNING') == 1)
self.assertTrue(output.getvalue().count("WARNING") == 1)
def test_lines_arg(self):
# Run tests with --lines option
parser = osaca.create_parser()
kernel_x86 = 'triad_x86_iaca.s'
args_base = parser.parse_args(
['--arch', 'csx', self._find_test_file(kernel_x86)]
)
kernel_x86 = "triad_x86_iaca.s"
args_base = parser.parse_args(["--arch", "csx", self._find_test_file(kernel_x86)])
output_base = StringIO()
osaca.run(args_base, output_file=output_base)
output_base = output_base.getvalue().split('\n')[8:]
output_base = output_base.getvalue().split("\n")[8:]
args = []
args.append(parser.parse_args(
['--lines', '146-154', '--arch', 'csx', self._find_test_file(kernel_x86)]
))
args.append(parser.parse_args(
['--lines', '146:154', '--arch', 'csx', self._find_test_file(kernel_x86)]
))
args.append(parser.parse_args(
['--lines', '146,147:148,149-154', '--arch', 'csx', self._find_test_file(kernel_x86)]
))
args.append(
parser.parse_args(
["--lines", "146-154", "--arch", "csx", self._find_test_file(kernel_x86)]
)
)
args.append(
parser.parse_args(
["--lines", "146:154", "--arch", "csx", self._find_test_file(kernel_x86)]
)
)
args.append(
parser.parse_args(
[
"--lines",
"146,147:148,149-154",
"--arch",
"csx",
self._find_test_file(kernel_x86),
]
)
)
for a in args:
with self.subTest(params=a):
output = StringIO()
osaca.run(a, output_file=output)
self.assertEqual(output.getvalue().split('\n')[8:], output_base)
self.assertEqual(output.getvalue().split("\n")[8:], output_base)
##################
# Helper functions
@@ -231,23 +238,23 @@ class TestCLI(unittest.TestCase):
testdir = os.path.dirname(__file__)
name = os.path.join(
testdir,
'../examples',
"../examples",
kernel,
kernel + '.s.' + arch[:3].lower() + '.' + comp.lower() + '.s',
kernel + ".s." + arch[:3].lower() + "." + comp.lower() + ".s",
)
if kernel == 'j2d' and arch.lower() == 'csx':
name = name[:-1] + 'AVX.s'
if kernel == "j2d" and arch.lower() == "csx":
name = name[:-1] + "AVX.s"
assert os.path.exists(name)
return name
@staticmethod
def _find_test_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestCLI)
unittest.TextTestRunner(verbosity=2, buffer=True).run(suite)

108
tests/test_db_interface.py
View File

@@ -15,47 +15,47 @@ class TestDBInterface(unittest.TestCase):
@classmethod
def setUpClass(self):
sample_entry = {
'name': 'DoItRightAndDoItFast',
'operands': [
{'class': 'memory', 'offset': 'imd', 'base': 'gpr', 'index': 'gpr', 'scale': 8},
{'class': 'register', 'name': 'xmm'},
"name": "DoItRightAndDoItFast",
"operands": [
{"class": "memory", "offset": "imd", "base": "gpr", "index": "gpr", "scale": 8},
{"class": "register", "name": "xmm"},
],
'throughput': 1.25,
'latency': 125,
'uops': 6,
"throughput": 1.25,
"latency": 125,
"uops": 6,
}
self.entry_csx = sample_entry.copy()
self.entry_tx2 = sample_entry.copy()
self.entry_zen1 = sample_entry.copy()
# self.entry_csx['port_pressure'] = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0]
self.entry_csx['port_pressure'] = [[5, '0156'], [1, '23'], [1, ['2D', '3D']]]
self.entry_csx["port_pressure"] = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]]
# self.entry_tx2['port_pressure'] = [2.5, 2.5, 0, 0, 0.5, 0.5]
self.entry_tx2['port_pressure'] = [[5, '01'], [1, '45']]
del self.entry_tx2['operands'][1]['name']
self.entry_tx2['operands'][1]['prefix'] = 'x'
self.entry_tx2["port_pressure"] = [[5, "01"], [1, "45"]]
del self.entry_tx2["operands"][1]["name"]
self.entry_tx2["operands"][1]["prefix"] = "x"
# self.entry_zen1['port_pressure'] = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1]
self.entry_zen1['port_pressure'] = [[4, '0123'], [1, '4'], [1, '89'], [2, ['8D', '9D']]]
self.entry_zen1["port_pressure"] = [[4, "0123"], [1, "4"], [1, "89"], [2, ["8D", "9D"]]]
###########
# Tests
###########
def test_add_single_entry(self):
mm_csx = MachineModel('csx')
mm_tx2 = MachineModel('tx2')
mm_zen1 = MachineModel('zen1')
num_entries_csx = len(mm_csx['instruction_forms'])
num_entries_tx2 = len(mm_tx2['instruction_forms'])
num_entries_zen1 = len(mm_zen1['instruction_forms'])
mm_csx = MachineModel("csx")
mm_tx2 = MachineModel("tx2")
mm_zen1 = MachineModel("zen1")
num_entries_csx = len(mm_csx["instruction_forms"])
num_entries_tx2 = len(mm_tx2["instruction_forms"])
num_entries_zen1 = len(mm_zen1["instruction_forms"])
mm_csx.set_instruction_entry(self.entry_csx)
mm_tx2.set_instruction_entry(self.entry_tx2)
mm_zen1.set_instruction_entry({'name': 'empty_operation'})
mm_zen1.set_instruction_entry({"name": "empty_operation"})
num_entries_csx = len(mm_csx['instruction_forms']) - num_entries_csx
num_entries_tx2 = len(mm_tx2['instruction_forms']) - num_entries_tx2
num_entries_zen1 = len(mm_zen1['instruction_forms']) - num_entries_zen1
num_entries_csx = len(mm_csx["instruction_forms"]) - num_entries_csx
num_entries_tx2 = len(mm_tx2["instruction_forms"]) - num_entries_tx2
num_entries_zen1 = len(mm_zen1["instruction_forms"]) - num_entries_zen1
self.assertEqual(num_entries_csx, 1)
self.assertEqual(num_entries_tx2, 1)
@@ -64,76 +64,76 @@ class TestDBInterface(unittest.TestCase):
def test_invalid_add(self):
entry = {}
with self.assertRaises(KeyError):
MachineModel('csx').set_instruction_entry(entry)
MachineModel("csx").set_instruction_entry(entry)
with self.assertRaises(TypeError):
MachineModel('csx').set_instruction()
MachineModel("csx").set_instruction()
def test_sanity_check(self):
output = StringIO()
# non-verbose
sanity_check('csx', verbose=False, internet_check=False, output_file=output)
sanity_check('tx2', verbose=False, internet_check=False, output_file=output)
sanity_check('zen1', verbose=False, internet_check=False, output_file=output)
sanity_check("csx", verbose=False, internet_check=False, output_file=output)
sanity_check("tx2", verbose=False, internet_check=False, output_file=output)
sanity_check("zen1", verbose=False, internet_check=False, output_file=output)
# verbose
sanity_check('csx', verbose=True, internet_check=False, output_file=output)
sanity_check('tx2', verbose=True, internet_check=False, output_file=output)
sanity_check('zen1', verbose=True, internet_check=False, output_file=output)
sanity_check("csx", verbose=True, internet_check=False, output_file=output)
sanity_check("tx2", verbose=True, internet_check=False, output_file=output)
sanity_check("zen1", verbose=True, internet_check=False, output_file=output)
def test_ibench_import(self):
# only check import without dumping the DB file (takes too much time)
with open(self._find_file('ibench_import_x86.dat')) as input_file:
with open(self._find_file("ibench_import_x86.dat")) as input_file:
input_data = input_file.readlines()
entries = dbi._get_ibench_output(input_data, 'x86')
entries = dbi._get_ibench_output(input_data, "x86")
self.assertEqual(len(entries), 3)
for _, e in entries.items():
self.assertIsNotNone(e['throughput'])
self.assertIsNotNone(e['latency'])
with open(self._find_file('ibench_import_aarch64.dat')) as input_file:
self.assertIsNotNone(e["throughput"])
self.assertIsNotNone(e["latency"])
with open(self._find_file("ibench_import_aarch64.dat")) as input_file:
input_data = input_file.readlines()
entries = dbi._get_ibench_output(input_data, 'aarch64')
entries = dbi._get_ibench_output(input_data, "aarch64")
self.assertEqual(len(entries), 4)
for _, e in entries.items():
self.assertIsNotNone(e['throughput'])
self.assertIsNotNone(e['latency'])
self.assertIsNotNone(e["throughput"])
self.assertIsNotNone(e["latency"])
def test_asmbench_import(self):
# only check import without dumping the DB file (takes too much time)
with open(self._find_file('asmbench_import_x86.dat')) as input_file:
with open(self._find_file("asmbench_import_x86.dat")) as input_file:
input_data = input_file.readlines()
entries = dbi._get_asmbench_output(input_data, 'x86')
entries = dbi._get_asmbench_output(input_data, "x86")
self.assertEqual(len(entries), 3)
for _, e in entries.items():
self.assertIsNotNone(e['throughput'])
self.assertIsNotNone(e['latency'])
with open(self._find_file('asmbench_import_aarch64.dat')) as input_file:
self.assertIsNotNone(e["throughput"])
self.assertIsNotNone(e["latency"])
with open(self._find_file("asmbench_import_aarch64.dat")) as input_file:
input_data = input_file.readlines()
entries = dbi._get_asmbench_output(input_data, 'aarch64')
entries = dbi._get_asmbench_output(input_data, "aarch64")
self.assertEqual(len(entries), 4)
for _, e in entries.items():
self.assertIsNotNone(e['throughput'])
self.assertIsNotNone(e['latency'])
self.assertIsNotNone(e["throughput"])
self.assertIsNotNone(e["latency"])
# remove empty line => no import since broken format
del input_data[3]
entries = dbi._get_asmbench_output(input_data, 'aarch64')
entries = dbi._get_asmbench_output(input_data, "aarch64")
self.assertEqual(len(entries), 0)
with self.assertRaises(ValueError):
dbi.import_benchmark_output(
'csx', 'invalid_bench_type', self._find_file('asmbench_import_x86.dat')
"csx", "invalid_bench_type", self._find_file("asmbench_import_x86.dat")
)
with self.assertRaises(AssertionError):
dbi.import_benchmark_output('csx', 'ibench', 'invalid_file')
dbi.import_benchmark_output("csx", "ibench", "invalid_file")
def test_online_scraping(self):
# addpd -- suspicious instruction, normal URL
instr_1 = ['addpd', (True, '(r) (r,w)')]
instr_1 = ["addpd", (True, "(r) (r,w)")]
self.assertEqual(dbi._scrape_from_felixcloutier(instr_1[0]), instr_1[1])
# movpd -- not suspicious,
instr_2 = ['movapd', (False, '(r) (w)')]
instr_2 = ["movapd", (False, "(r) (w)")]
self.assertEqual(dbi._scrape_from_felixcloutier(instr_2[0]), instr_2[1])
# vfmadd132pd -- only in combined view with 213/231.
# No 2-operand version, therefore, empty string
instr_3 = ['vfmadd132pd', (True, '')]
instr_3 = ["vfmadd132pd", (True, "")]
self.assertEqual(dbi._scrape_from_felixcloutier(instr_3[0]), instr_3[1])
##################
@@ -142,11 +142,11 @@ class TestDBInterface(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestDBInterface)
unittest.TextTestRunner(verbosity=2, buffer=True).run(suite)

32
tests/test_frontend.py
View File

@@ -13,7 +13,7 @@ from osaca.semantics import ArchSemantics, KernelDG, MachineModel
class TestFrontend(unittest.TestCase):
MODULE_DATA_DIR = os.path.join(
os.path.dirname(os.path.split(os.path.abspath(__file__))[0]), 'osaca/data/'
os.path.dirname(os.path.split(os.path.abspath(__file__))[0]), "osaca/data/"
)
@classmethod
@@ -21,26 +21,24 @@ class TestFrontend(unittest.TestCase):
# set up parser and kernels
self.parser_x86 = ParserX86ATT()
self.parser_AArch64 = ParserAArch64()
with open(self._find_file('kernel_x86.s')) as f:
with open(self._find_file("kernel_x86.s")) as f:
code_x86 = f.read()
with open(self._find_file('kernel_aarch64.s')) as f:
with open(self._find_file("kernel_aarch64.s")) as f:
code_AArch64 = f.read()
self.kernel_x86 = self.parser_x86.parse_file(code_x86)
self.kernel_AArch64 = self.parser_AArch64.parse_file(code_AArch64)
# set up machine models
self.machine_model_csx = MachineModel(
path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'csx.yml')
)
self.machine_model_tx2 = MachineModel(
arch='tx2'
path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml")
)
self.machine_model_tx2 = MachineModel(arch="tx2")
self.semantics_csx = ArchSemantics(
self.machine_model_csx, path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'isa/x86.yml')
self.machine_model_csx, path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "isa/x86.yml")
)
self.semantics_tx2 = ArchSemantics(
self.machine_model_tx2,
path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'isa/aarch64.yml'),
path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "isa/aarch64.yml"),
)
for i in range(len(self.kernel_x86)):
self.semantics_csx.assign_src_dst(self.kernel_x86[i])
@@ -57,23 +55,23 @@ class TestFrontend(unittest.TestCase):
with self.assertRaises(ValueError):
Frontend()
with self.assertRaises(ValueError):
Frontend(arch='csx', path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'csx.yml'))
Frontend(arch="csx", path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml"))
with self.assertRaises(FileNotFoundError):
Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'THE_MACHINE.yml'))
Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "THE_MACHINE.yml"))
with self.assertRaises(FileNotFoundError):
Frontend(arch='THE_MACHINE')
Frontend(arch='zen1')
Frontend(arch="THE_MACHINE")
Frontend(arch="zen1")
def test_frontend_x86(self):
dg = KernelDG(self.kernel_x86, self.parser_x86, self.machine_model_csx)
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'csx.yml'))
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml"))
fe.throughput_analysis(self.kernel_x86, show_cmnts=False)
fe.latency_analysis(dg.get_critical_path())
# TODO compare output with checked string
def test_frontend_AArch64(self):
dg = KernelDG(self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2)
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'tx2.yml'))
fe = Frontend(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "tx2.yml"))
fe.full_analysis(self.kernel_AArch64, dg, verbose=True)
# TODO compare output with checked string
@@ -84,11 +82,11 @@ class TestFrontend(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestFrontend)
unittest.TextTestRunner(verbosity=2).run(suite)

50
tests/test_kerncraftAPI.py
View File

@@ -18,9 +18,9 @@ class TestKerncraftAPI(unittest.TestCase):
# set up parser and kernels
self.parser_x86 = ParserX86ATT()
self.parser_AArch64 = ParserAArch64()
with open(self._find_file('triad_x86_iaca.s')) as f:
with open(self._find_file("triad_x86_iaca.s")) as f:
self.code_x86 = f.read()
with open(self._find_file('triad_arm_iaca.s')) as f:
with open(self._find_file("triad_arm_iaca.s")) as f:
self.code_AArch64 = f.read()
###########
@@ -28,23 +28,23 @@ class TestKerncraftAPI(unittest.TestCase):
###########
def test_kerncraft_API_x86(self):
kapi = KerncraftAPI('csx', self.code_x86)
kapi = KerncraftAPI("csx", self.code_x86)
kapi.create_output()
self.assertEqual(kapi.get_unmatched_instruction_ratio(), 0.0)
port_occupation = OrderedDict(
[
('0', 1.25),
('0DV', 0.0),
('1', 1.25),
('2', 2.0),
('2D', 1.5),
('3', 2.0),
('3D', 1.5),
('4', 1.0),
('5', 0.75),
('6', 0.75),
('7', 0.0),
("0", 1.25),
("0DV", 0.0),
("1", 1.25),
("2", 2.0),
("2D", 1.5),
("3", 2.0),
("3D", 1.5),
("4", 1.0),
("5", 0.75),
("6", 0.75),
("7", 0.0),
]
)
self.assertEqual(kapi.get_port_occupation_cycles(), port_occupation)
@@ -53,20 +53,20 @@ class TestKerncraftAPI(unittest.TestCase):
self.assertEqual(kapi.get_latency(), (1.0, 8.0))
def test_kerncraft_API_AArch64(self):
kapi = KerncraftAPI('tx2', self.code_AArch64)
kapi = KerncraftAPI("tx2", self.code_AArch64)
kapi.create_output()
self.assertEqual(kapi.get_unmatched_instruction_ratio(), 0.0)
port_occupation = OrderedDict(
[
('0', 34.0),
('0DV', 0.0),
('1', 34.0),
('1DV', 0.0),
('2', 3.0),
('3', 64.0),
('4', 64.0),
('5', 32.0),
("0", 34.0),
("0DV", 0.0),
("1", 34.0),
("1DV", 0.0),
("2", 3.0),
("3", 64.0),
("4", 64.0),
("5", 32.0),
]
)
self.assertEqual(kapi.get_port_occupation_cycles(), port_occupation)
@@ -81,11 +81,11 @@ class TestKerncraftAPI(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestKerncraftAPI)
unittest.TextTestRunner(verbosity=2).run(suite)

405
tests/test_marker_utils.py
View File

@@ -6,8 +6,12 @@ import os
import unittest
from collections import OrderedDict
from osaca.semantics import reduce_to_section, find_basic_blocks, find_jump_labels, \
find_basic_loop_bodies
from osaca.semantics import (
reduce_to_section,
find_basic_blocks,
find_jump_labels,
find_basic_loop_bodies,
)
from osaca.parser import ParserAArch64, ParserX86ATT
@@ -16,9 +20,9 @@ class TestMarkerUtils(unittest.TestCase):
def setUpClass(self):
self.parser_AArch = ParserAArch64()
self.parser_x86 = ParserX86ATT()
with open(self._find_file('triad_arm_iaca.s')) as f:
with open(self._find_file("triad_arm_iaca.s")) as f:
triad_code_arm = f.read()
with open(self._find_file('triad_x86_iaca.s')) as f:
with open(self._find_file("triad_x86_iaca.s")) as f:
triad_code_x86 = f.read()
self.parsed_AArch = self.parser_AArch.parse_file(triad_code_arm)
self.parsed_x86 = self.parser_x86.parse_file(triad_code_x86)
@@ -28,44 +32,44 @@ class TestMarkerUtils(unittest.TestCase):
#################
def test_marker_detection_AArch64(self):
kernel = reduce_to_section(self.parsed_AArch, 'AArch64')
kernel = reduce_to_section(self.parsed_AArch, "AArch64")
self.assertEqual(len(kernel), 138)
self.assertEqual(kernel[0].line_number, 307)
self.assertEqual(kernel[-1].line_number, 444)
def test_marker_detection_x86(self):
kernel = reduce_to_section(self.parsed_x86, 'x86')
kernel = reduce_to_section(self.parsed_x86, "x86")
self.assertEqual(len(kernel), 9)
self.assertEqual(kernel[0].line_number, 146)
self.assertEqual(kernel[-1].line_number, 154)
def test_marker_matching_AArch64(self):
# preparation
bytes_1_line = '.byte 213,3,32,31\n'
bytes_2_lines_1 = '.byte 213,3,32\n' + '.byte 31\n'
bytes_2_lines_2 = '.byte 213,3\n' + '.byte 32,31\n'
bytes_2_lines_3 = '.byte 213\n' + '.byte 3,32,31\n'
bytes_3_lines_1 = '.byte 213,3\n' + '.byte 32\n' + '.byte 31\n'
bytes_3_lines_2 = '.byte 213\n' + '.byte 3,32\n' + '.byte 31\n'
bytes_3_lines_3 = '.byte 213\n' + '.byte 3\n' + '.byte 32,31\n'
bytes_4_lines = '.byte 213\n' + '.byte 3\n' + '.byte 32\n' + '.byte 31\n'
mov_start_1 = 'mov x1, #111\n'
mov_start_2 = 'mov x1, 111 // should work as well\n'
mov_end_1 = 'mov x1, #222 // preferred way\n'
mov_end_2 = 'mov x1, 222\n'
bytes_1_line = ".byte 213,3,32,31\n"
bytes_2_lines_1 = ".byte 213,3,32\n" + ".byte 31\n"
bytes_2_lines_2 = ".byte 213,3\n" + ".byte 32,31\n"
bytes_2_lines_3 = ".byte 213\n" + ".byte 3,32,31\n"
bytes_3_lines_1 = ".byte 213,3\n" + ".byte 32\n" + ".byte 31\n"
bytes_3_lines_2 = ".byte 213\n" + ".byte 3,32\n" + ".byte 31\n"
bytes_3_lines_3 = ".byte 213\n" + ".byte 3\n" + ".byte 32,31\n"
bytes_4_lines = ".byte 213\n" + ".byte 3\n" + ".byte 32\n" + ".byte 31\n"
mov_start_1 = "mov x1, #111\n"
mov_start_2 = "mov x1, 111 // should work as well\n"
mov_end_1 = "mov x1, #222 // preferred way\n"
mov_end_2 = "mov x1, 222\n"
prologue = (
'mov x12, xzr\n'
+ '\tldp x9, x10, [sp, #16] // 8-byte Folded Reload\n'
+ ' .p2align 6\n'
"mov x12, xzr\n"
+ "\tldp x9, x10, [sp, #16] // 8-byte Folded Reload\n"
+ " .p2align 6\n"
)
kernel = (
'.LBB0_28:\n'
+ 'fmul v7.2d, v7.2d, v19.2d\n'
+ 'stp q0, q1, [x10, #-32]\n'
+ 'b.ne .LBB0_28\n'
".LBB0_28:\n"
+ "fmul v7.2d, v7.2d, v19.2d\n"
+ "stp q0, q1, [x10, #-32]\n"
+ "b.ne .LBB0_28\n"
)
epilogue = '.LBB0_29: // Parent Loop BB0_20 Depth=1\n' + 'bl dummy\n'
kernel_length = len(list(filter(None, kernel.split('\n'))))
epilogue = ".LBB0_29: // Parent Loop BB0_20 Depth=1\n" + "bl dummy\n"
kernel_length = len(list(filter(None, kernel.split("\n"))))
bytes_variations = [
bytes_1_line,
@@ -100,12 +104,12 @@ class TestMarkerUtils(unittest.TestCase):
bytes_end=bytes_var_2,
):
sample_parsed = self.parser_AArch.parse_file(sample_code)
sample_kernel = reduce_to_section(sample_parsed, 'AArch64')
sample_kernel = reduce_to_section(sample_parsed, "AArch64")
self.assertEqual(len(sample_kernel), kernel_length)
kernel_start = len(
list(
filter(
None, (prologue + mov_start_var + bytes_var_1).split('\n')
None, (prologue + mov_start_var + bytes_var_1).split("\n")
)
)
)
@@ -116,27 +120,27 @@ class TestMarkerUtils(unittest.TestCase):
def test_marker_matching_x86(self):
# preparation
bytes_1_line = '.byte 100,103,144\n'
bytes_2_lines_1 = '.byte 100,103\n' + '.byte 144\n'
bytes_2_lines_2 = '.byte 100\n' + '.byte 103,144\n'
bytes_1_line = ".byte 100,103,144\n"
bytes_2_lines_1 = ".byte 100,103\n" + ".byte 144\n"
bytes_2_lines_2 = ".byte 100\n" + ".byte 103,144\n"
bytes_3_lines = (
'.byte 100 # IACA MARKER UTILITY\n'
+ '.byte 103 # IACA MARKER UTILITY\n'
+ '.byte 144 # IACA MARKER UTILITY\n'
".byte 100 # IACA MARKER UTILITY\n"
+ ".byte 103 # IACA MARKER UTILITY\n"
+ ".byte 144 # IACA MARKER UTILITY\n"
)
mov_start_1 = 'movl $111, %ebx # IACA START\n'
mov_start_2 = 'mov $111, %ebx # IACA START\n'
mov_end_1 = 'movl $222, %ebx # IACA END\n'
mov_end_2 = 'mov $222, %ebx # IACA END\n'
prologue = 'movl -92(%rbp), %r11d\n' + 'movl $111, %ebx\n'
mov_start_1 = "movl $111, %ebx # IACA START\n"
mov_start_2 = "mov $111, %ebx # IACA START\n"
mov_end_1 = "movl $222, %ebx # IACA END\n"
mov_end_2 = "mov $222, %ebx # IACA END\n"
prologue = "movl -92(%rbp), %r11d\n" + "movl $111, %ebx\n"
kernel = (
'vfmadd132sd (%r15,%rcx,8), %xmm5, %xmm0\n'
+ 'vmovsd %xmm0, (%r14,%rcx,8)\n'
+ 'cmpl %ebx, %ecx\n'
+ 'jge .L8\n'
"vfmadd132sd (%r15,%rcx,8), %xmm5, %xmm0\n"
+ "vmovsd %xmm0, (%r14,%rcx,8)\n"
+ "cmpl %ebx, %ecx\n"
+ "jge .L8\n"
)
epilogue = '.LE9:\t\t#12.2\n' 'call dummy\n'
kernel_length = len(list(filter(None, kernel.split('\n'))))
epilogue = ".LE9:\t\t#12.2\n" "call dummy\n"
kernel_length = len(list(filter(None, kernel.split("\n"))))
bytes_variations = [bytes_1_line, bytes_2_lines_1, bytes_2_lines_2, bytes_3_lines]
mov_start_variations = [mov_start_1, mov_start_2]
@@ -162,12 +166,12 @@ class TestMarkerUtils(unittest.TestCase):
bytes_end=bytes_var_2,
):
sample_parsed = self.parser_x86.parse_file(sample_code)
sample_kernel = reduce_to_section(sample_parsed, 'x86')
sample_kernel = reduce_to_section(sample_parsed, "x86")
self.assertEqual(len(sample_kernel), kernel_length)
kernel_start = len(
list(
filter(
None, (prologue + mov_start_var + bytes_var_1).split('\n')
None, (prologue + mov_start_var + bytes_var_1).split("\n")
)
)
)
@@ -177,171 +181,250 @@ class TestMarkerUtils(unittest.TestCase):
self.assertEqual(sample_kernel, parsed_kernel)
def test_marker_special_cases_AArch(self):
bytes_line = '.byte 213,3,32,31\n'
start_marker = 'mov x1, #111\n' + bytes_line
end_marker = 'mov x1, #222\n' + bytes_line
prologue = (
'dup v0.2d, x14\n'
'neg x9, x9\n'
'.p2align 6\n')
bytes_line = ".byte 213,3,32,31\n"
start_marker = "mov x1, #111\n" + bytes_line
end_marker = "mov x1, #222\n" + bytes_line
prologue = "dup v0.2d, x14\n" "neg x9, x9\n" ".p2align 6\n"
kernel = (
'.LBB0_28:\n'
+ 'fmul v7.2d, v7.2d, v19.2d\n'
+ 'stp q0, q1, [x10, #-32]\n'
+ 'b.ne .LBB0_28\n')
epilogue = (
'.LBB0_29: // Parent Loop BB0_20 Depth=1\n'
'bl dummy\n')
".LBB0_28:\n"
+ "fmul v7.2d, v7.2d, v19.2d\n"
+ "stp q0, q1, [x10, #-32]\n"
+ "b.ne .LBB0_28\n"
)
epilogue = ".LBB0_29: // Parent Loop BB0_20 Depth=1\n" "bl dummy\n"
samples = [
# (test name,
# ignored prologue, section to be extraced, ignored epilogue)
("markers",
prologue + start_marker, kernel, end_marker + epilogue),
("marker at file start",
start_marker, kernel, end_marker + epilogue),
("no start marker",
'', prologue + kernel, end_marker + epilogue),
("marker at file end",
prologue + start_marker, kernel, end_marker),
("no end marker",
prologue + start_marker, kernel + epilogue, ''),
("empty kernel",
prologue + start_marker, '', end_marker + epilogue),
("markers", prologue + start_marker, kernel, end_marker + epilogue),
("marker at file start", start_marker, kernel, end_marker + epilogue),
("no start marker", "", prologue + kernel, end_marker + epilogue),
("marker at file end", prologue + start_marker, kernel, end_marker),
("no end marker", prologue + start_marker, kernel + epilogue, ""),
("empty kernel", prologue + start_marker, "", end_marker + epilogue),
]
for test_name, pro, kernel, epi in samples:
code = pro + kernel + epi
parsed = self.parser_AArch.parse_file(code)
test_kernel = reduce_to_section(parsed, 'AArch64')
test_kernel = reduce_to_section(parsed, "AArch64")
if kernel:
kernel_length = len(kernel.strip().split('\n'))
kernel_length = len(kernel.strip().split("\n"))
else:
kernel_length = 0
self.assertEqual(
len(test_kernel), kernel_length,
msg="Invalid exctracted kernel length on {!r} sample".format(test_name))
len(test_kernel),
kernel_length,
msg="Invalid exctracted kernel length on {!r} sample".format(test_name),
)
if pro:
kernel_start = len((pro).strip().split('\n'))
kernel_start = len((pro).strip().split("\n"))
else:
kernel_start = 0
parsed_kernel = self.parser_AArch.parse_file(kernel, start_line=kernel_start)
self.assertEqual(
test_kernel, parsed_kernel,
msg="Invalid exctracted kernel on {!r}".format(test_name))
test_kernel,
parsed_kernel,
msg="Invalid exctracted kernel on {!r}".format(test_name),
)
def test_marker_special_cases_x86(self):
bytes_line = (
'.byte 100\n'
'.byte 103\n'
'.byte 144\n')
start_marker = 'movl $111, %ebx\n' + bytes_line
end_marker = 'movl $222, %ebx\n' + bytes_line
prologue = (
'movl -88(%rbp), %r10d\n'
'xorl %r11d, %r11d\n'
'.p2align 4,,10\n')
bytes_line = ".byte 100\n" ".byte 103\n" ".byte 144\n"
start_marker = "movl $111, %ebx\n" + bytes_line
end_marker = "movl $222, %ebx\n" + bytes_line
prologue = "movl -88(%rbp), %r10d\n" "xorl %r11d, %r11d\n" ".p2align 4,,10\n"
kernel = (
'.L3: #L3\n'
'vmovsd .LC1(%rip), %xmm0\n'
'vmovsd %xmm0, (%r15,%rcx,8)\n'
'cmpl %ecx, %ebx\n'
'jle .L3\n')
epilogue = (
'leaq -56(%rbp), %rsi\n'
'movl %r10d, -88(%rbp)\n'
'call timing\n')
".L3: #L3\n"
"vmovsd .LC1(%rip), %xmm0\n"
"vmovsd %xmm0, (%r15,%rcx,8)\n"
"cmpl %ecx, %ebx\n"
"jle .L3\n"
)
epilogue = "leaq -56(%rbp), %rsi\n" "movl %r10d, -88(%rbp)\n" "call timing\n"
samples = [
# (test name,
# ignored prologue, section to be extraced, ignored epilogue)
("markers",
prologue + start_marker, kernel, end_marker + epilogue),
("marker at file start",
start_marker, kernel, end_marker + epilogue),
("no start marker",
'', prologue + kernel, end_marker + epilogue),
("marker at file end",
prologue + start_marker, kernel, end_marker),
("no end marker",
prologue + start_marker, kernel + epilogue, ''),
("empty kernel",
prologue + start_marker, '', end_marker + epilogue),
("markers", prologue + start_marker, kernel, end_marker + epilogue),
("marker at file start", start_marker, kernel, end_marker + epilogue),
("no start marker", "", prologue + kernel, end_marker + epilogue),
("marker at file end", prologue + start_marker, kernel, end_marker),
("no end marker", prologue + start_marker, kernel + epilogue, ""),
("empty kernel", prologue + start_marker, "", end_marker + epilogue),
]
for test_name, pro, kernel, epi in samples:
code = pro + kernel + epi
parsed = self.parser_x86.parse_file(code)
test_kernel = reduce_to_section(parsed, 'x86')
test_kernel = reduce_to_section(parsed, "x86")
if kernel:
kernel_length = len(kernel.strip().split('\n'))
kernel_length = len(kernel.strip().split("\n"))
else:
kernel_length = 0
self.assertEqual(
len(test_kernel), kernel_length,
msg="Invalid exctracted kernel length on {!r} sample".format(test_name))
len(test_kernel),
kernel_length,
msg="Invalid exctracted kernel length on {!r} sample".format(test_name),
)
if pro:
kernel_start = len((pro).strip().split('\n'))
kernel_start = len((pro).strip().split("\n"))
else:
kernel_start = 0
parsed_kernel = self.parser_x86.parse_file(kernel, start_line=kernel_start)
self.assertEqual(
test_kernel, parsed_kernel,
msg="Invalid exctracted kernel on {!r}".format(test_name))
test_kernel,
parsed_kernel,
msg="Invalid exctracted kernel on {!r}".format(test_name),
)
def test_find_jump_labels(self):
self.assertEqual(find_jump_labels(self.parsed_x86),
OrderedDict([('.LFB24', 10), ('.L4', 65), ('.L3', 79), ('.L2', 102),
('.L13', 111), ('.L12', 120), ('.L6', 132), ('.L10', 145),
('.L9', 161), ('.L8', 183), ('.L15', 252), ('.L26', 256),
('.L14', 259), ('.LFB25', 277), ('.L28', 289)]))
self.assertEqual(
find_jump_labels(self.parsed_x86),
OrderedDict(
[
(".LFB24", 10),
(".L4", 65),
(".L3", 79),
(".L2", 102),
(".L13", 111),
(".L12", 120),
(".L6", 132),
(".L10", 145),
(".L9", 161),
(".L8", 183),
(".L15", 252),
(".L26", 256),
(".L14", 259),
(".LFB25", 277),
(".L28", 289),
]
),
)
self.assertEqual(
find_jump_labels(self.parsed_AArch),
OrderedDict([('triad', 18), ('.LBB0_3', 71), ('.LBB0_4', 76), ('.LBB0_5', 84),
('.LBB0_7', 92), ('.LBB0_8', 95), ('.LBB0_9', 106), ('.LBB0_11', 118),
('.LBB0_12', 133), ('.LBB0_14', 177), ('.LBB0_15', 190),
('.LBB0_16', 205), ('.LBB0_17', 208), ('.LBB0_18', 221),
('.LBB0_19', 228), ('.LBB0_20', 260), ('.LBB0_22', 272),
('.LBB0_24', 283), ('.LBB0_26', 290), ('.LBB0_28', 298),
('.LBB0_29', 306), ('.LBB0_31', 448), ('.LBB0_32', 458),
('.LBB0_33', 480), ('.LBB0_34', 484), ('.LBB0_35', 493),
('.LBB0_36', 504), ('.LBB0_37', 508), ('.LBB0_38', 518),
('main', 574)]))
OrderedDict(
[
("triad", 18),
(".LBB0_3", 71),
(".LBB0_4", 76),
(".LBB0_5", 84),
(".LBB0_7", 92),
(".LBB0_8", 95),
(".LBB0_9", 106),
(".LBB0_11", 118),
(".LBB0_12", 133),
(".LBB0_14", 177),
(".LBB0_15", 190),
(".LBB0_16", 205),
(".LBB0_17", 208),
(".LBB0_18", 221),
(".LBB0_19", 228),
(".LBB0_20", 260),
(".LBB0_22", 272),
(".LBB0_24", 283),
(".LBB0_26", 290),
(".LBB0_28", 298),
(".LBB0_29", 306),
(".LBB0_31", 448),
(".LBB0_32", 458),
(".LBB0_33", 480),
(".LBB0_34", 484),
(".LBB0_35", 493),
(".LBB0_36", 504),
(".LBB0_37", 508),
(".LBB0_38", 518),
("main", 574),
]
),
)
def test_find_basic_blocks(self):
self.assertEqual(
[(k, v[0]['line_number'], v[-1]['line_number'])
for k, v in find_basic_blocks(self.parsed_x86).items()],
[('.LFB24', 11, 56), ('.L4', 66, 74), ('.L3', 80, 89), ('.L2', 103, 112),
('.L13', 112, 121), ('.L12', 121, 125), ('.L6', 133, 135), ('.L10', 146, 154),
('.L9', 162, 170), ('.L8', 184, 187), ('.L15', 253, 256), ('.L26', 257, 259),
('.L14', 260, 262), ('.LFB25', 278, 290), ('.L28', 290, 300)])
[
(k, v[0]["line_number"], v[-1]["line_number"])
for k, v in find_basic_blocks(self.parsed_x86).items()
],
[
(".LFB24", 11, 56),
(".L4", 66, 74),
(".L3", 80, 89),
(".L2", 103, 112),
(".L13", 112, 121),
(".L12", 121, 125),
(".L6", 133, 135),
(".L10", 146, 154),
(".L9", 162, 170),
(".L8", 184, 187),
(".L15", 253, 256),
(".L26", 257, 259),
(".L14", 260, 262),
(".LFB25", 278, 290),
(".L28", 290, 300),
],
)
self.assertEqual(
[(k, v[0]['line_number'], v[-1]['line_number'])
for k, v in find_basic_blocks(self.parsed_AArch).items()],
[('triad', 19, 64), ('.LBB0_3', 72, 77), ('.LBB0_4', 77, 83), ('.LBB0_5', 85, 89),
('.LBB0_7', 93, 95), ('.LBB0_8', 96, 105), ('.LBB0_9', 107, 114),
('.LBB0_11', 119, 134), ('.LBB0_12', 134, 173), ('.LBB0_14', 178, 191),
('.LBB0_15', 191, 205), ('.LBB0_16', 206, 208), ('.LBB0_17', 209, 222),
('.LBB0_18', 222, 228), ('.LBB0_19', 229, 261), ('.LBB0_20', 261, 269),
('.LBB0_22', 273, 280), ('.LBB0_24', 284, 286), ('.LBB0_26', 291, 293),
('.LBB0_28', 299, 307), ('.LBB0_29', 307, 444), ('.LBB0_31', 449, 459),
('.LBB0_32', 459, 480), ('.LBB0_33', 481, 484), ('.LBB0_34', 485, 494),
('.LBB0_35', 494, 504), ('.LBB0_36', 505, 508), ('.LBB0_37', 509, 518),
('.LBB0_38', 519, 568), ('main', 575, 590)])
[
(k, v[0]["line_number"], v[-1]["line_number"])
for k, v in find_basic_blocks(self.parsed_AArch).items()
],
[
("triad", 19, 64),
(".LBB0_3", 72, 77),
(".LBB0_4", 77, 83),
(".LBB0_5", 85, 89),
(".LBB0_7", 93, 95),
(".LBB0_8", 96, 105),
(".LBB0_9", 107, 114),
(".LBB0_11", 119, 134),
(".LBB0_12", 134, 173),
(".LBB0_14", 178, 191),
(".LBB0_15", 191, 205),
(".LBB0_16", 206, 208),
(".LBB0_17", 209, 222),
(".LBB0_18", 222, 228),
(".LBB0_19", 229, 261),
(".LBB0_20", 261, 269),
(".LBB0_22", 273, 280),
(".LBB0_24", 284, 286),
(".LBB0_26", 291, 293),
(".LBB0_28", 299, 307),
(".LBB0_29", 307, 444),
(".LBB0_31", 449, 459),
(".LBB0_32", 459, 480),
(".LBB0_33", 481, 484),
(".LBB0_34", 485, 494),
(".LBB0_35", 494, 504),
(".LBB0_36", 505, 508),
(".LBB0_37", 509, 518),
(".LBB0_38", 519, 568),
("main", 575, 590),
],
)
def test_find_basic_loop_body(self):
self.assertEqual(
[(k, v[0]['line_number'], v[-1]['line_number'])
for k, v in find_basic_loop_bodies(self.parsed_x86).items()],
[('.L4', 66, 74), ('.L10', 146, 154), ('.L28', 290, 300)])
[
(k, v[0]["line_number"], v[-1]["line_number"])
for k, v in find_basic_loop_bodies(self.parsed_x86).items()
],
[(".L4", 66, 74), (".L10", 146, 154), (".L28", 290, 300)],
)
self.assertEqual(
[(k, v[0]['line_number'], v[-1]['line_number'])
for k, v in find_basic_loop_bodies(self.parsed_AArch).items()],
[('.LBB0_12', 134, 173), ('.LBB0_15', 191, 205), ('.LBB0_18', 222, 228),
('.LBB0_29', 307, 444), ('.LBB0_32', 459, 480), ('.LBB0_35', 494, 504)])
[
(k, v[0]["line_number"], v[-1]["line_number"])
for k, v in find_basic_loop_bodies(self.parsed_AArch).items()
],
[
(".LBB0_12", 134, 173),
(".LBB0_15", 191, 205),
(".LBB0_18", 222, 228),
(".LBB0_29", 307, 444),
(".LBB0_32", 459, 480),
(".LBB0_35", 494, 504),
],
)
##################
# Helper functions
@@ -350,11 +433,11 @@ class TestMarkerUtils(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestMarkerUtils)
unittest.TextTestRunner(verbosity=2).run(suite)

445
tests/test_parser_AArch64.py
View File

@@ -15,7 +15,7 @@ class TestParserAArch64(unittest.TestCase):
@classmethod
def setUpClass(self):
self.parser = ParserAArch64()
with open(self._find_file('triad_arm_iaca.s')) as f:
with open(self._find_file("triad_arm_iaca.s")) as f:
self.triad_code = f.read()
##################
@@ -23,63 +23,61 @@ class TestParserAArch64(unittest.TestCase):
##################
def test_comment_parser(self):
self.assertEqual(self._get_comment(self.parser, '// some comments'), 'some comments')
self.assertEqual(self._get_comment(self.parser, "// some comments"), "some comments")
self.assertEqual(self._get_comment(self.parser, "\t\t//AA BB CC \t end \t"), "AA BB CC end")
self.assertEqual(
self._get_comment(self.parser, '\t\t//AA BB CC \t end \t'), 'AA BB CC end'
)
self.assertEqual(
self._get_comment(self.parser, '\t//// comment //// comment'),
'// comment //// comment',
self._get_comment(self.parser, "\t//// comment //// comment"),
"// comment //// comment",
)
def test_label_parser(self):
self.assertEqual(self._get_label(self.parser, 'main:').name, 'main')
self.assertEqual(self._get_label(self.parser, '..B1.10:').name, '..B1.10')
self.assertEqual(self._get_label(self.parser, '.2.3_2_pack.3:').name, '.2.3_2_pack.3')
self.assertEqual(self._get_label(self.parser, '.L1:\t\t\t//label1').name, '.L1')
self.assertEqual(self._get_label(self.parser, "main:").name, "main")
self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1").name, ".L1")
self.assertEqual(
' '.join(self._get_label(self.parser, '.L1:\t\t\t//label1').comment), 'label1'
" ".join(self._get_label(self.parser, ".L1:\t\t\t//label1").comment), "label1"
)
with self.assertRaises(ParseException):
self._get_label(self.parser, '\t.cfi_startproc')
self._get_label(self.parser, "\t.cfi_startproc")
def test_directive_parser(self):
self.assertEqual(self._get_directive(self.parser, '\t.text').name, 'text')
self.assertEqual(len(self._get_directive(self.parser, '\t.text').parameters), 0)
self.assertEqual(self._get_directive(self.parser, '\t.align\t16,0x90').name, 'align')
self.assertEqual(len(self._get_directive(self.parser, '\t.align\t16,0x90').parameters), 2)
self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
self.assertEqual(
self._get_directive(self.parser, '\t.align\t16,0x90').parameters[1], '0x90'
self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
)
self.assertEqual(
self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
'name'
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
"name"
],
'byte',
"byte",
)
self.assertEqual(
self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
'parameters'
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
"parameters"
][2],
'144',
"144",
)
self.assertEqual(
' '.join(
self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
'comment'
" ".join(
self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
"comment"
]
),
'IACA START',
"IACA START",
)
def test_parse_instruction(self):
instr1 = '\t\tvcvt.F32.S32 w1, w2\t\t\t//12.27'
instr2 = 'b.lo ..B1.4 \t'
instr3 = ' mov x2,#0x222 //NOT IACA END'
instr4 = 'str x28, [sp, x1, lsl #4] //12.9'
instr5 = 'ldr x0, [x0, #:got_lo12:q2c]'
instr6 = 'adrp x0, :got:visited'
instr7 = 'fadd v17.2d, v16.2d, v1.2d'
instr1 = "\t\tvcvt.F32.S32 w1, w2\t\t\t//12.27"
instr2 = "b.lo ..B1.4 \t"
instr3 = " mov x2,#0x222 //NOT IACA END"
instr4 = "str x28, [sp, x1, lsl #4] //12.9"
instr5 = "ldr x0, [x0, #:got_lo12:q2c]"
instr6 = "adrp x0, :got:visited"
instr7 = "fadd v17.2d, v16.2d, v1.2d"
parsed_1 = self.parser.parse_instruction(instr1)
parsed_2 = self.parser.parse_instruction(instr2)
@@ -89,198 +87,196 @@ class TestParserAArch64(unittest.TestCase):
parsed_6 = self.parser.parse_instruction(instr6)
parsed_7 = self.parser.parse_instruction(instr7)
self.assertEqual(parsed_1.instruction, 'vcvt.F32.S32')
self.assertEqual(parsed_1.operands[0].register.name, '1')
self.assertEqual(parsed_1.operands[0].register.prefix, 'w')
self.assertEqual(parsed_1.operands[1].register.name, '2')
self.assertEqual(parsed_1.operands[1].register.prefix, 'w')
self.assertEqual(parsed_1.comment, '12.27')
self.assertEqual(parsed_1.instruction, "vcvt.F32.S32")
self.assertEqual(parsed_1.operands[0].register.name, "1")
self.assertEqual(parsed_1.operands[0].register.prefix, "w")
self.assertEqual(parsed_1.operands[1].register.name, "2")
self.assertEqual(parsed_1.operands[1].register.prefix, "w")
self.assertEqual(parsed_1.comment, "12.27")
self.assertEqual(parsed_2.instruction, 'b.lo')
self.assertEqual(parsed_2.operands[0].identifier.name, '..B1.4')
self.assertEqual(parsed_2.instruction, "b.lo")
self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4")
self.assertEqual(len(parsed_2.operands), 1)
self.assertIsNone(parsed_2.comment)
self.assertEqual(parsed_3.instruction, 'mov')
self.assertEqual(parsed_3.operands[0].register.name, '2')
self.assertEqual(parsed_3.operands[0].register.prefix, 'x')
self.assertEqual(parsed_3.operands[1].immediate.value, '0x222')
self.assertEqual(parsed_3.comment, 'NOT IACA END')
self.assertEqual(parsed_3.instruction, "mov")
self.assertEqual(parsed_3.operands[0].register.name, "2")
self.assertEqual(parsed_3.operands[0].register.prefix, "x")
self.assertEqual(parsed_3.operands[1].immediate.value, "0x222")
self.assertEqual(parsed_3.comment, "NOT IACA END")
self.assertEqual(parsed_4.instruction, 'str')
self.assertEqual(parsed_4.instruction, "str")
self.assertIsNone(parsed_4.operands[1].memory.offset)
self.assertEqual(parsed_4.operands[1].memory.base.name, 'sp')
self.assertEqual(parsed_4.operands[1].memory.base.prefix, 'x')
self.assertEqual(parsed_4.operands[1].memory.index.name, '1')
self.assertEqual(parsed_4.operands[1].memory.index.prefix, 'x')
self.assertEqual(parsed_4.operands[1].memory.base.name, "sp")
self.assertEqual(parsed_4.operands[1].memory.base.prefix, "x")
self.assertEqual(parsed_4.operands[1].memory.index.name, "1")
self.assertEqual(parsed_4.operands[1].memory.index.prefix, "x")
self.assertEqual(parsed_4.operands[1].memory.scale, 16)
self.assertEqual(parsed_4.operands[0].register.name, '28')
self.assertEqual(parsed_4.operands[0].register.prefix, 'x')
self.assertEqual(parsed_4.comment, '12.9')
self.assertEqual(parsed_4.operands[0].register.name, "28")
self.assertEqual(parsed_4.operands[0].register.prefix, "x")
self.assertEqual(parsed_4.comment, "12.9")
self.assertEqual(parsed_5.instruction, 'ldr')
self.assertEqual(parsed_5.operands[0].register.name, '0')
self.assertEqual(parsed_5.operands[0].register.prefix, 'x')
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, 'q2c')
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation,
':got_lo12:')
self.assertEqual(parsed_5.operands[1].memory.base.name, '0')
self.assertEqual(parsed_5.operands[1].memory.base.prefix, 'x')
self.assertEqual(parsed_5.instruction, "ldr")
self.assertEqual(parsed_5.operands[0].register.name, "0")
self.assertEqual(parsed_5.operands[0].register.prefix, "x")
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "q2c")
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation, ":got_lo12:")
self.assertEqual(parsed_5.operands[1].memory.base.name, "0")
self.assertEqual(parsed_5.operands[1].memory.base.prefix, "x")
self.assertIsNone(parsed_5.operands[1].memory.index)
self.assertEqual(parsed_5.operands[1].memory.scale, 1)
self.assertEqual(parsed_6.instruction, 'adrp')
self.assertEqual(parsed_6.operands[0].register.name, '0')
self.assertEqual(parsed_6.operands[0].register.prefix, 'x')
self.assertEqual(parsed_6.operands[1].identifier.relocation, ':got:')
self.assertEqual(parsed_6.operands[1].identifier.name, 'visited')
self.assertEqual(parsed_6.instruction, "adrp")
self.assertEqual(parsed_6.operands[0].register.name, "0")
self.assertEqual(parsed_6.operands[0].register.prefix, "x")
self.assertEqual(parsed_6.operands[1].identifier.relocation, ":got:")
self.assertEqual(parsed_6.operands[1].identifier.name, "visited")
self.assertEqual(parsed_7.instruction, 'fadd')
self.assertEqual(parsed_7.operands[0].register.name, '17')
self.assertEqual(parsed_7.operands[0].register.prefix, 'v')
self.assertEqual(parsed_7.operands[0].register.lanes, '2')
self.assertEqual(parsed_7.operands[0].register.shape, 'd')
self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register),
'v1.2d')
self.assertEqual(parsed_7.instruction, "fadd")
self.assertEqual(parsed_7.operands[0].register.name, "17")
self.assertEqual(parsed_7.operands[0].register.prefix, "v")
self.assertEqual(parsed_7.operands[0].register.lanes, "2")
self.assertEqual(parsed_7.operands[0].register.shape, "d")
self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register), "v1.2d")
def test_parse_line(self):
line_comment = '// -- Begin main'
line_label = '.LBB0_1: // =>This Inner Loop Header: Depth=1'
line_directive = '.cfi_def_cfa w29, -16'
line_instruction = 'ldr s0, [x11, w10, sxtw #2] // = <<2'
line_prefetch = 'prfm pldl1keep, [x26, #2048] //HPL'
line_preindexed = 'stp x29, x30, [sp, #-16]!'
line_postindexed = 'ldp q2, q3, [x11], #64'
line_5_operands = 'fcmla z26.d, p0/m, z29.d, z21.d, #90'
line_comment = "// -- Begin main"
line_label = ".LBB0_1: // =>This Inner Loop Header: Depth=1"
line_directive = ".cfi_def_cfa w29, -16"
line_instruction = "ldr s0, [x11, w10, sxtw #2] // = <<2"
line_prefetch = "prfm pldl1keep, [x26, #2048] //HPL"
line_preindexed = "stp x29, x30, [sp, #-16]!"
line_postindexed = "ldp q2, q3, [x11], #64"
line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90"
instruction_form_1 = {
'instruction': None,
'operands': [],
'directive': None,
'comment': '-- Begin main',
'label': None,
'line': '// -- Begin main',
'line_number': 1,
"instruction": None,
"operands": [],
"directive": None,
"comment": "-- Begin main",
"label": None,
"line": "// -- Begin main",
"line_number": 1,
}
instruction_form_2 = {
'instruction': None,
'operands': [],
'directive': None,
'comment': '=>This Inner Loop Header: Depth=1',
'label': '.LBB0_1',
'line': '.LBB0_1: // =>This Inner Loop Header: Depth=1',
'line_number': 2,
"instruction": None,
"operands": [],
"directive": None,
"comment": "=>This Inner Loop Header: Depth=1",
"label": ".LBB0_1",
"line": ".LBB0_1: // =>This Inner Loop Header: Depth=1",
"line_number": 2,
}
instruction_form_3 = {
'instruction': None,
'operands': [],
'directive': {'name': 'cfi_def_cfa', 'parameters': ['w29', '-16']},
'comment': None,
'label': None,
'line': '.cfi_def_cfa w29, -16',
'line_number': 3,
"instruction": None,
"operands": [],
"directive": {"name": "cfi_def_cfa", "parameters": ["w29", "-16"]},
"comment": None,
"label": None,
"line": ".cfi_def_cfa w29, -16",
"line_number": 3,
}
instruction_form_4 = {
'instruction': 'ldr',
'operands': [
{'register': {'prefix': 's', 'name': '0'}},
"instruction": "ldr",
"operands": [
{"register": {"prefix": "s", "name": "0"}},
{
'memory': {
'offset': None,
'base': {'prefix': 'x', 'name': '11'},
'index': {
'prefix': 'w',
'name': '10',
'shift_op': 'sxtw',
'immediate': {'value': '2'},
'shift': [{'value': '2'}],
"memory": {
"offset": None,
"base": {"prefix": "x", "name": "11"},
"index": {
"prefix": "w",
"name": "10",
"shift_op": "sxtw",
"immediate": {"value": "2"},
"shift": [{"value": "2"}],
},
'scale': 4,
"scale": 4,
}
},
],
'directive': None,
'comment': '= <<2',
'label': None,
'line': 'ldr s0, [x11, w10, sxtw #2] // = <<2',
'line_number': 4,
"directive": None,
"comment": "= <<2",
"label": None,
"line": "ldr s0, [x11, w10, sxtw #2] // = <<2",
"line_number": 4,
}
instruction_form_5 = {
'instruction': 'prfm',
'operands': [
{'prfop': {'type': ['PLD'], 'target': ['L1'], 'policy': ['KEEP']}},
"instruction": "prfm",
"operands": [
{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
{
'memory': {
'offset': {'value': '2048'},
'base': {'prefix': 'x', 'name': '26'},
'index': None,
'scale': 1,
"memory": {
"offset": {"value": "2048"},
"base": {"prefix": "x", "name": "26"},
"index": None,
"scale": 1,
}
},
],
'directive': None,
'comment': 'HPL',
'label': None,
'line': 'prfm pldl1keep, [x26, #2048] //HPL',
'line_number': 5,
"directive": None,
"comment": "HPL",
"label": None,
"line": "prfm pldl1keep, [x26, #2048] //HPL",
"line_number": 5,
}
instruction_form_6 = {
'instruction': 'stp',
'operands': [
{'register': {'prefix': 'x', 'name': '29'}},
{'register': {'prefix': 'x', 'name': '30'}},
"instruction": "stp",
"operands": [
{"register": {"prefix": "x", "name": "29"}},
{"register": {"prefix": "x", "name": "30"}},
{
'memory': {
'offset': {'value': '-16'},
'base': {'name': 'sp', 'prefix': 'x'},
'index': None,
'scale': 1,
'pre_indexed': True,
"memory": {
"offset": {"value": "-16"},
"base": {"name": "sp", "prefix": "x"},
"index": None,
"scale": 1,
"pre_indexed": True,
}
},
],
'directive': None,
'comment': None,
'label': None,
'line': 'stp x29, x30, [sp, #-16]!',
'line_number': 6,
"directive": None,
"comment": None,
"label": None,
"line": "stp x29, x30, [sp, #-16]!",
"line_number": 6,
}
instruction_form_7 = {
'instruction': 'ldp',
'operands': [
{'register': {'prefix': 'q', 'name': '2'}},
{'register': {'prefix': 'q', 'name': '3'}},
"instruction": "ldp",
"operands": [
{"register": {"prefix": "q", "name": "2"}},
{"register": {"prefix": "q", "name": "3"}},
{
'memory': {
'offset': None,
'base': {'prefix': 'x', 'name': '11'},
'index': None,
'scale': 1,
'post_indexed': {'value': '64'},
"memory": {
"offset": None,
"base": {"prefix": "x", "name": "11"},
"index": None,
"scale": 1,
"post_indexed": {"value": "64"},
}
},
],
'directive': None,
'comment': None,
'label': None,
'line': 'ldp q2, q3, [x11], #64',
'line_number': 7,
"directive": None,
"comment": None,
"label": None,
"line": "ldp q2, q3, [x11], #64",
"line_number": 7,
}
instruction_form_8 = {
'instruction': 'fcmla',
'operands': [
{'register': {'prefix': 'z', 'name': '26', 'shape': 'd'}},
{'register': {'prefix': 'p', 'name': '0', 'predication': 'm'}},
{'register': {'prefix': 'z', 'name': '29', 'shape': 'd'}},
{'register': {'prefix': 'z', 'name': '21', 'shape': 'd'}},
{'immediate': {'value': '90'}},
"instruction": "fcmla",
"operands": [
{"register": {"prefix": "z", "name": "26", "shape": "d"}},
{"register": {"prefix": "p", "name": "0", "predication": "m"}},
{"register": {"prefix": "z", "name": "29", "shape": "d"}},
{"register": {"prefix": "z", "name": "21", "shape": "d"}},
{"immediate": {"value": "90"}},
],
'directive': None,
'comment': None,
'label': None,
'line': 'fcmla z26.d, p0/m, z29.d, z21.d, #90',
'line_number': 8,
"directive": None,
"comment": None,
"label": None,
"line": "fcmla z26.d, p0/m, z29.d, z21.d, #90",
"line_number": 8,
}
parsed_1 = self.parser.parse_line(line_comment, 1)
@@ -307,15 +303,15 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(len(parsed), 645)
def test_normalize_imd(self):
imd_decimal_1 = {'value': '79'}
imd_hex_1 = {'value': '0x4f'}
imd_decimal_2 = {'value': '8'}
imd_hex_2 = {'value': '0x8'}
imd_float_11 = {'float': {'mantissa': '0.79', 'e_sign': '+', 'exponent': '2'}}
imd_float_12 = {'float': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
imd_double_11 = {'double': {'mantissa': '0.79', 'e_sign': '+', 'exponent': '2'}}
imd_double_12 = {'double': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
identifier = {'identifier': {'name': '..B1.4'}}
imd_decimal_1 = {"value": "79"}
imd_hex_1 = {"value": "0x4f"}
imd_decimal_2 = {"value": "8"}
imd_hex_2 = {"value": "0x8"}
imd_float_11 = {"float": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
imd_float_12 = {"float": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
imd_double_11 = {"double": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
imd_double_12 = {"double": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
identifier = {"identifier": {"name": "..B1.4"}}
value1 = self.parser.normalize_imd(imd_decimal_1)
self.assertEqual(value1, self.parser.normalize_imd(imd_hex_1))
@@ -329,27 +325,28 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(self.parser.normalize_imd(identifier), identifier)
def test_multiple_regs(self):
instr_range = 'PUSH {x5-x7}'
reg_range = AttrDict({
'register': {
'range': [
{'prefix': 'x', 'name': '5'},
{'prefix': 'x', 'name': '7'}
],
'index': None
instr_range = "PUSH {x5-x7}"
reg_range = AttrDict(
{
"register": {
"range": [{"prefix": "x", "name": "5"}, {"prefix": "x", "name": "7"}],
"index": None,
}
}
})
instr_list = 'POP {x5, x7, x9}'
reg_list = AttrDict({
'register': {
'list': [
{'prefix': 'x', 'name': '5'},
{'prefix': 'x', 'name': '7'},
{'prefix': 'x', 'name': '9'}
],
'index': None
)
instr_list = "POP {x5, x7, x9}"
reg_list = AttrDict(
{
"register": {
"list": [
{"prefix": "x", "name": "5"},
{"prefix": "x", "name": "7"},
{"prefix": "x", "name": "9"},
],
"index": None,
}
}
})
)
prange = self.parser.parse_line(instr_range)
plist = self.parser.parse_line(instr_list)
@@ -357,22 +354,22 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(plist.operands[0], reg_list)
def test_reg_dependency(self):
reg_1_1 = AttrDict({'prefix': 'b', 'name': '1'})
reg_1_2 = AttrDict({'prefix': 'h', 'name': '1'})
reg_1_3 = AttrDict({'prefix': 's', 'name': '1'})
reg_1_4 = AttrDict({'prefix': 'd', 'name': '1'})
reg_1_4 = AttrDict({'prefix': 'q', 'name': '1'})
reg_2_1 = AttrDict({'prefix': 'w', 'name': '2'})
reg_2_2 = AttrDict({'prefix': 'x', 'name': '2'})
reg_v1_1 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '16', 'shape': 'b'})
reg_v1_2 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '8', 'shape': 'h'})
reg_v1_3 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '4', 'shape': 's'})
reg_v1_4 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '2', 'shape': 'd'})
reg_1_1 = AttrDict({"prefix": "b", "name": "1"})
reg_1_2 = AttrDict({"prefix": "h", "name": "1"})
reg_1_3 = AttrDict({"prefix": "s", "name": "1"})
reg_1_4 = AttrDict({"prefix": "d", "name": "1"})
reg_1_4 = AttrDict({"prefix": "q", "name": "1"})
reg_2_1 = AttrDict({"prefix": "w", "name": "2"})
reg_2_2 = AttrDict({"prefix": "x", "name": "2"})
reg_v1_1 = AttrDict({"prefix": "v", "name": "11", "lanes": "16", "shape": "b"})
reg_v1_2 = AttrDict({"prefix": "v", "name": "11", "lanes": "8", "shape": "h"})
reg_v1_3 = AttrDict({"prefix": "v", "name": "11", "lanes": "4", "shape": "s"})
reg_v1_4 = AttrDict({"prefix": "v", "name": "11", "lanes": "2", "shape": "d"})
reg_b5 = AttrDict({'prefix': 'b', 'name': '5'})
reg_q15 = AttrDict({'prefix': 'q', 'name': '15'})
reg_v10 = AttrDict({'prefix': 'v', 'name': '10', 'lanes': '2', 'shape': 's'})
reg_v20 = AttrDict({'prefix': 'v', 'name': '20', 'lanes': '2', 'shape': 'd'})
reg_b5 = AttrDict({"prefix": "b", "name": "5"})
reg_q15 = AttrDict({"prefix": "q", "name": "15"})
reg_v10 = AttrDict({"prefix": "v", "name": "10", "lanes": "2", "shape": "s"})
reg_v20 = AttrDict({"prefix": "v", "name": "20", "lanes": "2", "shape": "d"})
reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
reg_2 = [reg_2_1, reg_2_2]
@@ -406,7 +403,7 @@ class TestParserAArch64(unittest.TestCase):
# Helper functions
##################
def _get_comment(self, parser, comment):
return ' '.join(
return " ".join(
AttrDict.convert_dict(
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())
).comment
@@ -425,11 +422,11 @@ class TestParserAArch64(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestParserAArch64)
unittest.TextTestRunner(verbosity=2).run(suite)

268
tests/test_parser_x86att.py
View File

@@ -15,7 +15,7 @@ class TestParserX86ATT(unittest.TestCase):
@classmethod
def setUpClass(self):
self.parser = ParserX86ATT()
with open(self._find_file('triad_x86_iaca.s')) as f:
with open(self._find_file("triad_x86_iaca.s")) as f:
self.triad_code = f.read()
##################
@@ -23,29 +23,29 @@ class TestParserX86ATT(unittest.TestCase):
##################
def test_comment_parser(self):
self.assertEqual(self._get_comment(self.parser, '# some comments'), 'some comments')
self.assertEqual(self._get_comment(self.parser, '\t\t#AA BB CC \t end \t'), 'AA BB CC end')
self.assertEqual(self._get_comment(self.parser, "# some comments"), "some comments")
self.assertEqual(self._get_comment(self.parser, "\t\t#AA BB CC \t end \t"), "AA BB CC end")
self.assertEqual(
self._get_comment(self.parser, '\t## comment ## comment'), '# comment ## comment'
self._get_comment(self.parser, "\t## comment ## comment"), "# comment ## comment"
)
def test_label_parser(self):
self.assertEqual(self._get_label(self.parser, 'main:').name, 'main')
self.assertEqual(self._get_label(self.parser, '..B1.10:').name, '..B1.10')
self.assertEqual(self._get_label(self.parser, '.2.3_2_pack.3:').name, '.2.3_2_pack.3')
self.assertEqual(self._get_label(self.parser, '.L1:\t\t\t#label1').name, '.L1')
self.assertEqual(self._get_label(self.parser, "main:").name, "main")
self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t#label1").name, ".L1")
self.assertEqual(
' '.join(self._get_label(self.parser, '.L1:\t\t\t#label1').comment), 'label1'
" ".join(self._get_label(self.parser, ".L1:\t\t\t#label1").comment), "label1"
)
with self.assertRaises(ParseException):
self._get_label(self.parser, '\t.cfi_startproc')
self._get_label(self.parser, "\t.cfi_startproc")
def test_directive_parser(self):
self.assertEqual(self._get_directive(self.parser, '\t.text').name, 'text')
self.assertEqual(len(self._get_directive(self.parser, '\t.text').parameters), 0)
self.assertEqual(self._get_directive(self.parser, '\t.align\t16,0x90').name, 'align')
self.assertEqual(len(self._get_directive(self.parser, '\t.align\t16,0x90').parameters), 2)
self.assertEqual(len(self._get_directive(self.parser, '.text').parameters), 0)
self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
self.assertEqual(len(self._get_directive(self.parser, ".text").parameters), 0)
self.assertEqual(
len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"').parameters), 2
)
@@ -54,54 +54,52 @@ class TestParserX86ATT(unittest.TestCase):
'"path/to/file.c"',
)
self.assertEqual(
self._get_directive(self.parser, '\t.set\tL$set$0,LECIE1-LSCIE1').parameters,
['L$set$0', 'LECIE1-LSCIE1'],
self._get_directive(self.parser, "\t.set\tL$set$0,LECIE1-LSCIE1").parameters,
["L$set$0", "LECIE1-LSCIE1"],
)
self.assertEqual(
self._get_directive(
self.parser,
'\t.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support',
"\t.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support",
).parameters,
['__TEXT', '__eh_frame', 'coalesced', 'no_toc+strip_static_syms+live_support'],
["__TEXT", "__eh_frame", "coalesced", "no_toc+strip_static_syms+live_support"],
)
self.assertEqual(
self._get_directive(
self.parser, '\t.section\t__TEXT,__literal16,16byte_literals'
self.parser, "\t.section\t__TEXT,__literal16,16byte_literals"
).parameters,
['__TEXT', '__literal16', '16byte_literals'],
["__TEXT", "__literal16", "16byte_literals"],
)
self.assertEqual(
self._get_directive(self.parser, '\t.align\t16,0x90').parameters[1], '0x90'
self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
)
self.assertEqual(
self._get_directive(self.parser, ' .byte 100,103,144 #IACA START')[
'name'
],
'byte',
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")["name"],
"byte",
)
self.assertEqual(
self._get_directive(self.parser, ' .byte 100,103,144 #IACA START')[
'parameters'
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[
"parameters"
][2],
'144',
"144",
)
self.assertEqual(
' '.join(
self._get_directive(self.parser, ' .byte 100,103,144 #IACA START')[
'comment'
" ".join(
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[
"comment"
]
),
'IACA START',
"IACA START",
)
def test_parse_instruction(self):
instr1 = '\t\tvcvtsi2ss %edx, %xmm2, %xmm2\t\t\t#12.27'
instr2 = 'jb ..B1.4 \t'
instr3 = ' movl $222,%ebx #IACA END'
instr4 = 'vmovss %xmm4, -4(%rsp,%rax,8) #12.9'
instr5 = 'mov %ebx,var(,1)'
instr6 = 'lea (,%rax,8),%rbx'
instr7 = 'vinsertf128 $0x1, %xmm0, %ymm1, %ymm1'
instr1 = "\t\tvcvtsi2ss %edx, %xmm2, %xmm2\t\t\t#12.27"
instr2 = "jb ..B1.4 \t"
instr3 = " movl $222,%ebx #IACA END"
instr4 = "vmovss %xmm4, -4(%rsp,%rax,8) #12.9"
instr5 = "mov %ebx,var(,1)"
instr6 = "lea (,%rax,8),%rbx"
instr7 = "vinsertf128 $0x1, %xmm0, %ymm1, %ymm1"
parsed_1 = self.parser.parse_instruction(instr1)
parsed_2 = self.parser.parse_instruction(instr2)
@@ -111,99 +109,99 @@ class TestParserX86ATT(unittest.TestCase):
parsed_6 = self.parser.parse_instruction(instr6)
parsed_7 = self.parser.parse_instruction(instr7)
self.assertEqual(parsed_1.instruction, 'vcvtsi2ss')
self.assertEqual(parsed_1.operands[0].register.name, 'edx')
self.assertEqual(parsed_1.operands[1].register.name, 'xmm2')
self.assertEqual(parsed_1.comment, '12.27')
self.assertEqual(parsed_1.instruction, "vcvtsi2ss")
self.assertEqual(parsed_1.operands[0].register.name, "edx")
self.assertEqual(parsed_1.operands[1].register.name, "xmm2")
self.assertEqual(parsed_1.comment, "12.27")
self.assertEqual(parsed_2.instruction, 'jb')
self.assertEqual(parsed_2.operands[0].identifier.name, '..B1.4')
self.assertEqual(parsed_2.instruction, "jb")
self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4")
self.assertEqual(len(parsed_2.operands), 1)
self.assertIsNone(parsed_2.comment)
self.assertEqual(parsed_3.instruction, 'movl')
self.assertEqual(parsed_3.operands[0].immediate.value, '222')
self.assertEqual(parsed_3.operands[1].register.name, 'ebx')
self.assertEqual(parsed_3.comment, 'IACA END')
self.assertEqual(parsed_3.instruction, "movl")
self.assertEqual(parsed_3.operands[0].immediate.value, "222")
self.assertEqual(parsed_3.operands[1].register.name, "ebx")
self.assertEqual(parsed_3.comment, "IACA END")
self.assertEqual(parsed_4.instruction, 'vmovss')
self.assertEqual(parsed_4.operands[1].memory.offset.value, '-4')
self.assertEqual(parsed_4.operands[1].memory.base.name, 'rsp')
self.assertEqual(parsed_4.operands[1].memory.index.name, 'rax')
self.assertEqual(parsed_4.instruction, "vmovss")
self.assertEqual(parsed_4.operands[1].memory.offset.value, "-4")
self.assertEqual(parsed_4.operands[1].memory.base.name, "rsp")
self.assertEqual(parsed_4.operands[1].memory.index.name, "rax")
self.assertEqual(parsed_4.operands[1].memory.scale, 8)
self.assertEqual(parsed_4.operands[0].register.name, 'xmm4')
self.assertEqual(parsed_4.comment, '12.9')
self.assertEqual(parsed_4.operands[0].register.name, "xmm4")
self.assertEqual(parsed_4.comment, "12.9")
self.assertEqual(parsed_5.instruction, 'mov')
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, 'var')
self.assertEqual(parsed_5.instruction, "mov")
self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "var")
self.assertIsNone(parsed_5.operands[1].memory.base)
self.assertIsNone(parsed_5.operands[1].memory.index)
self.assertEqual(parsed_5.operands[1].memory.scale, 1)
self.assertEqual(parsed_5.operands[0].register.name, 'ebx')
self.assertEqual(parsed_5.operands[0].register.name, "ebx")
self.assertEqual(parsed_6.instruction, 'lea')
self.assertEqual(parsed_6.instruction, "lea")
self.assertIsNone(parsed_6.operands[0].memory.offset)
self.assertIsNone(parsed_6.operands[0].memory.base)
self.assertEqual(parsed_6.operands[0].memory.index.name, 'rax')
self.assertEqual(parsed_6.operands[0].memory.index.name, "rax")
self.assertEqual(parsed_6.operands[0].memory.scale, 8)
self.assertEqual(parsed_6.operands[1].register.name, 'rbx')
self.assertEqual(parsed_6.operands[1].register.name, "rbx")
self.assertEqual(parsed_7.operands[0].immediate.value, '0x1')
self.assertEqual(parsed_7.operands[1].register.name, 'xmm0')
self.assertEqual(parsed_7.operands[2].register.name, 'ymm1')
self.assertEqual(parsed_7.operands[3].register.name, 'ymm1')
self.assertEqual(parsed_7.operands[0].immediate.value, "0x1")
self.assertEqual(parsed_7.operands[1].register.name, "xmm0")
self.assertEqual(parsed_7.operands[2].register.name, "ymm1")
self.assertEqual(parsed_7.operands[3].register.name, "ymm1")
def test_parse_line(self):
line_comment = '# -- Begin main'
line_label = '..B1.7: # Preds ..B1.6'
line_directive = '.quad .2.3_2__kmpc_loc_pack.2 #qed'
line_instruction = 'lea 2(%rax,%rax), %ecx #12.9'
line_comment = "# -- Begin main"
line_label = "..B1.7: # Preds ..B1.6"
line_directive = ".quad .2.3_2__kmpc_loc_pack.2 #qed"
line_instruction = "lea 2(%rax,%rax), %ecx #12.9"
instruction_form_1 = {
'instruction': None,
'operands': [],
'directive': None,
'comment': '-- Begin main',
'label': None,
'line': '# -- Begin main',
'line_number': 1,
"instruction": None,
"operands": [],
"directive": None,
"comment": "-- Begin main",
"label": None,
"line": "# -- Begin main",
"line_number": 1,
}
instruction_form_2 = {
'instruction': None,
'operands': [],
'directive': None,
'comment': 'Preds ..B1.6',
'label': '..B1.7',
'line': '..B1.7: # Preds ..B1.6',
'line_number': 2,
"instruction": None,
"operands": [],
"directive": None,
"comment": "Preds ..B1.6",
"label": "..B1.7",
"line": "..B1.7: # Preds ..B1.6",
"line_number": 2,
}
instruction_form_3 = {
'instruction': None,
'operands': [],
'directive': {'name': 'quad', 'parameters': ['.2.3_2__kmpc_loc_pack.2']},
'comment': 'qed',
'label': None,
'line': '.quad .2.3_2__kmpc_loc_pack.2 #qed',
'line_number': 3,
"instruction": None,
"operands": [],
"directive": {"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]},
"comment": "qed",
"label": None,
"line": ".quad .2.3_2__kmpc_loc_pack.2 #qed",
"line_number": 3,
}
instruction_form_4 = {
'instruction': 'lea',
'operands': [
"instruction": "lea",
"operands": [
{
'memory': {
'offset': {'value': '2'},
'base': {'name': 'rax'},
'index': {'name': 'rax'},
'scale': 1,
"memory": {
"offset": {"value": "2"},
"base": {"name": "rax"},
"index": {"name": "rax"},
"scale": 1,
}
},
{'register': {'name': 'ecx'}},
{"register": {"name": "ecx"}},
],
'directive': None,
'comment': '12.9',
'label': None,
'line': 'lea 2(%rax,%rax), %ecx #12.9',
'line_number': 4,
"directive": None,
"comment": "12.9",
"label": None,
"line": "lea 2(%rax,%rax), %ecx #12.9",
"line_number": 4,
}
parsed_1 = self.parser.parse_line(line_comment, 1)
@@ -222,27 +220,27 @@ class TestParserX86ATT(unittest.TestCase):
self.assertEqual(len(parsed), 353)
def test_parse_register(self):
register_str_1 = '%rax'
register_str_2 = '%r9'
register_str_3 = '%xmm1'
register_str_4 = '%rip'
register_str_1 = "%rax"
register_str_2 = "%r9"
register_str_3 = "%xmm1"
register_str_4 = "%rip"
parsed_reg_1 = {'register': {'name': 'rax'}}
parsed_reg_2 = {'register': {'name': 'r9'}}
parsed_reg_3 = {'register': {'name': 'xmm1'}}
parsed_reg_4 = {'register': {'name': 'rip'}}
parsed_reg_1 = {"register": {"name": "rax"}}
parsed_reg_2 = {"register": {"name": "r9"}}
parsed_reg_3 = {"register": {"name": "xmm1"}}
parsed_reg_4 = {"register": {"name": "rip"}}
self.assertEqual(self.parser.parse_register(register_str_1), parsed_reg_1)
self.assertEqual(self.parser.parse_register(register_str_2), parsed_reg_2)
self.assertEqual(self.parser.parse_register(register_str_3), parsed_reg_3)
self.assertEqual(self.parser.parse_register(register_str_4), parsed_reg_4)
self.assertIsNone(self.parser.parse_register('rax'))
self.assertIsNone(self.parser.parse_register("rax"))
def test_normalize_imd(self):
imd_decimal_1 = {'value': '79'}
imd_hex_1 = {'value': '0x4f'}
imd_decimal_2 = {'value': '8'}
imd_hex_2 = {'value': '0x8'}
imd_decimal_1 = {"value": "79"}
imd_hex_1 = {"value": "0x4f"}
imd_decimal_2 = {"value": "8"}
imd_hex_2 = {"value": "0x8"}
self.assertEqual(
self.parser.normalize_imd(imd_decimal_1), self.parser.normalize_imd(imd_hex_1)
)
@@ -251,22 +249,22 @@ class TestParserX86ATT(unittest.TestCase):
)
def test_reg_dependency(self):
reg_a1 = AttrDict({'name': 'rax'})
reg_a2 = AttrDict({'name': 'eax'})
reg_a3 = AttrDict({'name': 'ax'})
reg_a4 = AttrDict({'name': 'al'})
reg_r11 = AttrDict({'name': 'r11'})
reg_r11b = AttrDict({'name': 'r11b'})
reg_r11d = AttrDict({'name': 'r11d'})
reg_r11w = AttrDict({'name': 'r11w'})
reg_xmm1 = AttrDict({'name': 'xmm1'})
reg_ymm1 = AttrDict({'name': 'ymm1'})
reg_zmm1 = AttrDict({'name': 'zmm1'})
reg_a1 = AttrDict({"name": "rax"})
reg_a2 = AttrDict({"name": "eax"})
reg_a3 = AttrDict({"name": "ax"})
reg_a4 = AttrDict({"name": "al"})
reg_r11 = AttrDict({"name": "r11"})
reg_r11b = AttrDict({"name": "r11b"})
reg_r11d = AttrDict({"name": "r11d"})
reg_r11w = AttrDict({"name": "r11w"})
reg_xmm1 = AttrDict({"name": "xmm1"})
reg_ymm1 = AttrDict({"name": "ymm1"})
reg_zmm1 = AttrDict({"name": "zmm1"})
reg_b1 = AttrDict({'name': 'rbx'})
reg_r15 = AttrDict({'name': 'r15'})
reg_xmm2 = AttrDict({'name': 'xmm2'})
reg_ymm3 = AttrDict({'name': 'ymm3'})
reg_b1 = AttrDict({"name": "rbx"})
reg_r15 = AttrDict({"name": "r15"})
reg_xmm2 = AttrDict({"name": "xmm2"})
reg_ymm3 = AttrDict({"name": "ymm3"})
reg_a = [reg_a1, reg_a2, reg_a3, reg_a4]
reg_r = [reg_r11, reg_r11b, reg_r11d, reg_r11w]
@@ -300,7 +298,7 @@ class TestParserX86ATT(unittest.TestCase):
# Helper functions
##################
def _get_comment(self, parser, comment):
return ' '.join(
return " ".join(
AttrDict.convert_dict(
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())
).comment
@@ -319,11 +317,11 @@ class TestParserX86ATT(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestParserX86ATT)
unittest.TextTestRunner(verbosity=2).run(suite)

247
tests/test_semantics.py
View File

@@ -12,13 +12,12 @@ import networkx as nx
from osaca.osaca import get_unmatched_instruction_ratio
from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT
from osaca.semantics import (INSTR_FLAGS, ArchSemantics, KernelDG,
MachineModel, reduce_to_section)
from osaca.semantics import INSTR_FLAGS, ArchSemantics, KernelDG, MachineModel, reduce_to_section
class TestSemanticTools(unittest.TestCase):
MODULE_DATA_DIR = os.path.join(
os.path.dirname(os.path.split(os.path.abspath(__file__))[0]), 'osaca/data/'
os.path.dirname(os.path.split(os.path.abspath(__file__))[0]), "osaca/data/"
)
@classmethod
@@ -26,30 +25,30 @@ class TestSemanticTools(unittest.TestCase):
# set up parser and kernels
cls.parser_x86 = ParserX86ATT()
cls.parser_AArch64 = ParserAArch64()
with open(cls._find_file('kernel_x86.s')) as f:
with open(cls._find_file("kernel_x86.s")) as f:
cls.code_x86 = f.read()
with open(cls._find_file('kernel_aarch64.s')) as f:
with open(cls._find_file("kernel_aarch64.s")) as f:
cls.code_AArch64 = f.read()
cls.kernel_x86 = reduce_to_section(cls.parser_x86.parse_file(cls.code_x86), 'x86')
cls.kernel_x86 = reduce_to_section(cls.parser_x86.parse_file(cls.code_x86), "x86")
cls.kernel_AArch64 = reduce_to_section(
cls.parser_AArch64.parse_file(cls.code_AArch64), 'aarch64'
cls.parser_AArch64.parse_file(cls.code_AArch64), "aarch64"
)
# set up machine models
cls.machine_model_csx = MachineModel(
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, 'csx.yml')
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, "csx.yml")
)
cls.machine_model_tx2 = MachineModel(
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, 'tx2.yml')
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, "tx2.yml")
)
cls.semantics_csx = ArchSemantics(
cls.machine_model_csx, path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, 'isa/x86.yml')
cls.machine_model_csx, path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, "isa/x86.yml")
)
cls.semantics_tx2 = ArchSemantics(
cls.machine_model_tx2,
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, 'isa/aarch64.yml'),
path_to_yaml=os.path.join(cls.MODULE_DATA_DIR, "isa/aarch64.yml"),
)
cls.machine_model_zen = MachineModel(arch='zen1')
cls.machine_model_zen = MachineModel(arch="zen1")
for i in range(len(cls.kernel_x86)):
cls.semantics_csx.assign_src_dst(cls.kernel_x86[i])
@@ -64,7 +63,7 @@ class TestSemanticTools(unittest.TestCase):
def test_creation_by_name(self):
try:
tmp_mm = MachineModel(arch='CSX')
tmp_mm = MachineModel(arch="CSX")
ArchSemantics(tmp_mm)
except ValueError:
self.fail()
@@ -72,12 +71,12 @@ class TestSemanticTools(unittest.TestCase):
def test_machine_model_various_functions(self):
# check dummy MachineModel creation
try:
MachineModel(isa='x86')
MachineModel(isa='aarch64')
MachineModel(isa="x86")
MachineModel(isa="aarch64")
except ValueError:
self.fail()
test_mm_x86 = MachineModel(path_to_yaml=self._find_file('test_db_x86.yml'))
test_mm_arm = MachineModel(path_to_yaml=self._find_file('test_db_aarch64.yml'))
test_mm_x86 = MachineModel(path_to_yaml=self._find_file("test_db_x86.yml"))
test_mm_arm = MachineModel(path_to_yaml=self._find_file("test_db_aarch64.yml"))
# test get_instruction without mnemonic
self.assertIsNone(test_mm_x86.get_instruction(None, []))
@@ -86,80 +85,80 @@ class TestSemanticTools(unittest.TestCase):
# test get_instruction from DB
self.assertIsNone(test_mm_x86.get_instruction(None, []))
self.assertIsNone(test_mm_arm.get_instruction(None, []))
self.assertIsNone(test_mm_x86.get_instruction('NOT_IN_DB', []))
self.assertIsNone(test_mm_arm.get_instruction('NOT_IN_DB', []))
name_x86_1 = 'vaddpd'
self.assertIsNone(test_mm_x86.get_instruction("NOT_IN_DB", []))
self.assertIsNone(test_mm_arm.get_instruction("NOT_IN_DB", []))
name_x86_1 = "vaddpd"
operands_x86_1 = [
{'class': 'register', 'name': 'xmm'},
{'class': 'register', 'name': 'xmm'},
{'class': 'register', 'name': 'xmm'},
{"class": "register", "name": "xmm"},
{"class": "register", "name": "xmm"},
{"class": "register", "name": "xmm"},
]
instr_form_x86_1 = test_mm_x86.get_instruction(name_x86_1, operands_x86_1)
self.assertEqual(instr_form_x86_1, test_mm_x86.get_instruction(name_x86_1, operands_x86_1))
self.assertEqual(
test_mm_x86.get_instruction('jg', [{'class': 'identifier'}]),
test_mm_x86.get_instruction('jg', [{'class': 'identifier'}]),
test_mm_x86.get_instruction("jg", [{"class": "identifier"}]),
test_mm_x86.get_instruction("jg", [{"class": "identifier"}]),
)
name_arm_1 = 'fadd'
name_arm_1 = "fadd"
operands_arm_1 = [
{'class': 'register', 'prefix': 'v', 'shape': 's'},
{'class': 'register', 'prefix': 'v', 'shape': 's'},
{'class': 'register', 'prefix': 'v', 'shape': 's'},
{"class": "register", "prefix": "v", "shape": "s"},
{"class": "register", "prefix": "v", "shape": "s"},
{"class": "register", "prefix": "v", "shape": "s"},
]
instr_form_arm_1 = test_mm_arm.get_instruction(name_arm_1, operands_arm_1)
self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1))
self.assertEqual(
test_mm_arm.get_instruction('b.ne', [{'class': 'identifier'}]),
test_mm_arm.get_instruction('b.ne', [{'class': 'identifier'}]),
test_mm_arm.get_instruction("b.ne", [{"class": "identifier"}]),
test_mm_arm.get_instruction("b.ne", [{"class": "identifier"}]),
)
# test full instruction name
self.assertEqual(
MachineModel.get_full_instruction_name(instr_form_x86_1),
'vaddpd register(name:xmm),register(name:xmm),register(name:xmm)',
"vaddpd register(name:xmm),register(name:xmm),register(name:xmm)",
)
self.assertEqual(
MachineModel.get_full_instruction_name(instr_form_arm_1),
'fadd register(prefix:v,shape:s),register(prefix:v,shape:s),'
+ 'register(prefix:v,shape:s)',
"fadd register(prefix:v,shape:s),register(prefix:v,shape:s),"
+ "register(prefix:v,shape:s)",
)
# test get_store_tp
self.assertEqual(
test_mm_x86.get_store_throughput(
{'base': {'name': 'x'}, 'offset': None, 'index': None, 'scale': 1}
{"base": {"name": "x"}, "offset": None, "index": None, "scale": 1}
),
[[2, '237'], [2, '4']],
[[2, "237"], [2, "4"]],
)
self.assertEqual(
test_mm_x86.get_store_throughput(
{'base': {'prefix': 'NOT_IN_DB'}, 'offset': None, 'index': 'NOT_NONE', 'scale': 1}
{"base": {"prefix": "NOT_IN_DB"}, "offset": None, "index": "NOT_NONE", "scale": 1}
),
[[1, '23'], [1, '4']],
[[1, "23"], [1, "4"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
{'base': {'prefix': 'x'}, 'offset': None, 'index': None, 'scale': 1}
{"base": {"prefix": "x"}, "offset": None, "index": None, "scale": 1}
),
[[2, '34'], [2, '5']],
[[2, "34"], [2, "5"]],
)
self.assertEqual(
test_mm_arm.get_store_throughput(
{'base': {'prefix': 'NOT_IN_DB'}, 'offset': None, 'index': None, 'scale': 1}
{"base": {"prefix": "NOT_IN_DB"}, "offset": None, "index": None, "scale": 1}
),
[[1, '34'], [1, '5']],
[[1, "34"], [1, "5"]],
)
# test get_store_lt
self.assertEqual(
test_mm_x86.get_store_latency(
{'base': {'name': 'x'}, 'offset': None, 'index': None, 'scale': '1'}
{"base": {"name": "x"}, "offset": None, "index": None, "scale": "1"}
),
0,
)
self.assertEqual(
test_mm_arm.get_store_latency(
{'base': {'prefix': 'x'}, 'offset': None, 'index': None, 'scale': '1'}
{"base": {"prefix": "x"}, "offset": None, "index": None, "scale": "1"}
),
0,
)
@@ -170,55 +169,55 @@ class TestSemanticTools(unittest.TestCase):
# test default load tp
self.assertEqual(
test_mm_x86.get_load_throughput(
{'base': {'name': 'x'}, 'offset': None, 'index': None, 'scale': 1}
{"base": {"name": "x"}, "offset": None, "index": None, "scale": 1}
),
[[1, '23'], [1, ['2D', '3D']]],
[[1, "23"], [1, ["2D", "3D"]]],
)
# test adding port
test_mm_x86.add_port('dummyPort')
test_mm_arm.add_port('dummyPort')
test_mm_x86.add_port("dummyPort")
test_mm_arm.add_port("dummyPort")
# test dump of DB
with open('/dev/null', 'w') as dev_null:
with open("/dev/null", "w") as dev_null:
test_mm_x86.dump(stream=dev_null)
test_mm_arm.dump(stream=dev_null)
def test_src_dst_assignment_x86(self):
for instruction_form in self.kernel_x86:
with self.subTest(instruction_form=instruction_form):
if instruction_form['semantic_operands'] is not None:
self.assertTrue('source' in instruction_form['semantic_operands'])
self.assertTrue('destination' in instruction_form['semantic_operands'])
self.assertTrue('src_dst' in instruction_form['semantic_operands'])
if instruction_form["semantic_operands"] is not None:
self.assertTrue("source" in instruction_form["semantic_operands"])
self.assertTrue("destination" in instruction_form["semantic_operands"])
self.assertTrue("src_dst" in instruction_form["semantic_operands"])
def test_src_dst_assignment_AArch64(self):
for instruction_form in self.kernel_AArch64:
with self.subTest(instruction_form=instruction_form):
if instruction_form['semantic_operands'] is not None:
self.assertTrue('source' in instruction_form['semantic_operands'])
self.assertTrue('destination' in instruction_form['semantic_operands'])
self.assertTrue('src_dst' in instruction_form['semantic_operands'])
if instruction_form["semantic_operands"] is not None:
self.assertTrue("source" in instruction_form["semantic_operands"])
self.assertTrue("destination" in instruction_form["semantic_operands"])
self.assertTrue("src_dst" in instruction_form["semantic_operands"])
def test_tp_lt_assignment_x86(self):
self.assertTrue('ports' in self.machine_model_csx)
port_num = len(self.machine_model_csx['ports'])
self.assertTrue("ports" in self.machine_model_csx)
port_num = len(self.machine_model_csx["ports"])
for instruction_form in self.kernel_x86:
with self.subTest(instruction_form=instruction_form):
self.assertTrue('throughput' in instruction_form)
self.assertTrue('latency' in instruction_form)
self.assertIsInstance(instruction_form['port_pressure'], list)
self.assertEqual(len(instruction_form['port_pressure']), port_num)
self.assertTrue("throughput" in instruction_form)
self.assertTrue("latency" in instruction_form)
self.assertIsInstance(instruction_form["port_pressure"], list)
self.assertEqual(len(instruction_form["port_pressure"]), port_num)
def test_tp_lt_assignment_AArch64(self):
self.assertTrue('ports' in self.machine_model_tx2)
port_num = len(self.machine_model_tx2['ports'])
self.assertTrue("ports" in self.machine_model_tx2)
port_num = len(self.machine_model_tx2["ports"])
for instruction_form in self.kernel_AArch64:
with self.subTest(instruction_form=instruction_form):
self.assertTrue('throughput' in instruction_form)
self.assertTrue('latency' in instruction_form)
self.assertIsInstance(instruction_form['port_pressure'], list)
self.assertEqual(len(instruction_form['port_pressure']), port_num)
self.assertTrue("throughput" in instruction_form)
self.assertTrue("latency" in instruction_form)
self.assertIsInstance(instruction_form["port_pressure"], list)
self.assertEqual(len(instruction_form["port_pressure"]), port_num)
def test_optimal_throughput_assignment(self):
# x86
@@ -266,7 +265,7 @@ class TestSemanticTools(unittest.TestCase):
with self.assertRaises(ValueError):
dg.get_dependent_instruction_forms()
# test dot creation
dg.export_graph(filepath='/dev/null')
dg.export_graph(filepath="/dev/null")
def test_kernelDG_AArch64(self):
dg = KernelDG(self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2)
@@ -292,11 +291,11 @@ class TestSemanticTools(unittest.TestCase):
with self.assertRaises(ValueError):
dg.get_dependent_instruction_forms()
# test dot creation
dg.export_graph(filepath='/dev/null')
dg.export_graph(filepath="/dev/null")
def test_hidden_load(self):
machine_model_hld = MachineModel(
path_to_yaml=self._find_file('hidden_load_machine_model.yml')
path_to_yaml=self._find_file("hidden_load_machine_model.yml")
)
self.assertTrue(machine_model_hld.has_hidden_loads())
semantics_hld = ArchSemantics(machine_model_hld)
@@ -308,9 +307,9 @@ class TestSemanticTools(unittest.TestCase):
semantics_hld.add_semantics(kernel_hld_2)
semantics_hld.add_semantics(kernel_hld_3)
num_hidden_loads = len([x for x in kernel_hld if INSTR_FLAGS.HIDDEN_LD in x['flags']])
num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_FLAGS.HIDDEN_LD in x['flags']])
num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_FLAGS.HIDDEN_LD in x['flags']])
num_hidden_loads = len([x for x in kernel_hld if INSTR_FLAGS.HIDDEN_LD in x["flags"]])
num_hidden_loads_2 = len([x for x in kernel_hld_2 if INSTR_FLAGS.HIDDEN_LD in x["flags"]])
num_hidden_loads_3 = len([x for x in kernel_hld_3 if INSTR_FLAGS.HIDDEN_LD in x["flags"]])
self.assertEqual(num_hidden_loads, 1)
self.assertEqual(num_hidden_loads_2, 0)
self.assertEqual(num_hidden_loads_3, 1)
@@ -333,42 +332,42 @@ class TestSemanticTools(unittest.TestCase):
self.assertEqual(len(lc_deps), 2)
# ID 8
self.assertEqual(
lc_deps[lcd_id]['root'], dg.dg.nodes(data=True)[lcd_id]['instruction_form']
lc_deps[lcd_id]["root"], dg.dg.nodes(data=True)[lcd_id]["instruction_form"]
)
self.assertEqual(len(lc_deps[lcd_id]['dependencies']), 1)
self.assertEqual(len(lc_deps[lcd_id]["dependencies"]), 1)
self.assertEqual(
lc_deps[lcd_id]['dependencies'][0], dg.dg.nodes(data=True)[lcd_id]['instruction_form']
lc_deps[lcd_id]["dependencies"][0], dg.dg.nodes(data=True)[lcd_id]["instruction_form"]
)
# w/ flag dependencies: ID 9 w/ len=2
# w/o flag dependencies: ID 5 w/ len=1
# TODO discuss
self.assertEqual(
lc_deps[lcd_id2]['root'], dg.dg.nodes(data=True)[lcd_id2]['instruction_form']
lc_deps[lcd_id2]["root"], dg.dg.nodes(data=True)[lcd_id2]["instruction_form"]
)
self.assertEqual(len(lc_deps[lcd_id2]['dependencies']), 1)
self.assertEqual(len(lc_deps[lcd_id2]["dependencies"]), 1)
self.assertEqual(
lc_deps[lcd_id2]['dependencies'][0],
dg.dg.nodes(data=True)[lcd_id2]['instruction_form'],
lc_deps[lcd_id2]["dependencies"][0],
dg.dg.nodes(data=True)[lcd_id2]["instruction_form"],
)
def test_is_read_is_written_x86(self):
# independent form HW model
dag = KernelDG(self.kernel_x86, self.parser_x86, None)
reg_rcx = AttrDict({'name': 'rcx'})
reg_ymm1 = AttrDict({'name': 'ymm1'})
reg_rcx = AttrDict({"name": "rcx"})
reg_ymm1 = AttrDict({"name": "ymm1"})
instr_form_r_c = self.parser_x86.parse_line('vmovsd %xmm0, (%r15,%rcx,8)')
instr_form_r_c = self.parser_x86.parse_line("vmovsd %xmm0, (%r15,%rcx,8)")
self.semantics_csx.assign_src_dst(instr_form_r_c)
instr_form_non_r_c = self.parser_x86.parse_line('movl %xmm0, (%r15,%rax,8)')
instr_form_non_r_c = self.parser_x86.parse_line("movl %xmm0, (%r15,%rax,8)")
self.semantics_csx.assign_src_dst(instr_form_non_r_c)
instr_form_w_c = self.parser_x86.parse_line('movi $0x05ACA, %rcx')
instr_form_w_c = self.parser_x86.parse_line("movi $0x05ACA, %rcx")
self.semantics_csx.assign_src_dst(instr_form_w_c)
instr_form_rw_ymm_1 = self.parser_x86.parse_line('vinsertf128 $0x1, %xmm1, %ymm0, %ymm1')
instr_form_rw_ymm_1 = self.parser_x86.parse_line("vinsertf128 $0x1, %xmm1, %ymm0, %ymm1")
self.semantics_csx.assign_src_dst(instr_form_rw_ymm_1)
instr_form_rw_ymm_2 = self.parser_x86.parse_line('vinsertf128 $0x1, %xmm0, %ymm1, %ymm1')
instr_form_rw_ymm_2 = self.parser_x86.parse_line("vinsertf128 $0x1, %xmm0, %ymm1, %ymm1")
self.semantics_csx.assign_src_dst(instr_form_rw_ymm_2)
instr_form_r_ymm = self.parser_x86.parse_line('vmovapd %ymm1, %ymm0')
instr_form_r_ymm = self.parser_x86.parse_line("vmovapd %ymm1, %ymm0")
self.semantics_csx.assign_src_dst(instr_form_r_ymm)
self.assertTrue(dag.is_read(reg_rcx, instr_form_r_c))
@@ -387,29 +386,29 @@ class TestSemanticTools(unittest.TestCase):
def test_is_read_is_written_AArch64(self):
# independent form HW model
dag = KernelDG(self.kernel_AArch64, self.parser_AArch64, None)
reg_x1 = AttrDict({'prefix': 'x', 'name': '1'})
reg_w1 = AttrDict({'prefix': 'w', 'name': '1'})
reg_d1 = AttrDict({'prefix': 'd', 'name': '1'})
reg_q1 = AttrDict({'prefix': 'q', 'name': '1'})
reg_v1 = AttrDict({'prefix': 'v', 'name': '1', 'lanes': '2', 'shape': 'd'})
reg_x1 = AttrDict({"prefix": "x", "name": "1"})
reg_w1 = AttrDict({"prefix": "w", "name": "1"})
reg_d1 = AttrDict({"prefix": "d", "name": "1"})
reg_q1 = AttrDict({"prefix": "q", "name": "1"})
reg_v1 = AttrDict({"prefix": "v", "name": "1", "lanes": "2", "shape": "d"})
regs = [reg_d1, reg_q1, reg_v1]
regs_gp = [reg_w1, reg_x1]
instr_form_r_1 = self.parser_AArch64.parse_line('stp q1, q3, [x12, #192]')
instr_form_r_1 = self.parser_AArch64.parse_line("stp q1, q3, [x12, #192]")
self.semantics_tx2.assign_src_dst(instr_form_r_1)
instr_form_r_2 = self.parser_AArch64.parse_line('fadd v2.2d, v1.2d, v0.2d')
instr_form_r_2 = self.parser_AArch64.parse_line("fadd v2.2d, v1.2d, v0.2d")
self.semantics_tx2.assign_src_dst(instr_form_r_2)
instr_form_w_1 = self.parser_AArch64.parse_line('ldr d1, [x1, #:got_lo12:q2c]')
instr_form_w_1 = self.parser_AArch64.parse_line("ldr d1, [x1, #:got_lo12:q2c]")
self.semantics_tx2.assign_src_dst(instr_form_w_1)
instr_form_non_w_1 = self.parser_AArch64.parse_line('ldr x1, [x1, #:got_lo12:q2c]')
instr_form_non_w_1 = self.parser_AArch64.parse_line("ldr x1, [x1, #:got_lo12:q2c]")
self.semantics_tx2.assign_src_dst(instr_form_non_w_1)
instr_form_rw_1 = self.parser_AArch64.parse_line('fmul v1.2d, v1.2d, v0.2d')
instr_form_rw_1 = self.parser_AArch64.parse_line("fmul v1.2d, v1.2d, v0.2d")
self.semantics_tx2.assign_src_dst(instr_form_rw_1)
instr_form_rw_2 = self.parser_AArch64.parse_line('ldp q2, q4, [x1, #64]!')
instr_form_rw_2 = self.parser_AArch64.parse_line("ldp q2, q4, [x1, #64]!")
self.semantics_tx2.assign_src_dst(instr_form_rw_2)
instr_form_rw_3 = self.parser_AArch64.parse_line('str x4, [x1], #64')
instr_form_rw_3 = self.parser_AArch64.parse_line("str x4, [x1], #64")
self.semantics_tx2.assign_src_dst(instr_form_rw_3)
instr_form_non_rw_1 = self.parser_AArch64.parse_line('adds x1, x11')
instr_form_non_rw_1 = self.parser_AArch64.parse_line("adds x1, x11")
self.semantics_tx2.assign_src_dst(instr_form_non_rw_1)
for reg in regs:
@@ -447,43 +446,43 @@ class TestSemanticTools(unittest.TestCase):
with self.assertRaises(ValueError):
MachineModel()
with self.assertRaises(ValueError):
MachineModel(arch='CSX', path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'csx.yml'))
MachineModel(arch="CSX", path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "csx.yml"))
with self.assertRaises(FileNotFoundError):
MachineModel(arch='THE_MACHINE')
MachineModel(arch="THE_MACHINE")
with self.assertRaises(FileNotFoundError):
MachineModel(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, 'THE_MACHINE.yml'))
MachineModel(path_to_yaml=os.path.join(self.MODULE_DATA_DIR, "THE_MACHINE.yml"))
def test_MachineModel_getter(self):
sample_operands = [
{
'memory': {
'offset': None,
'base': {'name': 'r12'},
'index': {'name': 'rcx'},
'scale': 8,
"memory": {
"offset": None,
"base": {"name": "r12"},
"index": {"name": "rcx"},
"scale": 8,
}
}
]
self.assertIsNone(self.machine_model_csx.get_instruction('GETRESULT', sample_operands))
self.assertIsNone(self.machine_model_tx2.get_instruction('GETRESULT', sample_operands))
self.assertIsNone(self.machine_model_csx.get_instruction("GETRESULT", sample_operands))
self.assertIsNone(self.machine_model_tx2.get_instruction("GETRESULT", sample_operands))
self.assertEqual(self.machine_model_csx.get_arch(), 'csx')
self.assertEqual(self.machine_model_tx2.get_arch(), 'tx2')
self.assertEqual(self.machine_model_csx.get_arch(), "csx")
self.assertEqual(self.machine_model_tx2.get_arch(), "tx2")
self.assertEqual(self.machine_model_csx.get_ISA(), 'x86')
self.assertEqual(self.machine_model_tx2.get_ISA(), 'aarch64')
self.assertEqual(self.machine_model_csx.get_ISA(), "x86")
self.assertEqual(self.machine_model_tx2.get_ISA(), "aarch64")
ports_csx = ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5', '6', '7']
data_ports_csx = ['2D', '3D']
ports_csx = ["0", "0DV", "1", "2", "2D", "3", "3D", "4", "5", "6", "7"]
data_ports_csx = ["2D", "3D"]
self.assertEqual(self.machine_model_csx.get_ports(), ports_csx)
self.assertEqual(self.machine_model_csx.get_data_ports(), data_ports_csx)
self.assertFalse(self.machine_model_tx2.has_hidden_loads())
self.assertEqual(MachineModel.get_isa_for_arch('CSX'), 'x86')
self.assertEqual(MachineModel.get_isa_for_arch('tX2'), 'aarch64')
self.assertEqual(MachineModel.get_isa_for_arch("CSX"), "x86")
self.assertEqual(MachineModel.get_isa_for_arch("tX2"), "aarch64")
with self.assertRaises(ValueError):
self.assertIsNone(MachineModel.get_isa_for_arch('THE_MACHINE'))
self.assertIsNone(MachineModel.get_isa_for_arch("THE_MACHINE"))
##################
# Helper functions
@@ -492,11 +491,11 @@ class TestSemanticTools(unittest.TestCase):
@staticmethod
def _find_file(name):
testdir = os.path.dirname(__file__)
name = os.path.join(testdir, 'test_files', name)
name = os.path.join(testdir, "test_files", name)
assert os.path.exists(name)
return name
if __name__ == '__main__':
if __name__ == "__main__":
suite = unittest.TestLoader().loadTestsFromTestCase(TestSemanticTools)
unittest.TextTestRunner(verbosity=2).run(suite)