mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-04 18:20:09 +01:00
migrate code style to Black
This commit is contained in:
Julian Hammer
@@ -15,7 +15,7 @@ class TestParserAArch64(unittest.TestCase):
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@classmethod
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def setUpClass(self):
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self.parser = ParserAArch64()
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with open(self._find_file('triad_arm_iaca.s')) as f:
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with open(self._find_file("triad_arm_iaca.s")) as f:
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self.triad_code = f.read()
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##################
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@@ -23,63 +23,61 @@ class TestParserAArch64(unittest.TestCase):
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##################
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def test_comment_parser(self):
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self.assertEqual(self._get_comment(self.parser, '// some comments'), 'some comments')
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self.assertEqual(self._get_comment(self.parser, "// some comments"), "some comments")
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self.assertEqual(self._get_comment(self.parser, "\t\t//AA BB CC \t end \t"), "AA BB CC end")
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self.assertEqual(
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self._get_comment(self.parser, '\t\t//AA BB CC \t end \t'), 'AA BB CC end'
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)
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self.assertEqual(
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self._get_comment(self.parser, '\t//// comment //// comment'),
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'// comment //// comment',
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self._get_comment(self.parser, "\t//// comment //// comment"),
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"// comment //// comment",
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)
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def test_label_parser(self):
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self.assertEqual(self._get_label(self.parser, 'main:').name, 'main')
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self.assertEqual(self._get_label(self.parser, '..B1.10:').name, '..B1.10')
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self.assertEqual(self._get_label(self.parser, '.2.3_2_pack.3:').name, '.2.3_2_pack.3')
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self.assertEqual(self._get_label(self.parser, '.L1:\t\t\t//label1').name, '.L1')
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self.assertEqual(self._get_label(self.parser, "main:").name, "main")
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self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
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self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
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self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1").name, ".L1")
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self.assertEqual(
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' '.join(self._get_label(self.parser, '.L1:\t\t\t//label1').comment), 'label1'
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" ".join(self._get_label(self.parser, ".L1:\t\t\t//label1").comment), "label1"
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)
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with self.assertRaises(ParseException):
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self._get_label(self.parser, '\t.cfi_startproc')
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self._get_label(self.parser, "\t.cfi_startproc")
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def test_directive_parser(self):
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self.assertEqual(self._get_directive(self.parser, '\t.text').name, 'text')
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self.assertEqual(len(self._get_directive(self.parser, '\t.text').parameters), 0)
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self.assertEqual(self._get_directive(self.parser, '\t.align\t16,0x90').name, 'align')
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self.assertEqual(len(self._get_directive(self.parser, '\t.align\t16,0x90').parameters), 2)
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self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
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self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
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self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
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self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
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self.assertEqual(
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self._get_directive(self.parser, '\t.align\t16,0x90').parameters[1], '0x90'
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self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
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)
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self.assertEqual(
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self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
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'name'
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"name"
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],
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'byte',
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"byte",
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)
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self.assertEqual(
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self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
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'parameters'
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"parameters"
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][2],
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'144',
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"144",
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)
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self.assertEqual(
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' '.join(
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self._get_directive(self.parser, ' .byte 100,103,144 //IACA START')[
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'comment'
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" ".join(
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"comment"
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]
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),
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'IACA START',
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"IACA START",
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)
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def test_parse_instruction(self):
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instr1 = '\t\tvcvt.F32.S32 w1, w2\t\t\t//12.27'
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instr2 = 'b.lo ..B1.4 \t'
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instr3 = ' mov x2,#0x222 //NOT IACA END'
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instr4 = 'str x28, [sp, x1, lsl #4] //12.9'
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instr5 = 'ldr x0, [x0, #:got_lo12:q2c]'
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instr6 = 'adrp x0, :got:visited'
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instr7 = 'fadd v17.2d, v16.2d, v1.2d'
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instr1 = "\t\tvcvt.F32.S32 w1, w2\t\t\t//12.27"
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instr2 = "b.lo ..B1.4 \t"
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instr3 = " mov x2,#0x222 //NOT IACA END"
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instr4 = "str x28, [sp, x1, lsl #4] //12.9"
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instr5 = "ldr x0, [x0, #:got_lo12:q2c]"
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instr6 = "adrp x0, :got:visited"
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instr7 = "fadd v17.2d, v16.2d, v1.2d"
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parsed_1 = self.parser.parse_instruction(instr1)
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parsed_2 = self.parser.parse_instruction(instr2)
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@@ -89,198 +87,196 @@ class TestParserAArch64(unittest.TestCase):
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parsed_6 = self.parser.parse_instruction(instr6)
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parsed_7 = self.parser.parse_instruction(instr7)
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self.assertEqual(parsed_1.instruction, 'vcvt.F32.S32')
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self.assertEqual(parsed_1.operands[0].register.name, '1')
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self.assertEqual(parsed_1.operands[0].register.prefix, 'w')
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self.assertEqual(parsed_1.operands[1].register.name, '2')
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self.assertEqual(parsed_1.operands[1].register.prefix, 'w')
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self.assertEqual(parsed_1.comment, '12.27')
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self.assertEqual(parsed_1.instruction, "vcvt.F32.S32")
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self.assertEqual(parsed_1.operands[0].register.name, "1")
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self.assertEqual(parsed_1.operands[0].register.prefix, "w")
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self.assertEqual(parsed_1.operands[1].register.name, "2")
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self.assertEqual(parsed_1.operands[1].register.prefix, "w")
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self.assertEqual(parsed_1.comment, "12.27")
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self.assertEqual(parsed_2.instruction, 'b.lo')
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self.assertEqual(parsed_2.operands[0].identifier.name, '..B1.4')
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self.assertEqual(parsed_2.instruction, "b.lo")
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self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4")
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self.assertEqual(len(parsed_2.operands), 1)
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self.assertIsNone(parsed_2.comment)
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self.assertEqual(parsed_3.instruction, 'mov')
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self.assertEqual(parsed_3.operands[0].register.name, '2')
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self.assertEqual(parsed_3.operands[0].register.prefix, 'x')
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self.assertEqual(parsed_3.operands[1].immediate.value, '0x222')
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self.assertEqual(parsed_3.comment, 'NOT IACA END')
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self.assertEqual(parsed_3.instruction, "mov")
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self.assertEqual(parsed_3.operands[0].register.name, "2")
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self.assertEqual(parsed_3.operands[0].register.prefix, "x")
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self.assertEqual(parsed_3.operands[1].immediate.value, "0x222")
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self.assertEqual(parsed_3.comment, "NOT IACA END")
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self.assertEqual(parsed_4.instruction, 'str')
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self.assertEqual(parsed_4.instruction, "str")
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self.assertIsNone(parsed_4.operands[1].memory.offset)
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self.assertEqual(parsed_4.operands[1].memory.base.name, 'sp')
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self.assertEqual(parsed_4.operands[1].memory.base.prefix, 'x')
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self.assertEqual(parsed_4.operands[1].memory.index.name, '1')
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self.assertEqual(parsed_4.operands[1].memory.index.prefix, 'x')
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self.assertEqual(parsed_4.operands[1].memory.base.name, "sp")
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self.assertEqual(parsed_4.operands[1].memory.base.prefix, "x")
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self.assertEqual(parsed_4.operands[1].memory.index.name, "1")
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self.assertEqual(parsed_4.operands[1].memory.index.prefix, "x")
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self.assertEqual(parsed_4.operands[1].memory.scale, 16)
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self.assertEqual(parsed_4.operands[0].register.name, '28')
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self.assertEqual(parsed_4.operands[0].register.prefix, 'x')
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self.assertEqual(parsed_4.comment, '12.9')
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self.assertEqual(parsed_4.operands[0].register.name, "28")
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self.assertEqual(parsed_4.operands[0].register.prefix, "x")
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self.assertEqual(parsed_4.comment, "12.9")
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self.assertEqual(parsed_5.instruction, 'ldr')
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self.assertEqual(parsed_5.operands[0].register.name, '0')
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self.assertEqual(parsed_5.operands[0].register.prefix, 'x')
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, 'q2c')
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation,
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':got_lo12:')
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self.assertEqual(parsed_5.operands[1].memory.base.name, '0')
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self.assertEqual(parsed_5.operands[1].memory.base.prefix, 'x')
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self.assertEqual(parsed_5.instruction, "ldr")
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self.assertEqual(parsed_5.operands[0].register.name, "0")
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self.assertEqual(parsed_5.operands[0].register.prefix, "x")
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "q2c")
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation, ":got_lo12:")
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self.assertEqual(parsed_5.operands[1].memory.base.name, "0")
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self.assertEqual(parsed_5.operands[1].memory.base.prefix, "x")
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self.assertIsNone(parsed_5.operands[1].memory.index)
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self.assertEqual(parsed_5.operands[1].memory.scale, 1)
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self.assertEqual(parsed_6.instruction, 'adrp')
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self.assertEqual(parsed_6.operands[0].register.name, '0')
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self.assertEqual(parsed_6.operands[0].register.prefix, 'x')
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self.assertEqual(parsed_6.operands[1].identifier.relocation, ':got:')
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self.assertEqual(parsed_6.operands[1].identifier.name, 'visited')
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self.assertEqual(parsed_6.instruction, "adrp")
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self.assertEqual(parsed_6.operands[0].register.name, "0")
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self.assertEqual(parsed_6.operands[0].register.prefix, "x")
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self.assertEqual(parsed_6.operands[1].identifier.relocation, ":got:")
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self.assertEqual(parsed_6.operands[1].identifier.name, "visited")
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self.assertEqual(parsed_7.instruction, 'fadd')
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self.assertEqual(parsed_7.operands[0].register.name, '17')
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self.assertEqual(parsed_7.operands[0].register.prefix, 'v')
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self.assertEqual(parsed_7.operands[0].register.lanes, '2')
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self.assertEqual(parsed_7.operands[0].register.shape, 'd')
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self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register),
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'v1.2d')
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self.assertEqual(parsed_7.instruction, "fadd")
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self.assertEqual(parsed_7.operands[0].register.name, "17")
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self.assertEqual(parsed_7.operands[0].register.prefix, "v")
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self.assertEqual(parsed_7.operands[0].register.lanes, "2")
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self.assertEqual(parsed_7.operands[0].register.shape, "d")
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self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register), "v1.2d")
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def test_parse_line(self):
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line_comment = '// -- Begin main'
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line_label = '.LBB0_1: // =>This Inner Loop Header: Depth=1'
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line_directive = '.cfi_def_cfa w29, -16'
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line_instruction = 'ldr s0, [x11, w10, sxtw #2] // = <<2'
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line_prefetch = 'prfm pldl1keep, [x26, #2048] //HPL'
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line_preindexed = 'stp x29, x30, [sp, #-16]!'
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line_postindexed = 'ldp q2, q3, [x11], #64'
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line_5_operands = 'fcmla z26.d, p0/m, z29.d, z21.d, #90'
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line_comment = "// -- Begin main"
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line_label = ".LBB0_1: // =>This Inner Loop Header: Depth=1"
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line_directive = ".cfi_def_cfa w29, -16"
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line_instruction = "ldr s0, [x11, w10, sxtw #2] // = <<2"
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line_prefetch = "prfm pldl1keep, [x26, #2048] //HPL"
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line_preindexed = "stp x29, x30, [sp, #-16]!"
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line_postindexed = "ldp q2, q3, [x11], #64"
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line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90"
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instruction_form_1 = {
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'instruction': None,
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'operands': [],
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'directive': None,
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'comment': '-- Begin main',
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'label': None,
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'line': '// -- Begin main',
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'line_number': 1,
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"instruction": None,
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"operands": [],
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"directive": None,
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"comment": "-- Begin main",
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"label": None,
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"line": "// -- Begin main",
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"line_number": 1,
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}
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instruction_form_2 = {
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'instruction': None,
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'operands': [],
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'directive': None,
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'comment': '=>This Inner Loop Header: Depth=1',
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'label': '.LBB0_1',
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'line': '.LBB0_1: // =>This Inner Loop Header: Depth=1',
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'line_number': 2,
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"instruction": None,
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"operands": [],
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"directive": None,
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"comment": "=>This Inner Loop Header: Depth=1",
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"label": ".LBB0_1",
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"line": ".LBB0_1: // =>This Inner Loop Header: Depth=1",
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"line_number": 2,
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}
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instruction_form_3 = {
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'instruction': None,
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'operands': [],
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'directive': {'name': 'cfi_def_cfa', 'parameters': ['w29', '-16']},
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'comment': None,
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'label': None,
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'line': '.cfi_def_cfa w29, -16',
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'line_number': 3,
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"instruction": None,
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"operands": [],
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"directive": {"name": "cfi_def_cfa", "parameters": ["w29", "-16"]},
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"comment": None,
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"label": None,
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"line": ".cfi_def_cfa w29, -16",
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"line_number": 3,
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}
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instruction_form_4 = {
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'instruction': 'ldr',
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'operands': [
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{'register': {'prefix': 's', 'name': '0'}},
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"instruction": "ldr",
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"operands": [
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{"register": {"prefix": "s", "name": "0"}},
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{
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'memory': {
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'offset': None,
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'base': {'prefix': 'x', 'name': '11'},
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'index': {
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'prefix': 'w',
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'name': '10',
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'shift_op': 'sxtw',
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'immediate': {'value': '2'},
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'shift': [{'value': '2'}],
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"memory": {
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"offset": None,
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"base": {"prefix": "x", "name": "11"},
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"index": {
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||||
"prefix": "w",
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"name": "10",
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"shift_op": "sxtw",
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"immediate": {"value": "2"},
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"shift": [{"value": "2"}],
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||||
},
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||||
'scale': 4,
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||||
"scale": 4,
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||||
}
|
||||
},
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],
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'directive': None,
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||||
'comment': '= <<2',
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||||
'label': None,
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'line': 'ldr s0, [x11, w10, sxtw #2] // = <<2',
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'line_number': 4,
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"directive": None,
|
||||
"comment": "= <<2",
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||||
"label": None,
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||||
"line": "ldr s0, [x11, w10, sxtw #2] // = <<2",
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||||
"line_number": 4,
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||||
}
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||||
instruction_form_5 = {
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||||
'instruction': 'prfm',
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||||
'operands': [
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||||
{'prfop': {'type': ['PLD'], 'target': ['L1'], 'policy': ['KEEP']}},
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||||
"instruction": "prfm",
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||||
"operands": [
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||||
{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
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||||
{
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||||
'memory': {
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||||
'offset': {'value': '2048'},
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||||
'base': {'prefix': 'x', 'name': '26'},
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||||
'index': None,
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||||
'scale': 1,
|
||||
"memory": {
|
||||
"offset": {"value": "2048"},
|
||||
"base": {"prefix": "x", "name": "26"},
|
||||
"index": None,
|
||||
"scale": 1,
|
||||
}
|
||||
},
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||||
],
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||||
'directive': None,
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||||
'comment': 'HPL',
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||||
'label': None,
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'line': 'prfm pldl1keep, [x26, #2048] //HPL',
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||||
'line_number': 5,
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||||
"directive": None,
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||||
"comment": "HPL",
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||||
"label": None,
|
||||
"line": "prfm pldl1keep, [x26, #2048] //HPL",
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||||
"line_number": 5,
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||||
}
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instruction_form_6 = {
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'instruction': 'stp',
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||||
'operands': [
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||||
{'register': {'prefix': 'x', 'name': '29'}},
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||||
{'register': {'prefix': 'x', 'name': '30'}},
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||||
"instruction": "stp",
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||||
"operands": [
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||||
{"register": {"prefix": "x", "name": "29"}},
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||||
{"register": {"prefix": "x", "name": "30"}},
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||||
{
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||||
'memory': {
|
||||
'offset': {'value': '-16'},
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||||
'base': {'name': 'sp', 'prefix': 'x'},
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||||
'index': None,
|
||||
'scale': 1,
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||||
'pre_indexed': True,
|
||||
"memory": {
|
||||
"offset": {"value": "-16"},
|
||||
"base": {"name": "sp", "prefix": "x"},
|
||||
"index": None,
|
||||
"scale": 1,
|
||||
"pre_indexed": True,
|
||||
}
|
||||
},
|
||||
],
|
||||
'directive': None,
|
||||
'comment': None,
|
||||
'label': None,
|
||||
'line': 'stp x29, x30, [sp, #-16]!',
|
||||
'line_number': 6,
|
||||
"directive": None,
|
||||
"comment": None,
|
||||
"label": None,
|
||||
"line": "stp x29, x30, [sp, #-16]!",
|
||||
"line_number": 6,
|
||||
}
|
||||
instruction_form_7 = {
|
||||
'instruction': 'ldp',
|
||||
'operands': [
|
||||
{'register': {'prefix': 'q', 'name': '2'}},
|
||||
{'register': {'prefix': 'q', 'name': '3'}},
|
||||
"instruction": "ldp",
|
||||
"operands": [
|
||||
{"register": {"prefix": "q", "name": "2"}},
|
||||
{"register": {"prefix": "q", "name": "3"}},
|
||||
{
|
||||
'memory': {
|
||||
'offset': None,
|
||||
'base': {'prefix': 'x', 'name': '11'},
|
||||
'index': None,
|
||||
'scale': 1,
|
||||
'post_indexed': {'value': '64'},
|
||||
"memory": {
|
||||
"offset": None,
|
||||
"base": {"prefix": "x", "name": "11"},
|
||||
"index": None,
|
||||
"scale": 1,
|
||||
"post_indexed": {"value": "64"},
|
||||
}
|
||||
},
|
||||
],
|
||||
'directive': None,
|
||||
'comment': None,
|
||||
'label': None,
|
||||
'line': 'ldp q2, q3, [x11], #64',
|
||||
'line_number': 7,
|
||||
"directive": None,
|
||||
"comment": None,
|
||||
"label": None,
|
||||
"line": "ldp q2, q3, [x11], #64",
|
||||
"line_number": 7,
|
||||
}
|
||||
instruction_form_8 = {
|
||||
'instruction': 'fcmla',
|
||||
'operands': [
|
||||
{'register': {'prefix': 'z', 'name': '26', 'shape': 'd'}},
|
||||
{'register': {'prefix': 'p', 'name': '0', 'predication': 'm'}},
|
||||
{'register': {'prefix': 'z', 'name': '29', 'shape': 'd'}},
|
||||
{'register': {'prefix': 'z', 'name': '21', 'shape': 'd'}},
|
||||
{'immediate': {'value': '90'}},
|
||||
"instruction": "fcmla",
|
||||
"operands": [
|
||||
{"register": {"prefix": "z", "name": "26", "shape": "d"}},
|
||||
{"register": {"prefix": "p", "name": "0", "predication": "m"}},
|
||||
{"register": {"prefix": "z", "name": "29", "shape": "d"}},
|
||||
{"register": {"prefix": "z", "name": "21", "shape": "d"}},
|
||||
{"immediate": {"value": "90"}},
|
||||
],
|
||||
'directive': None,
|
||||
'comment': None,
|
||||
'label': None,
|
||||
'line': 'fcmla z26.d, p0/m, z29.d, z21.d, #90',
|
||||
'line_number': 8,
|
||||
"directive": None,
|
||||
"comment": None,
|
||||
"label": None,
|
||||
"line": "fcmla z26.d, p0/m, z29.d, z21.d, #90",
|
||||
"line_number": 8,
|
||||
}
|
||||
|
||||
parsed_1 = self.parser.parse_line(line_comment, 1)
|
||||
@@ -307,15 +303,15 @@ class TestParserAArch64(unittest.TestCase):
|
||||
self.assertEqual(len(parsed), 645)
|
||||
|
||||
def test_normalize_imd(self):
|
||||
imd_decimal_1 = {'value': '79'}
|
||||
imd_hex_1 = {'value': '0x4f'}
|
||||
imd_decimal_2 = {'value': '8'}
|
||||
imd_hex_2 = {'value': '0x8'}
|
||||
imd_float_11 = {'float': {'mantissa': '0.79', 'e_sign': '+', 'exponent': '2'}}
|
||||
imd_float_12 = {'float': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
|
||||
imd_double_11 = {'double': {'mantissa': '0.79', 'e_sign': '+', 'exponent': '2'}}
|
||||
imd_double_12 = {'double': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
|
||||
identifier = {'identifier': {'name': '..B1.4'}}
|
||||
imd_decimal_1 = {"value": "79"}
|
||||
imd_hex_1 = {"value": "0x4f"}
|
||||
imd_decimal_2 = {"value": "8"}
|
||||
imd_hex_2 = {"value": "0x8"}
|
||||
imd_float_11 = {"float": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
|
||||
imd_float_12 = {"float": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
|
||||
imd_double_11 = {"double": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
|
||||
imd_double_12 = {"double": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
|
||||
identifier = {"identifier": {"name": "..B1.4"}}
|
||||
|
||||
value1 = self.parser.normalize_imd(imd_decimal_1)
|
||||
self.assertEqual(value1, self.parser.normalize_imd(imd_hex_1))
|
||||
@@ -329,27 +325,28 @@ class TestParserAArch64(unittest.TestCase):
|
||||
self.assertEqual(self.parser.normalize_imd(identifier), identifier)
|
||||
|
||||
def test_multiple_regs(self):
|
||||
instr_range = 'PUSH {x5-x7}'
|
||||
reg_range = AttrDict({
|
||||
'register': {
|
||||
'range': [
|
||||
{'prefix': 'x', 'name': '5'},
|
||||
{'prefix': 'x', 'name': '7'}
|
||||
],
|
||||
'index': None
|
||||
instr_range = "PUSH {x5-x7}"
|
||||
reg_range = AttrDict(
|
||||
{
|
||||
"register": {
|
||||
"range": [{"prefix": "x", "name": "5"}, {"prefix": "x", "name": "7"}],
|
||||
"index": None,
|
||||
}
|
||||
}
|
||||
})
|
||||
instr_list = 'POP {x5, x7, x9}'
|
||||
reg_list = AttrDict({
|
||||
'register': {
|
||||
'list': [
|
||||
{'prefix': 'x', 'name': '5'},
|
||||
{'prefix': 'x', 'name': '7'},
|
||||
{'prefix': 'x', 'name': '9'}
|
||||
],
|
||||
'index': None
|
||||
)
|
||||
instr_list = "POP {x5, x7, x9}"
|
||||
reg_list = AttrDict(
|
||||
{
|
||||
"register": {
|
||||
"list": [
|
||||
{"prefix": "x", "name": "5"},
|
||||
{"prefix": "x", "name": "7"},
|
||||
{"prefix": "x", "name": "9"},
|
||||
],
|
||||
"index": None,
|
||||
}
|
||||
}
|
||||
})
|
||||
)
|
||||
prange = self.parser.parse_line(instr_range)
|
||||
plist = self.parser.parse_line(instr_list)
|
||||
|
||||
@@ -357,22 +354,22 @@ class TestParserAArch64(unittest.TestCase):
|
||||
self.assertEqual(plist.operands[0], reg_list)
|
||||
|
||||
def test_reg_dependency(self):
|
||||
reg_1_1 = AttrDict({'prefix': 'b', 'name': '1'})
|
||||
reg_1_2 = AttrDict({'prefix': 'h', 'name': '1'})
|
||||
reg_1_3 = AttrDict({'prefix': 's', 'name': '1'})
|
||||
reg_1_4 = AttrDict({'prefix': 'd', 'name': '1'})
|
||||
reg_1_4 = AttrDict({'prefix': 'q', 'name': '1'})
|
||||
reg_2_1 = AttrDict({'prefix': 'w', 'name': '2'})
|
||||
reg_2_2 = AttrDict({'prefix': 'x', 'name': '2'})
|
||||
reg_v1_1 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '16', 'shape': 'b'})
|
||||
reg_v1_2 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '8', 'shape': 'h'})
|
||||
reg_v1_3 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '4', 'shape': 's'})
|
||||
reg_v1_4 = AttrDict({'prefix': 'v', 'name': '11', 'lanes': '2', 'shape': 'd'})
|
||||
reg_1_1 = AttrDict({"prefix": "b", "name": "1"})
|
||||
reg_1_2 = AttrDict({"prefix": "h", "name": "1"})
|
||||
reg_1_3 = AttrDict({"prefix": "s", "name": "1"})
|
||||
reg_1_4 = AttrDict({"prefix": "d", "name": "1"})
|
||||
reg_1_4 = AttrDict({"prefix": "q", "name": "1"})
|
||||
reg_2_1 = AttrDict({"prefix": "w", "name": "2"})
|
||||
reg_2_2 = AttrDict({"prefix": "x", "name": "2"})
|
||||
reg_v1_1 = AttrDict({"prefix": "v", "name": "11", "lanes": "16", "shape": "b"})
|
||||
reg_v1_2 = AttrDict({"prefix": "v", "name": "11", "lanes": "8", "shape": "h"})
|
||||
reg_v1_3 = AttrDict({"prefix": "v", "name": "11", "lanes": "4", "shape": "s"})
|
||||
reg_v1_4 = AttrDict({"prefix": "v", "name": "11", "lanes": "2", "shape": "d"})
|
||||
|
||||
reg_b5 = AttrDict({'prefix': 'b', 'name': '5'})
|
||||
reg_q15 = AttrDict({'prefix': 'q', 'name': '15'})
|
||||
reg_v10 = AttrDict({'prefix': 'v', 'name': '10', 'lanes': '2', 'shape': 's'})
|
||||
reg_v20 = AttrDict({'prefix': 'v', 'name': '20', 'lanes': '2', 'shape': 'd'})
|
||||
reg_b5 = AttrDict({"prefix": "b", "name": "5"})
|
||||
reg_q15 = AttrDict({"prefix": "q", "name": "15"})
|
||||
reg_v10 = AttrDict({"prefix": "v", "name": "10", "lanes": "2", "shape": "s"})
|
||||
reg_v20 = AttrDict({"prefix": "v", "name": "20", "lanes": "2", "shape": "d"})
|
||||
|
||||
reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
|
||||
reg_2 = [reg_2_1, reg_2_2]
|
||||
@@ -406,7 +403,7 @@ class TestParserAArch64(unittest.TestCase):
|
||||
# Helper functions
|
||||
##################
|
||||
def _get_comment(self, parser, comment):
|
||||
return ' '.join(
|
||||
return " ".join(
|
||||
AttrDict.convert_dict(
|
||||
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())
|
||||
).comment
|
||||
@@ -425,11 +422,11 @@ class TestParserAArch64(unittest.TestCase):
|
||||
@staticmethod
|
||||
def _find_file(name):
|
||||
testdir = os.path.dirname(__file__)
|
||||
name = os.path.join(testdir, 'test_files', name)
|
||||
name = os.path.join(testdir, "test_files", name)
|
||||
assert os.path.exists(name)
|
||||
return name
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
if __name__ == "__main__":
|
||||
suite = unittest.TestLoader().loadTestsFromTestCase(TestParserAArch64)
|
||||
unittest.TextTestRunner(verbosity=2).run(suite)
|
||||
|
||||
Reference in New Issue
Block a user