From 63cb61b42396b0f5994e6265b009e1b5d63efab3 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Thu, 14 Aug 2025 13:34:45 +0200 Subject: [PATCH] add pseudo-ops for vcmpps/vcmppd --- osaca/data/skx.yml | 48 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/osaca/data/skx.yml b/osaca/data/skx.yml index 8cb77b7..902c882 100644 --- a/osaca/data/skx.yml +++ b/osaca/data/skx.yml @@ -5004,6 +5004,54 @@ instruction_forms: port_pressure: [[1, '01']] # uops.info import throughput: 0.5 # uops.info import uops: 1 # uops.info import +- name: [VCMPEQPD, VCMPLTPD, VCMPLEPD, VCMPUNORDPD, VCMPNEQPD, VCMPNLTPD, VCMPNLEPD, VCMPORDPD, VCMPEQ_UQPD, VCMPNGEPD, VCMPNGTPD, VCMPFALSEPD, VCMPNEQ_OQPD, VCMPGEPD, VCMPGTPD, VCMPTRUEPD, VCMPEQ_OSPD, VCMPLT_OQPD, VCMPLE_OQPD, VCMPUNORD_SPD, VCMPNEQ_USPD, VCMPNLT_UQPD, VCMPNLE_UQPD, VCMPORD_SPD, VCMPEQ_USPD, VCMPNGE_UQPD, VCMPNGT_UQPD, VCMPFALSE_OSPD, VCMPNEQ_OSPD, VCMPGE_OQPD, VCMPGT_OQPD, VCMPTRUE_USPD] # VCMPPD pseudo-op + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: [VCMPEQPD, VCMPLTPD, VCMPLEPD, VCMPUNORDPD, VCMPNEQPD, VCMPNLTPD, VCMPNLEPD, VCMPORDPD, VCMPEQ_UQPD, VCMPNGEPD, VCMPNGTPD, VCMPFALSEPD, VCMPNEQ_OQPD, VCMPGEPD, VCMPGTPD, VCMPTRUEPD, VCMPEQ_OSPD, VCMPLT_OQPD, VCMPLE_OQPD, VCMPUNORD_SPD, VCMPNEQ_USPD, VCMPNLT_UQPD, VCMPNLE_UQPD, VCMPORD_SPD, VCMPEQ_USPD, VCMPNGE_UQPD, VCMPNGT_UQPD, VCMPFALSE_OSPD, VCMPNEQ_OSPD, VCMPGE_OQPD, VCMPGT_OQPD, VCMPTRUE_USPD] # VCMPPD pseudo-op + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: [VCMPEQPS, VCMPLTPS, VCMPLEPS, VCMPUNORDPS, VCMPNEQPS, VCMPNLTPS, VCMPNLEPS, VCMPORDPS, VCMPEQ_UQPS, VCMPNGEPS, VCMPNGTPS, VCMPFALSEPS, VCMPNEQ_OQPS, VCMPGEPS, VCMPGTPS, VCMPTRUEPS, VCMPEQ_OSPS, VCMPLT_OQPS, VCMPLE_OQPS, VCMPUNORD_SPS, VCMPNEQ_USPS, VCMPNLT_UQPS, VCMPNLE_UQPS, VCMPORD_SPS, VCMPEQ_USPS, VCMPNGE_UQPS, VCMPNGT_UQPS, VCMPFALSE_OSPS, VCMPNEQ_OSPS, VCMPGE_OQPS, VCMPGT_OQPS, VCMPTRUE_USPS] # VCMPPS pseudo-op + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: [VCMPEQPS, VCMPLTPS, VCMPLEPS, VCMPUNORDPS, VCMPNEQPS, VCMPNLTPS, VCMPNLEPS, VCMPORDPS, VCMPEQ_UQPS, VCMPNGEPS, VCMPNGTPS, VCMPFALSEPS, VCMPNEQ_OQPS, VCMPGEPS, VCMPGTPS, VCMPTRUEPS, VCMPEQ_OSPS, VCMPLT_OQPS, VCMPLE_OQPS, VCMPUNORD_SPS, VCMPNEQ_USPS, VCMPNLT_UQPS, VCMPNLE_UQPS, VCMPORD_SPS, VCMPEQ_USPS, VCMPNGE_UQPS, VCMPNGT_UQPS, VCMPFALSE_OSPS, VCMPNEQ_OSPS, VCMPGE_OQPS, VCMPGT_OQPS, VCMPTRUE_USPS] # VCMPPS pseudo-op + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 - name: VCMPSD # uops.info import operands: # uops.info import - class: immediate # uops.info import