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added reg-only fallback for mem-instructions not found in ISA DB

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JanLJL
2020-03-10 17:15:57 +01:00
parent 381e9e9f76
commit 666512d54d
3 changed files with 77 additions and 57 deletions
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10
osaca/semantics/arch_semantics.py
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@@ -348,16 +348,6 @@ class ArchSemantics(ISASemantics):
flags.append(INSTR_FLAGS.LD)
return throughput, port_pressure, latency, latency_wo_load
def substitute_mem_address(self, operands):
"""Create memory wildcard for all memory operands"""
# reg_ops = [op for op in operands if 'register' in op]
# reg_type = self._parser.get_reg_type(reg_ops[0]['register'])
return [self._create_reg_wildcard() if 'memory' in op else op for op in operands]
def _create_reg_wildcard(self):
"""Wildcard constructor"""
return {'*': '*'}
def convert_op_to_reg(self, reg_type, reg_id='0'):
"""Create register operand for a memory addressing operand"""
if self._isa == 'x86':