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JanLJL
2019-08-09 09:52:09 +02:00
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commit 7183b767f2
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@@ -13,13 +13,16 @@ auto-generating of testcases for assembly instructions creating latency
and throughput benchmarks on a specific instruction form and throughput
analysis and throughput prediction for a innermost loop kernel.
.. image:: https://travis-ci.com/RRZE-HPC/OSACA.svg?token=393L6z2HEXNiGLtZ43s6&branch=master
:target: https://travis-ci.com/RRZE-HPC/OSACA
.. image:: https://travis-ci.com/RRZE-HPC/OSACA.svg?branch=v3
:target: https://travis-ci.com/RRZE-HPC/OSACA?branch=v3
.. ..image:: https://landscape.io/github/RRZE-HPC/OSACA/master/landscape.svg?style=flat&badge_auth_token=c95f01b247f94bc79c09d21c5c827697
.. :target: https://landscape.io/github/RRZE-HPC/OSACA/master
.. :alt: Code Health
.. image:: https://codecov.io/github/RRZE-HPC/OSACA/coverage.svg?branch=v3
:target: https://codecov.io/github/RRZE-HPC/OSACA?branch=v3
.. image:: https://img.shields.io/badge/code%20style-black-000000.svg
:target: https://github.com/ambv/black