diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml
index e4121dc..8f2d071 100644
--- a/osaca/data/tsv110.yml
+++ b/osaca/data/tsv110.yml
@@ -177,7 +177,7 @@ instruction_forms:
   port_pressure: [[1, '012']]
   uops: 1
 # logical instructions: orn (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
-- name: orr
+- name: orn
   operands:
   - class: register
     prefix: x
@@ -189,7 +189,7 @@ instruction_forms:
   latency: 1.0
   port_pressure: [[1, '012']]
   uops: 1
-- name: orr
+- name: orn
   operands:
   - class: register
     prefix: w
@@ -201,21 +201,30 @@ instruction_forms:
   latency: 1.0
   port_pressure: [[1, '012']]
   uops: 1
-- name: orr
+- name: orn
   operands:
   - class: register
-    prefix: v
-    shape: '*'
+    prefix: x
   - class: register
-    prefix: v
-    shape: '*'
+    prefix: x
+  - class: immediate
+    imd: int
+  throughput: 0.3333
+  latency: 1.0
+  port_pressure: [[1, '012']]
+  uops: 1
+- name: orn
+  operands:
   - class: register
-    prefix: v
-    shape: '*'
-  throughput: 1
-  latency: 2.0
-  port_pressure: [[1, '4'], [1, '5']]
-  uops: 2
+    prefix: w
+  - class: register
+    prefix: w
+  - class: immediate
+    imd: int
+  throughput: 0.3333
+  latency: 1.0
+  port_pressure: [[1, '012']]
+  uops: 1
 # logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
 - name: eor
   operands:
diff --git a/osaca/parser/parser_AArch64.py b/osaca/parser/parser_AArch64.py
index 705813c..3e80f83 100755
--- a/osaca/parser/parser_AArch64.py
+++ b/osaca/parser/parser_AArch64.py
@@ -104,6 +104,7 @@ class ParserAArch64(BaseParser):
             ^ pp.CaselessLiteral("ror")
             ^ pp.CaselessLiteral("sxtw")
             ^ pp.CaselessLiteral("uxtw")
+            ^ pp.CaselessLiteral("uxtb")
             ^ pp.CaselessLiteral("mul vl")
         )
         arith_immediate = pp.Group(
@@ -384,7 +385,7 @@ class ParserAArch64(BaseParser):
             base["prefix"] = "x"
         if index is not None and "name" in index and index["name"] == "sp":
             index["prefix"] = "x"
-        valid_shift_ops = ["lsl", "uxtw", "sxtw"]
+        valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"]
         if "index" in memory_address:
             if "shift" in memory_address["index"]:
                 if memory_address["index"]["shift_op"].lower() in valid_shift_ops: