mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 09:00:05 +01:00
Removed comments from operands
This commit is contained in:
stefandesouza
@@ -8,7 +8,7 @@ import unittest
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from pyparsing import ParseException
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from osaca.parser import ParserAArch64, instructionForm
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from osaca.parser import ParserAArch64, InstructionForm
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from osaca.parser.directive import DirectiveOperand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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@@ -38,40 +38,40 @@ class TestParserAArch64(unittest.TestCase):
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)
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def test_label_parser(self):
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self.assertEqual(self._get_label(self.parser, "main:").name, "main")
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self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
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self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
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self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1").name, ".L1")
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self.assertEqual(self._get_label(self.parser, "main:")[0].name, "main")
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self.assertEqual(self._get_label(self.parser, "..B1.10:")[0].name, "..B1.10")
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self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:")[0].name, ".2.3_2_pack.3")
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self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1")[0].name, ".L1")
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self.assertEqual(
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" ".join(self._get_label(self.parser, ".L1:\t\t\t//label1").comment),
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" ".join(self._get_label(self.parser, ".L1:\t\t\t//label1")[1]),
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"label1",
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)
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with self.assertRaises(ParseException):
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self._get_label(self.parser, "\t.cfi_startproc")
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def test_directive_parser(self):
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self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
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self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
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self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
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self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
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self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text")
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self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0)
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self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align")
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self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2)
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self.assertEqual(
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self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
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self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90"
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)
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self.assertEqual(
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START").name,
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[0].name,
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"byte",
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)
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self.assertEqual(
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self._get_directive(
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self.parser, " .byte 100,103,144 //IACA START"
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).parameters[2],
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)[0].parameters[2],
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"144",
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)
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self.assertEqual(
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" ".join(
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self._get_directive(
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self.parser, " .byte 100,103,144 //IACA START"
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).comment
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)[1]
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),
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"IACA START",
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)
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@@ -105,25 +105,25 @@ class TestParserAArch64(unittest.TestCase):
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parsed_8 = self.parser.parse_instruction(instr8)
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parsed_9 = self.parser.parse_instruction(instr9)
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self.assertEqual(parsed_1.instruction, "vcvt.F32.S32")
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self.assertEqual(parsed_1.mnemonic, "vcvt.F32.S32")
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self.assertEqual(parsed_1.operands[0].name, "1")
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self.assertEqual(parsed_1.operands[0].prefix, "w")
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self.assertEqual(parsed_1.operands[1].name, "2")
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self.assertEqual(parsed_1.operands[1].prefix, "w")
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self.assertEqual(parsed_1.comment, "12.27")
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self.assertEqual(parsed_2.instruction, "b.lo")
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self.assertEqual(parsed_2.mnemonic, "b.lo")
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self.assertEqual(parsed_2.operands[0].name, "..B1.4")
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self.assertEqual(len(parsed_2.operands), 1)
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self.assertIsNone(parsed_2.comment)
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self.assertEqual(parsed_3.instruction, "mov")
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self.assertEqual(parsed_3.mnemonic, "mov")
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self.assertEqual(parsed_3.operands[0].name, "2")
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self.assertEqual(parsed_3.operands[0].prefix, "x")
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self.assertEqual(parsed_3.operands[1].value, int("0x222", 0))
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self.assertEqual(parsed_3.comment, "NOT IACA END")
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self.assertEqual(parsed_4.instruction, "str")
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self.assertEqual(parsed_4.mnemonic, "str")
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self.assertIsNone(parsed_4.operands[1].offset)
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self.assertEqual(parsed_4.operands[1].base.name, "sp")
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self.assertEqual(parsed_4.operands[1].base.prefix, "x")
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@@ -134,7 +134,7 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_4.operands[0].prefix, "x")
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self.assertEqual(parsed_4.comment, "12.9")
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self.assertEqual(parsed_5.instruction, "ldr")
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self.assertEqual(parsed_5.mnemonic, "ldr")
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self.assertEqual(parsed_5.operands[0].name, "0")
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self.assertEqual(parsed_5.operands[0].prefix, "x")
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self.assertEqual(parsed_5.operands[1].offset.name, "q2c")
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@@ -144,20 +144,20 @@ class TestParserAArch64(unittest.TestCase):
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self.assertIsNone(parsed_5.operands[1].index)
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self.assertEqual(parsed_5.operands[1].scale, 1)
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self.assertEqual(parsed_6.instruction, "adrp")
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self.assertEqual(parsed_6.mnemonic, "adrp")
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self.assertEqual(parsed_6.operands[0].name, "0")
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self.assertEqual(parsed_6.operands[0].prefix, "x")
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self.assertEqual(parsed_6.operands[1].relocation, ":got:")
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self.assertEqual(parsed_6.operands[1].name, "visited")
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self.assertEqual(parsed_7.instruction, "fadd")
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self.assertEqual(parsed_7.mnemonic, "fadd")
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self.assertEqual(parsed_7.operands[0].name, "17")
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self.assertEqual(parsed_7.operands[0].prefix, "v")
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self.assertEqual(parsed_7.operands[0].lanes, "2")
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self.assertEqual(parsed_7.operands[0].shape, "d")
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self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2]), "v1.2d")
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self.assertEqual(parsed_8.instruction, "mov.d")
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self.assertEqual(parsed_8.mnemonic, "mov.d")
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self.assertEqual(parsed_8.operands[0].name, "0")
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self.assertEqual(parsed_8.operands[0].prefix, "x")
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self.assertEqual(parsed_8.operands[1].name, "16")
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@@ -165,7 +165,7 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_8.operands[1].index, "1")
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self.assertEqual(self.parser.get_full_reg_name(parsed_8.operands[1]), "v16.d[1]")
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self.assertEqual(parsed_9.instruction, "ccmp")
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self.assertEqual(parsed_9.mnemonic, "ccmp")
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self.assertEqual(parsed_9.operands[0].name, "0")
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self.assertEqual(parsed_9.operands[0].prefix, "x")
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self.assertEqual(parsed_9.operands[3].ccode, "CC")
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@@ -181,8 +181,8 @@ class TestParserAArch64(unittest.TestCase):
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line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90"
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line_conditions = "ccmn x11, #1, #3, eq"
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instruction_form_1 = instructionForm(
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instruction_id=None,
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instruction_form_1 = InstructionForm(
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mnemonic=None,
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operands_id=[],
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directive_id=None,
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comment_id="-- Begin main",
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@@ -191,8 +191,8 @@ class TestParserAArch64(unittest.TestCase):
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line_number=1,
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)
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instruction_form_2 = instructionForm(
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instruction_id=None,
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instruction_form_2 = InstructionForm(
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mnemonic=None,
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operands_id=[],
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directive_id=None,
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comment_id="=>This Inner Loop Header: Depth=1",
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@@ -200,8 +200,8 @@ class TestParserAArch64(unittest.TestCase):
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line=".LBB0_1: // =>This Inner Loop Header: Depth=1",
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line_number=2,
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)
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instruction_form_3 = instructionForm(
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instruction_id=None,
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instruction_form_3 = InstructionForm(
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mnemonic=None,
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operands_id=[],
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directive_id=DirectiveOperand(name="cfi_def_cfa", parameter_id=["w29", "-16"]),
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comment_id=None,
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@@ -209,17 +209,17 @@ class TestParserAArch64(unittest.TestCase):
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line=".cfi_def_cfa w29, -16",
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line_number=3,
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)
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instruction_form_4 = instructionForm(
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instruction_id="ldr",
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instruction_form_4 = InstructionForm(
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mnemonic="ldr",
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operands_id=[
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RegisterOperand(prefix_id="s", name="0"),
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RegisterOperand(prefix="s", name="0"),
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MemoryOperand(
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offset_ID=None,
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base_id=RegisterOperand(prefix_id="x", name="11"),
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index_id=RegisterOperand(
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prefix_id="w", name="10", shift_op="sxtw", shift=[{"value": "2"}]
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offset=None,
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base=RegisterOperand(prefix="x", name="11"),
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index=RegisterOperand(
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prefix="w", name="10", shift_op="sxtw", shift=[{"value": "2"}]
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),
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scale_id=4,
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scale=4,
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),
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],
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directive_id=None,
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@@ -228,15 +228,15 @@ class TestParserAArch64(unittest.TestCase):
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line="ldr s0, [x11, w10, sxtw #2] // = <<2",
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line_number=4,
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)
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instruction_form_5 = instructionForm(
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instruction_id="prfm",
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instruction_form_5 = InstructionForm(
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mnemonic="prfm",
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operands_id=[
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{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
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MemoryOperand(
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offset_ID=ImmediateOperand(value_id=2048),
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base_id=RegisterOperand(prefix_id="x", name="26"),
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index_id=None,
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scale_id=1,
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offset=ImmediateOperand(value_id=2048),
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base=RegisterOperand(prefix="x", name="26"),
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index=None,
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scale=1,
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),
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],
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directive_id=None,
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@@ -245,16 +245,16 @@ class TestParserAArch64(unittest.TestCase):
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line="prfm pldl1keep, [x26, #2048] //HPL",
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line_number=5,
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)
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instruction_form_6 = instructionForm(
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instruction_id="stp",
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instruction_form_6 = InstructionForm(
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mnemonic="stp",
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operands_id=[
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RegisterOperand(prefix_id="x", name="29"),
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RegisterOperand(prefix_id="x", name="30"),
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RegisterOperand(prefix="x", name="29"),
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RegisterOperand(prefix="x", name="30"),
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MemoryOperand(
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offset_ID=ImmediateOperand(value_id=-16),
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base_id=RegisterOperand(name="sp", prefix_id="x"),
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index_id=None,
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scale_id=1,
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offset=ImmediateOperand(value_id=-16),
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base=RegisterOperand(name="sp", prefix="x"),
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index=None,
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scale=1,
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pre_indexed=True,
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),
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],
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@@ -264,16 +264,16 @@ class TestParserAArch64(unittest.TestCase):
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line="stp x29, x30, [sp, #-16]!",
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line_number=6,
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)
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instruction_form_7 = instructionForm(
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instruction_id="ldp",
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instruction_form_7 = InstructionForm(
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mnemonic="ldp",
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operands_id=[
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RegisterOperand(prefix_id="q", name="2"),
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RegisterOperand(prefix_id="q", name="3"),
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RegisterOperand(prefix="q", name="2"),
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RegisterOperand(prefix="q", name="3"),
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MemoryOperand(
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offset_ID=None,
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base_id=RegisterOperand(name="11", prefix_id="x"),
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index_id=None,
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scale_id=1,
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offset=None,
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base=RegisterOperand(name="11", prefix="x"),
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index=None,
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scale=1,
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post_indexed={"value": 64},
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),
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],
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@@ -283,13 +283,13 @@ class TestParserAArch64(unittest.TestCase):
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line="ldp q2, q3, [x11], #64",
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line_number=7,
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)
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instruction_form_8 = instructionForm(
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instruction_id="fcmla",
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instruction_form_8 = InstructionForm(
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mnemonic="fcmla",
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operands_id=[
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RegisterOperand(prefix_id="z", name="26", shape="d"),
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RegisterOperand(prefix_id="p", name="0", predication="m"),
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RegisterOperand(prefix_id="z", name="29", shape="d"),
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RegisterOperand(prefix_id="z", name="21", shape="d"),
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RegisterOperand(prefix="z", name="26", shape="d"),
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RegisterOperand(prefix="p", name="0", predication="m"),
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RegisterOperand(prefix="z", name="29", shape="d"),
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RegisterOperand(prefix="z", name="21", shape="d"),
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ImmediateOperand(value_id=90, type_id="int"),
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],
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directive_id=None,
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@@ -298,10 +298,10 @@ class TestParserAArch64(unittest.TestCase):
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line="fcmla z26.d, p0/m, z29.d, z21.d, #90",
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line_number=8,
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)
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instruction_form_9 = instructionForm(
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instruction_id="ccmn",
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instruction_form_9 = InstructionForm(
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mnemonic="ccmn",
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operands_id=[
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RegisterOperand(prefix_id="x", name="11"),
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RegisterOperand(prefix="x", name="11"),
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ImmediateOperand(value_id=1, type_id="int"),
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ImmediateOperand(value_id=3, type_id="int"),
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{"condition": "EQ"},
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@@ -376,17 +376,17 @@ class TestParserAArch64(unittest.TestCase):
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instr_list_with_index = "ld4 {v0.S, v1.S, v2.S, v3.S}[2]"
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instr_range_single = "dummy { z1.d }"
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reg_list = [
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RegisterOperand(prefix_id="x", name="5"),
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RegisterOperand(prefix_id="x", name="6"),
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RegisterOperand(prefix_id="x", name="7"),
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RegisterOperand(prefix="x", name="5"),
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RegisterOperand(prefix="x", name="6"),
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RegisterOperand(prefix="x", name="7"),
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]
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reg_list_idx = [
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RegisterOperand(prefix_id="v", name="0", shape="S", index=2),
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RegisterOperand(prefix_id="v", name="1", shape="S", index=2),
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RegisterOperand(prefix_id="v", name="2", shape="S", index=2),
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RegisterOperand(prefix_id="v", name="3", shape="S", index=2),
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RegisterOperand(prefix="v", name="0", shape="S", index=2),
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RegisterOperand(prefix="v", name="1", shape="S", index=2),
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RegisterOperand(prefix="v", name="2", shape="S", index=2),
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RegisterOperand(prefix="v", name="3", shape="S", index=2),
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]
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reg_list_single = [RegisterOperand(prefix_id="z", name="1", shape="d")]
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reg_list_single = [RegisterOperand(prefix="z", name="1", shape="d")]
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prange = self.parser.parse_line(instr_range)
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plist = self.parser.parse_line(instr_list)
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@@ -401,22 +401,22 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(p_single.operands, reg_list_single)
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def test_reg_dependency(self):
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reg_1_1 = RegisterOperand(prefix_id="b", name="1")
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reg_1_2 = RegisterOperand(prefix_id="h", name="1")
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reg_1_3 = RegisterOperand(prefix_id="s", name="1")
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reg_1_4 = RegisterOperand(prefix_id="d", name="1")
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reg_1_4 = RegisterOperand(prefix_id="q", name="1")
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reg_2_1 = RegisterOperand(prefix_id="w", name="2")
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reg_2_2 = RegisterOperand(prefix_id="x", name="2")
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reg_v1_1 = RegisterOperand(prefix_id="v", name="11", lanes="16", shape="b")
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reg_v1_2 = RegisterOperand(prefix_id="v", name="11", lanes="8", shape="h")
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reg_v1_3 = RegisterOperand(prefix_id="v", name="11", lanes="4", shape="s")
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reg_v1_4 = RegisterOperand(prefix_id="v", name="11", lanes="2", shape="d")
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reg_1_1 = RegisterOperand(prefix="b", name="1")
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reg_1_2 = RegisterOperand(prefix="h", name="1")
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reg_1_3 = RegisterOperand(prefix="s", name="1")
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reg_1_4 = RegisterOperand(prefix="d", name="1")
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reg_1_4 = RegisterOperand(prefix="q", name="1")
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reg_2_1 = RegisterOperand(prefix="w", name="2")
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reg_2_2 = RegisterOperand(prefix="x", name="2")
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reg_v1_1 = RegisterOperand(prefix="v", name="11", lanes="16", shape="b")
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reg_v1_2 = RegisterOperand(prefix="v", name="11", lanes="8", shape="h")
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reg_v1_3 = RegisterOperand(prefix="v", name="11", lanes="4", shape="s")
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reg_v1_4 = RegisterOperand(prefix="v", name="11", lanes="2", shape="d")
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reg_b5 = RegisterOperand(prefix_id="b", name="5")
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reg_q15 = RegisterOperand(prefix_id="q", name="15")
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reg_v10 = RegisterOperand(prefix_id="v", name="10", lanes="2", shape="s")
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reg_v20 = RegisterOperand(prefix_id="v", name="20", lanes="2", shape="d")
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reg_b5 = RegisterOperand(prefix="b", name="5")
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reg_q15 = RegisterOperand(prefix="q", name="15")
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reg_v10 = RegisterOperand(prefix="v", name="10", lanes="2", shape="s")
|
||||
reg_v20 = RegisterOperand(prefix="v", name="20", lanes="2", shape="d")
|
||||
|
||||
reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
|
||||
reg_2 = [reg_2_1, reg_2_2]
|
||||
|
||||
@@ -8,7 +8,7 @@ import unittest
|
||||
|
||||
from pyparsing import ParseException
|
||||
|
||||
from osaca.parser import ParserX86ATT, instructionForm
|
||||
from osaca.parser import ParserX86ATT, InstructionForm
|
||||
from osaca.parser.register import RegisterOperand
|
||||
from osaca.parser.immediate import ImmediateOperand
|
||||
|
||||
@@ -33,40 +33,40 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
)
|
||||
|
||||
def test_label_parser(self):
|
||||
self.assertEqual(self._get_label(self.parser, "main:").name, "main")
|
||||
self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
|
||||
self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
|
||||
self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t#label1").name, ".L1")
|
||||
self.assertEqual(self._get_label(self.parser, "main:")[0].name, "main")
|
||||
self.assertEqual(self._get_label(self.parser, "..B1.10:")[0].name, "..B1.10")
|
||||
self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:")[0].name, ".2.3_2_pack.3")
|
||||
self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t#label1")[0].name, ".L1")
|
||||
self.assertEqual(
|
||||
" ".join(self._get_label(self.parser, ".L1:\t\t\t#label1").comment),
|
||||
" ".join(self._get_label(self.parser, ".L1:\t\t\t#label1")[1]),
|
||||
"label1",
|
||||
)
|
||||
with self.assertRaises(ParseException):
|
||||
self._get_label(self.parser, "\t.cfi_startproc")
|
||||
|
||||
def test_directive_parser(self):
|
||||
self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
|
||||
self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
|
||||
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
|
||||
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
|
||||
self.assertEqual(len(self._get_directive(self.parser, ".text").parameters), 0)
|
||||
self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text")
|
||||
self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0)
|
||||
self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90")[0].name, "align")
|
||||
self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters), 2)
|
||||
self.assertEqual(len(self._get_directive(self.parser, ".text")[0].parameters), 0)
|
||||
self.assertEqual(
|
||||
len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"').parameters),
|
||||
len(self._get_directive(self.parser, '.file\t1 "path/to/file.c"')[0].parameters),
|
||||
2,
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(self.parser, '.file\t1 "path/to/file.c"').parameters[1],
|
||||
self._get_directive(self.parser, '.file\t1 "path/to/file.c"')[0].parameters[1],
|
||||
'"path/to/file.c"',
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(self.parser, "\t.set\tL$set$0,LECIE1-LSCIE1").parameters,
|
||||
self._get_directive(self.parser, "\t.set\tL$set$0,LECIE1-LSCIE1")[0].parameters,
|
||||
["L$set$0", "LECIE1-LSCIE1"],
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(
|
||||
self.parser,
|
||||
"\t.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support",
|
||||
).parameters,
|
||||
)[0].parameters,
|
||||
[
|
||||
"__TEXT",
|
||||
"__eh_frame",
|
||||
@@ -77,27 +77,27 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
self.assertEqual(
|
||||
self._get_directive(
|
||||
self.parser, "\t.section\t__TEXT,__literal16,16byte_literals"
|
||||
).parameters,
|
||||
)[0].parameters,
|
||||
["__TEXT", "__literal16", "16byte_literals"],
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
|
||||
self._get_directive(self.parser, "\t.align\t16,0x90")[0].parameters[1], "0x90"
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(self.parser, " .byte 100,103,144 #IACA START").name,
|
||||
self._get_directive(self.parser, " .byte 100,103,144 #IACA START")[0].name,
|
||||
"byte",
|
||||
)
|
||||
self.assertEqual(
|
||||
self._get_directive(
|
||||
self.parser, " .byte 100,103,144 #IACA START"
|
||||
).parameters[2],
|
||||
)[0].parameters[2],
|
||||
"144",
|
||||
)
|
||||
self.assertEqual(
|
||||
" ".join(
|
||||
self._get_directive(
|
||||
self.parser, " .byte 100,103,144 #IACA START"
|
||||
).comment
|
||||
)[1]
|
||||
),
|
||||
"IACA START",
|
||||
)
|
||||
@@ -119,21 +119,21 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
parsed_6 = self.parser.parse_instruction(instr6)
|
||||
parsed_7 = self.parser.parse_instruction(instr7)
|
||||
|
||||
self.assertEqual(parsed_1.instruction, "vcvtsi2ss")
|
||||
self.assertEqual(parsed_1.mnemonic, "vcvtsi2ss")
|
||||
self.assertEqual(parsed_1.operands[0].name, "edx")
|
||||
self.assertEqual(parsed_1.operands[1].name, "xmm2")
|
||||
self.assertEqual(parsed_1.comment, "12.27")
|
||||
|
||||
self.assertEqual(parsed_2.instruction, "jb")
|
||||
self.assertEqual(parsed_2.mnemonic, "jb")
|
||||
self.assertEqual(parsed_2.operands[0].name, "..B1.4")
|
||||
self.assertEqual(len(parsed_2.operands), 1)
|
||||
self.assertIsNone(parsed_2.comment)
|
||||
self.assertEqual(parsed_3.instruction, "movl")
|
||||
self.assertEqual(parsed_3.mnemonic, "movl")
|
||||
self.assertEqual(parsed_3.operands[0].value, 222)
|
||||
self.assertEqual(parsed_3.operands[1].name, "ebx")
|
||||
self.assertEqual(parsed_3.comment, "IACA END")
|
||||
|
||||
self.assertEqual(parsed_4.instruction, "vmovss")
|
||||
self.assertEqual(parsed_4.mnemonic, "vmovss")
|
||||
self.assertEqual(parsed_4.operands[1].offset.value, -4)
|
||||
self.assertEqual(parsed_4.operands[1].base.name, "rsp")
|
||||
self.assertEqual(parsed_4.operands[1].index.name, "rax")
|
||||
@@ -141,14 +141,14 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
self.assertEqual(parsed_4.operands[0].name, "xmm4")
|
||||
self.assertEqual(parsed_4.comment, "12.9")
|
||||
|
||||
self.assertEqual(parsed_5.instruction, "mov")
|
||||
self.assertEqual(parsed_5.mnemonic, "mov")
|
||||
self.assertEqual(parsed_5.operands[1].offset.name, "var")
|
||||
self.assertIsNone(parsed_5.operands[1].base)
|
||||
self.assertIsNone(parsed_5.operands[1].index)
|
||||
self.assertEqual(parsed_5.operands[1].scale, 1)
|
||||
self.assertEqual(parsed_5.operands[0].name, "ebx")
|
||||
|
||||
self.assertEqual(parsed_6.instruction, "lea")
|
||||
self.assertEqual(parsed_6.mnemonic, "lea")
|
||||
self.assertIsNone(parsed_6.operands[0].offset)
|
||||
self.assertIsNone(parsed_6.operands[0].base)
|
||||
self.assertEqual(parsed_6.operands[0].index.name, "rax")
|
||||
@@ -166,8 +166,8 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
line_directive = ".quad .2.3_2__kmpc_loc_pack.2 #qed"
|
||||
line_instruction = "lea 2(%rax,%rax), %ecx #12.9"
|
||||
|
||||
instruction_form_1 = instructionForm(
|
||||
instruction_id=None,
|
||||
instruction_form_1 = InstructionForm(
|
||||
mnemonic=None,
|
||||
operands_id=[],
|
||||
directive_id=None,
|
||||
comment_id="-- Begin main",
|
||||
@@ -175,8 +175,8 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
line="# -- Begin main",
|
||||
line_number=1,
|
||||
)
|
||||
instruction_form_2 = instructionForm(
|
||||
instruction_id=None,
|
||||
instruction_form_2 = InstructionForm(
|
||||
mnemonic=None,
|
||||
operands_id=[],
|
||||
directive_id=None,
|
||||
comment_id="Preds ..B1.6",
|
||||
@@ -184,8 +184,8 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
line="..B1.7: # Preds ..B1.6",
|
||||
line_number=2,
|
||||
)
|
||||
instruction_form_3 = instructionForm(
|
||||
instruction_id=None,
|
||||
instruction_form_3 = InstructionForm(
|
||||
mnemonic=None,
|
||||
operands_id=[],
|
||||
directive_id={"name": "quad", "parameters": [".2.3_2__kmpc_loc_pack.2"]},
|
||||
comment_id="qed",
|
||||
@@ -193,8 +193,8 @@ class TestParserX86ATT(unittest.TestCase):
|
||||
line=".quad .2.3_2__kmpc_loc_pack.2 #qed",
|
||||
line_number=3,
|
||||
)
|
||||
instruction_form_4 = instructionForm(
|
||||
instruction_id="lea",
|
||||
instruction_form_4 = InstructionForm(
|
||||
mnemonic="lea",
|
||||
operands_id=[
|
||||
{
|
||||
"memory": {
|
||||
|
||||
Reference in New Issue
Block a user