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https://github.com/RRZE-HPC/OSACA.git
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Parser for RISCV is implemented and tested with a
simple kernel. Changes to be committed: modified: osaca/parser/__init__.py new file: osaca/parser/parser_RISCV.py new file: tests/test_files/kernel_riscv.s new file: tests/test_parser_RISCV.py
This commit is contained in:
Metehan Dundar
321
tests/test_parser_RISCV.py
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321
tests/test_parser_RISCV.py
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#!/usr/bin/env python3
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"""
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Unit tests for RISC-V assembly parser
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"""
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import os
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import unittest
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from pyparsing import ParseException
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from osaca.parser import ParserRISCV, InstructionForm
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from osaca.parser.directive import DirectiveOperand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.identifier import IdentifierOperand
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class TestParserRISCV(unittest.TestCase):
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@classmethod
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def setUpClass(self):
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self.parser = ParserRISCV()
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with open(self._find_file("kernel_riscv.s")) as f:
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self.riscv_code = f.read()
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##################
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# Test
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##################
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def test_comment_parser(self):
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self.assertEqual(self._get_comment(self.parser, "# some comments"), "some comments")
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self.assertEqual(
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self._get_comment(self.parser, "\t\t# RISC-V comment \t end \t"), "RISC-V comment end"
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)
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self.assertEqual(
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self._get_comment(self.parser, "\t## comment ## comment"),
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"# comment ## comment",
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)
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def test_label_parser(self):
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self.assertEqual(self._get_label(self.parser, "main:")[0].name, "main")
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self.assertEqual(self._get_label(self.parser, "loop_start:")[0].name, "loop_start")
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self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t# comment")[0].name, ".L1")
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self.assertEqual(
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" ".join(self._get_label(self.parser, ".L1:\t\t\t# comment")[1]),
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"comment",
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)
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with self.assertRaises(ParseException):
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self._get_label(self.parser, "\t.cfi_startproc")
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def test_directive_parser(self):
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self.assertEqual(self._get_directive(self.parser, "\t.text")[0].name, "text")
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self.assertEqual(len(self._get_directive(self.parser, "\t.text")[0].parameters), 0)
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self.assertEqual(self._get_directive(self.parser, "\t.align\t4")[0].name, "align")
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self.assertEqual(
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len(self._get_directive(self.parser, "\t.align\t4")[0].parameters), 1
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)
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self.assertEqual(
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self._get_directive(self.parser, "\t.align\t4")[0].parameters[0], "4"
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)
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self.assertEqual(
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self._get_directive(self.parser, " .byte 100,103,144 # IACA START")[
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0
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].name,
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"byte",
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)
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self.assertEqual(
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self._get_directive(self.parser, " .byte 100,103,144 # IACA START")[
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0
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].parameters[2],
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"144",
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)
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self.assertEqual(
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" ".join(
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self._get_directive(self.parser, " .byte 100,103,144 # IACA START")[1]
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),
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"IACA START",
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)
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def test_parse_instruction(self):
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instr1 = "addi t0, zero, 1"
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instr2 = "lw a0, 8(sp)"
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instr3 = "beq t0, t1, loop_start"
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instr4 = "lui a0, %hi(data)"
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instr5 = "sw ra, -4(sp)"
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instr6 = "jal ra, function"
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parsed_1 = self.parser.parse_instruction(instr1)
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parsed_2 = self.parser.parse_instruction(instr2)
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parsed_3 = self.parser.parse_instruction(instr3)
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parsed_4 = self.parser.parse_instruction(instr4)
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parsed_5 = self.parser.parse_instruction(instr5)
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parsed_6 = self.parser.parse_instruction(instr6)
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# Verify addi instruction
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self.assertEqual(parsed_1.mnemonic, "addi")
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self.assertEqual(parsed_1.operands[0].name, "t0")
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self.assertEqual(parsed_1.operands[1].name, "zero")
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self.assertEqual(parsed_1.operands[2].value, 1)
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# Verify lw instruction
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self.assertEqual(parsed_2.mnemonic, "lw")
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self.assertEqual(parsed_2.operands[0].name, "a0")
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self.assertEqual(parsed_2.operands[1].offset.value, 8)
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self.assertEqual(parsed_2.operands[1].base.name, "sp")
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# Verify beq instruction
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self.assertEqual(parsed_3.mnemonic, "beq")
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self.assertEqual(parsed_3.operands[0].name, "t0")
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self.assertEqual(parsed_3.operands[1].name, "t1")
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self.assertEqual(parsed_3.operands[2].name, "loop_start")
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# Verify lui instruction with high bits relocation
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self.assertEqual(parsed_4.mnemonic, "lui")
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self.assertEqual(parsed_4.operands[0].name, "a0")
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self.assertEqual(parsed_4.operands[1].name, "data")
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# Verify sw instruction with negative offset
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self.assertEqual(parsed_5.mnemonic, "sw")
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self.assertEqual(parsed_5.operands[0].name, "ra")
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self.assertEqual(parsed_5.operands[1].offset.value, -4)
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self.assertEqual(parsed_5.operands[1].base.name, "sp")
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# Verify jal instruction
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self.assertEqual(parsed_6.mnemonic, "jal")
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self.assertEqual(parsed_6.operands[0].name, "ra")
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self.assertEqual(parsed_6.operands[1].name, "function")
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def test_parse_line(self):
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line_comment = "# -- Begin main"
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line_label = ".LBB0_1: # Loop Header"
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line_directive = ".cfi_def_cfa sp, 0"
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line_instruction = "addi sp, sp, -16 # allocate stack frame"
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instruction_form_1 = InstructionForm(
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mnemonic=None,
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operands=[],
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directive_id=None,
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comment_id="-- Begin main",
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label_id=None,
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line="# -- Begin main",
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line_number=1,
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)
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instruction_form_2 = InstructionForm(
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mnemonic=None,
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operands=[],
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directive_id=None,
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comment_id="Loop Header",
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label_id=".LBB0_1",
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line=".LBB0_1: # Loop Header",
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line_number=2,
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)
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instruction_form_3 = InstructionForm(
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mnemonic=None,
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operands=[],
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directive_id=DirectiveOperand(name="cfi_def_cfa", parameters=["sp", "0"]),
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comment_id=None,
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label_id=None,
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line=".cfi_def_cfa sp, 0",
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line_number=3,
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)
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instruction_form_4 = InstructionForm(
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mnemonic="addi",
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operands=[
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RegisterOperand(prefix="x", name="sp"),
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RegisterOperand(prefix="x", name="sp"),
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ImmediateOperand(value=-16, imd_type="int"),
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],
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directive_id=None,
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comment_id="allocate stack frame",
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label_id=None,
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line="addi sp, sp, -16 # allocate stack frame",
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line_number=4,
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)
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parsed_1 = self.parser.parse_line(line_comment, 1)
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parsed_2 = self.parser.parse_line(line_label, 2)
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parsed_3 = self.parser.parse_line(line_directive, 3)
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parsed_4 = self.parser.parse_line(line_instruction, 4)
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self.assertEqual(parsed_1.comment, instruction_form_1.comment)
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self.assertEqual(parsed_2.label, instruction_form_2.label)
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self.assertEqual(parsed_3.directive.name, instruction_form_3.directive.name)
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self.assertEqual(parsed_3.directive.parameters, instruction_form_3.directive.parameters)
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self.assertEqual(parsed_4.mnemonic, instruction_form_4.mnemonic)
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self.assertEqual(parsed_4.operands[0].name, instruction_form_4.operands[0].name)
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self.assertEqual(parsed_4.operands[2].value, instruction_form_4.operands[2].value)
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self.assertEqual(parsed_4.comment, instruction_form_4.comment)
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def test_parse_file(self):
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parsed = self.parser.parse_file(self.riscv_code)
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self.assertEqual(parsed[0].line_number, 1)
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self.assertGreater(len(parsed), 80) # More than 80 lines should be parsed
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# Test parsing specific parts of the file
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# Find vector_add label
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vector_add_idx = next((i for i, instr in enumerate(parsed) if instr.label == "vector_add"), None)
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self.assertIsNotNone(vector_add_idx)
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# Find floating-point instructions
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flw_idx = next((i for i, instr in enumerate(parsed) if instr.mnemonic == "flw"), None)
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self.assertIsNotNone(flw_idx)
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# Find vector instructions
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vle_idx = next((i for i, instr in enumerate(parsed) if instr.mnemonic and instr.mnemonic.startswith("vle")), None)
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self.assertIsNotNone(vle_idx)
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# Find CSR instructions
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csr_idx = next((i for i, instr in enumerate(parsed) if instr.mnemonic == "csrr"), None)
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self.assertIsNotNone(csr_idx)
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def test_register_mapping(self):
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# Test ABI name to register number mapping
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reg_zero = RegisterOperand(name="zero")
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reg_ra = RegisterOperand(name="ra")
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reg_sp = RegisterOperand(name="sp")
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reg_a0 = RegisterOperand(name="a0")
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reg_t1 = RegisterOperand(name="t1")
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reg_s2 = RegisterOperand(name="s2")
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reg_x0 = RegisterOperand(prefix="x", name="0")
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reg_x1 = RegisterOperand(prefix="x", name="1")
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reg_x2 = RegisterOperand(prefix="x", name="2")
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reg_x10 = RegisterOperand(prefix="x", name="10")
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reg_x6 = RegisterOperand(prefix="x", name="6")
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reg_x18 = RegisterOperand(prefix="x", name="18")
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# Test canonical name conversion
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self.assertEqual(self.parser._get_canonical_reg_name(reg_zero), "x0")
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self.assertEqual(self.parser._get_canonical_reg_name(reg_ra), "x1")
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self.assertEqual(self.parser._get_canonical_reg_name(reg_sp), "x2")
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self.assertEqual(self.parser._get_canonical_reg_name(reg_a0), "x10")
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self.assertEqual(self.parser._get_canonical_reg_name(reg_t1), "x6")
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self.assertEqual(self.parser._get_canonical_reg_name(reg_s2), "x18")
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# Test register dependency
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self.assertTrue(self.parser.is_reg_dependend_of(reg_zero, reg_x0))
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self.assertTrue(self.parser.is_reg_dependend_of(reg_ra, reg_x1))
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self.assertTrue(self.parser.is_reg_dependend_of(reg_sp, reg_x2))
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self.assertTrue(self.parser.is_reg_dependend_of(reg_a0, reg_x10))
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self.assertTrue(self.parser.is_reg_dependend_of(reg_t1, reg_x6))
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self.assertTrue(self.parser.is_reg_dependend_of(reg_s2, reg_x18))
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# Test non-dependent registers
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self.assertFalse(self.parser.is_reg_dependend_of(reg_zero, reg_x1))
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self.assertFalse(self.parser.is_reg_dependend_of(reg_ra, reg_x2))
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self.assertFalse(self.parser.is_reg_dependend_of(reg_a0, reg_t1))
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def test_normalize_imd(self):
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imd_decimal = ImmediateOperand(value="42")
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imd_hex = ImmediateOperand(value="0x2A")
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imd_negative = ImmediateOperand(value="-12")
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identifier = IdentifierOperand(name="function")
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self.assertEqual(self.parser.normalize_imd(imd_decimal), 42)
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self.assertEqual(self.parser.normalize_imd(imd_hex), 42)
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self.assertEqual(self.parser.normalize_imd(imd_negative), -12)
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self.assertEqual(self.parser.normalize_imd(identifier), identifier)
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def test_is_gpr(self):
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# Test integer registers
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reg_x5 = RegisterOperand(prefix="x", name="5")
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reg_t0 = RegisterOperand(name="t0")
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reg_sp = RegisterOperand(name="sp")
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# Test floating point registers
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reg_f10 = RegisterOperand(prefix="f", name="10")
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reg_fa0 = RegisterOperand(name="fa0")
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# Test vector registers
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reg_v3 = RegisterOperand(prefix="v", name="3")
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self.assertTrue(self.parser.is_gpr(reg_x5))
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self.assertTrue(self.parser.is_gpr(reg_t0))
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self.assertTrue(self.parser.is_gpr(reg_sp))
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self.assertFalse(self.parser.is_gpr(reg_f10))
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self.assertFalse(self.parser.is_gpr(reg_fa0))
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self.assertFalse(self.parser.is_gpr(reg_v3))
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def test_is_vector_register(self):
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reg_v3 = RegisterOperand(prefix="v", name="3")
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reg_x5 = RegisterOperand(prefix="x", name="5")
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reg_f10 = RegisterOperand(prefix="f", name="10")
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self.assertTrue(self.parser.is_vector_register(reg_v3))
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self.assertFalse(self.parser.is_vector_register(reg_x5))
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self.assertFalse(self.parser.is_vector_register(reg_f10))
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##################
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# Helper functions
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##################
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def _get_comment(self, parser, comment):
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return " ".join(
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parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())[
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"comment"
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]
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)
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def _get_label(self, parser, label):
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return parser.process_operand(parser.label.parseString(label, parseAll=True).asDict())
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def _get_directive(self, parser, directive):
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return parser.process_operand(
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parser.directive.parseString(directive, parseAll=True).asDict()
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)
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@staticmethod
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def _find_file(name):
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testdir = os.path.dirname(__file__)
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name = os.path.join(testdir, "test_files", name)
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assert os.path.exists(name)
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return name
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if __name__ == "__main__":
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suite = unittest.TestLoader().loadTestsFromTestCase(TestParserRISCV)
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unittest.TextTestRunner(verbosity=2).run(suite)
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