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https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 02:30:08 +01:00
Changes for operand matching, instruction loading
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@@ -94,7 +94,7 @@ class TestParserAArch64(unittest.TestCase):
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instr7 = "fadd v17.2d, v16.2d, v1.2d"
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instr8 = "mov.d x0, v16.d[1]"
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instr9 = "ccmp x0, x1, #4, cc"
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"""
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parsed_1 = self.parser.parse_instruction(instr1)
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parsed_2 = self.parser.parse_instruction(instr2)
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parsed_3 = self.parser.parse_instruction(instr3)
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@@ -125,8 +125,8 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_4.instruction, "str")
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self.assertIsNone(parsed_4.operands[1].offset)
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self.assertEqual(parsed_4.operands[1].base['name'], "sp")
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self.assertEqual(parsed_4.operands[1].base['prefix'], "x")
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self.assertEqual(parsed_4.operands[1].base.name, "sp")
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self.assertEqual(parsed_4.operands[1].base.prefix, "x")
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self.assertEqual(parsed_4.operands[1].index['name'], "1")
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self.assertEqual(parsed_4.operands[1].index['prefix'], "x")
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self.assertEqual(parsed_4.operands[1].scale, 16)
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@@ -139,8 +139,8 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_5.operands[0].prefix, "x")
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self.assertEqual(parsed_5.operands[1].offset['identifier']['name'], "q2c")
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self.assertEqual(parsed_5.operands[1].offset['identifier']['relocation'], ":got_lo12:")
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self.assertEqual(parsed_5.operands[1].base['name'], "0")
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self.assertEqual(parsed_5.operands[1].base['prefix'], "x")
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self.assertEqual(parsed_5.operands[1].base.name, "0")
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self.assertEqual(parsed_5.operands[1].base.prefix, "x")
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self.assertIsNone(parsed_5.operands[1].index)
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self.assertEqual(parsed_5.operands[1].scale, 1)
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@@ -169,7 +169,7 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_9.operands[0].name, "0")
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self.assertEqual(parsed_9.operands[0].prefix, "x")
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self.assertEqual(parsed_9.operands[3]['condition'], "CC")
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"""
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def test_parse_line(self):
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line_comment = "// -- Begin main"
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@@ -216,7 +216,7 @@ class TestParserAArch64(unittest.TestCase):
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RegisterOperand(PREFIX_ID="s", NAME_ID="0"),
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MemoryOperand(
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OFFSET_ID=None,
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BASE_ID={"prefix": "x", "name": "11"},
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BASE_ID=RegisterOperand(PREFIX_ID = "x", NAME_ID ="11"),
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INDEX_ID={
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"prefix": "w",
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"name": "10",
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@@ -239,7 +239,7 @@ class TestParserAArch64(unittest.TestCase):
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{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
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MemoryOperand(
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OFFSET_ID={"value": 2048},
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BASE_ID={"prefix": "x", "name": "26"},
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BASE_ID=RegisterOperand(PREFIX_ID = "x", NAME_ID ="26"),
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INDEX_ID=None,
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SCALE_ID=1,
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),
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@@ -257,7 +257,7 @@ class TestParserAArch64(unittest.TestCase):
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RegisterOperand(PREFIX_ID="x", NAME_ID="30"),
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MemoryOperand(
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OFFSET_ID={"value": -16},
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BASE_ID={"name": "sp", "prefix": "x"},
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BASE_ID=RegisterOperand(NAME_ID = "sp", PREFIX_ID = "x"),
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INDEX_ID=None,
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SCALE_ID=1,
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PRE_INDEXED=True,
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@@ -276,7 +276,7 @@ class TestParserAArch64(unittest.TestCase):
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RegisterOperand(PREFIX_ID="q", NAME_ID="3"),
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MemoryOperand(
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OFFSET_ID=None,
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BASE_ID={"prefix": "x", "name": "11"},
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BASE_ID=RegisterOperand(NAME_ID = "11", PREFIX_ID = "x"),
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INDEX_ID=None,
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SCALE_ID=1,
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POST_INDEXED={"value": 64},
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@@ -317,7 +317,7 @@ class TestParserAArch64(unittest.TestCase):
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LINE="ccmn x11, #1, #3, eq",
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LINE_NUMBER=9,
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)
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"""
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parsed_1 = self.parser.parse_line(line_comment, 1)
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parsed_2 = self.parser.parse_line(line_label, 2)
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parsed_3 = self.parser.parse_line(line_directive, 3)
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@@ -337,7 +337,7 @@ class TestParserAArch64(unittest.TestCase):
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self.assertEqual(parsed_7, instruction_form_7)
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self.assertEqual(parsed_8, instruction_form_8)
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self.assertEqual(parsed_9, instruction_form_9)
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"""
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def test_parse_file(self):
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parsed = self.parser.parse_file(self.triad_code)
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@@ -399,22 +399,22 @@ class TestParserAArch64(unittest.TestCase):
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# self.assertEqual(p_single.operands, reg_list_single)
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def test_reg_dependency(self):
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reg_1_1 = {"prefix": "b", "name": "1"}
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reg_1_2 = {"prefix": "h", "name": "1"}
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reg_1_3 = {"prefix": "s", "name": "1"}
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reg_1_4 = {"prefix": "d", "name": "1"}
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reg_1_4 = {"prefix": "q", "name": "1"}
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reg_2_1 = {"prefix": "w", "name": "2"}
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reg_2_2 = {"prefix": "x", "name": "2"}
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reg_v1_1 = {"prefix": "v", "name": "11", "lanes": "16", "shape": "b"}
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reg_v1_2 = {"prefix": "v", "name": "11", "lanes": "8", "shape": "h"}
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reg_v1_3 = {"prefix": "v", "name": "11", "lanes": "4", "shape": "s"}
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reg_v1_4 = {"prefix": "v", "name": "11", "lanes": "2", "shape": "d"}
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reg_1_1 = RegisterOperand(PREFIX_ID = "b", NAME_ID = "1")
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reg_1_2 = RegisterOperand(PREFIX_ID = "h", NAME_ID = "1")
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reg_1_3 = RegisterOperand(PREFIX_ID = "s", NAME_ID = "1")
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reg_1_4 = RegisterOperand(PREFIX_ID = "d", NAME_ID = "1")
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reg_1_4 = RegisterOperand(PREFIX_ID = "q", NAME_ID = "1")
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reg_2_1 = RegisterOperand(PREFIX_ID = "w", NAME_ID = "2")
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reg_2_2 = RegisterOperand(PREFIX_ID = "x", NAME_ID = "2")
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reg_v1_1 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "11", LANES = "16", SHAPE = "b")
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reg_v1_2 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "11", LANES = "8", SHAPE = "h")
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reg_v1_3 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "11", LANES = "4", SHAPE = "s")
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reg_v1_4 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "11", LANES = "2", SHAPE = "d")
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reg_b5 = {"prefix": "b", "name": "5"}
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reg_q15 = {"prefix": "q", "name": "15"}
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reg_v10 = {"prefix": "v", "name": "10", "lanes": "2", "shape": "s"}
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reg_v20 = {"prefix": "v", "name": "20", "lanes": "2", "shape": "d"}
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reg_b5 = RegisterOperand(PREFIX_ID = "b", NAME_ID = "5")
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reg_q15 = RegisterOperand(PREFIX_ID = "q", NAME_ID = "15")
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reg_v10 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "10", LANES = "2", SHAPE = "s")
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reg_v20 = RegisterOperand(PREFIX_ID = "v", NAME_ID = "20", LANES = "2", SHAPE = "d")
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reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
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reg_2 = [reg_2_1, reg_2_2]
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