From 841a4a5724a9deef00551644988c710dc1d5cd65 Mon Sep 17 00:00:00 2001
From: JanLJL <jan.laukemann@fau.de>
Date: Thu, 2 Mar 2023 15:50:13 +0100
Subject: [PATCH] resolve #81

---
 osaca/data/a64fx.yml       | 98 +++++++++++++++++++++++++++-----------
 osaca/data/isa/aarch64.yml | 49 ++++++++++++++++++-
 2 files changed, 117 insertions(+), 30 deletions(-)

diff --git a/osaca/data/a64fx.yml b/osaca/data/a64fx.yml
index 4560e84..150b592 100644
--- a/osaca/data/a64fx.yml
+++ b/osaca/data/a64fx.yml
@@ -734,7 +734,24 @@ instruction_forms:
   throughput: 43.0
   latency: 43.0  # 	1*p0+43*p0DV
   port_pressure: [[1, '0'], [43.0, [0DV]]]
-- name: [fmad, fmla]
+- name: [fmad, fmla, mla]
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  throughput: 0.5
+  latency: 9.0  # 	1*p02
+  port_pressure: [[1, '02']]
+- name: [fmad, fmla, mla, fmsb, fmls, mls]
   operands:
   - class: register
     prefix: z
@@ -754,7 +771,7 @@ instruction_forms:
   throughput: 0.5
   latency: 9.0  # 	1*p02
   port_pressure: [[1, '02']]
-- name: [fmad, fmla]
+- name: [fmad, fmla, fmsb, fmls]
   operands:
   - class: register
     prefix: z
@@ -776,36 +793,19 @@ instruction_forms:
   throughput: 0.5
   latency: 9.0  # 	1*p02
   port_pressure: [[1, '02']]
-- name: [fmla, fmls]
+- name: [fmla, fmls, mla, mls]
   operands:
   - class: register
     prefix: v
-    shape: s
+    shape: '*'
     width: '*'
   - class: register
     prefix: v
-    shape: s
+    shape: '*'
     width: '*'
   - class: register
     prefix: v
-    shape: s
-    width: '*'
-  throughput: 0.5
-  latency: 9.0  # 	1*p02
-  port_pressure: [[1, '02']]
-- name: [fmla, fmls]
-  operands:
-  - class: register
-    prefix: v
-    shape: d
-    width: '*'
-  - class: register
-    prefix: v
-    shape: d
-    width: '*'
-  - class: register
-    prefix: v
-    shape: d
+    shape: '*'
     width: '*'
   throughput: 0.5
   latency: 9.0  # 	1*p02
@@ -2546,8 +2546,50 @@ instruction_forms:
   throughput: 1.0
   latency: 6.0
   port_pressure: [[1, '2']]
-
-
-
-
-
+- name: [sadalp, uadalp]
+  operands:
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  throughput: 3.0
+  latency: 14.0
+  port_pressure: [[3, '2']]
+- name: [smlal, smlal2]
+  operands:
+  - class: register
+    prefix: v
+    shape: s
+    width: '*'
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  throughput: 8.0
+  latency: 18.0
+  port_pressure: {0: [[8, '0']], 1: [[8, '2']]}
+- name: [smlal, smlal2]
+  operands:
+  - class: register
+    prefix: v
+    shape: d
+    width: '*'
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  - class: register
+    prefix: v
+    shape: '*'
+    width: '*'
+  throughput: 3.0
+  latency: 15.0
+  port_pressure: {0: [[3, '0']], 1: [[3, '2']]}
diff --git a/osaca/data/isa/aarch64.yml b/osaca/data/isa/aarch64.yml
index 85246ea..0651747 100644
--- a/osaca/data/isa/aarch64.yml
+++ b/osaca/data/isa/aarch64.yml
@@ -62,7 +62,7 @@ instruction_forms:
         imd: int
         source: false 
         destination: false
-    - name: fmla
+    - name: [fmla, fmad, mla, fmls, fmsb, mls]
       operands:
       - class: register
         prefix: "*"
@@ -84,7 +84,7 @@ instruction_forms:
         shape: "*"
         source: true
         destination: false
-    - name: fmla
+    - name: [fmla, mla, fmls, mls, smlal, smlal2, smlalb, smlalt, smlsl, smlsl2, smlslb, smlslt, umlal, umlal2, umlalb, umlalt, umlsl, umlsl2, umlslb, umlslt] 
       operands:
         - class: register
           prefix: "*"
@@ -101,6 +101,51 @@ instruction_forms:
           shape: "*"
           source: true
           destination: false
+    - name: [sadalp, uadalp]
+      operands:
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: true
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: false
+    - name: [sadalp, uadalp, sabal, sabal2, sabalb, sabalt]
+      operands:
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: true
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: false
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: false
+    - name: [ssra, srsra, usra, ursra]
+      operands:
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: true
+        - class: register
+          prefix: "*"
+          shape: "*"
+          source: true
+          destination: false
+        - class: immediate
+          imd: "int"
+          source: true
+          destination: false
     - name: ldp
       operands:
         - class: register