diff --git a/tests/test_files/test_db_aarch64.yml b/tests/test_files/test_db_aarch64.yml new file mode 100644 index 0000000..5378602 --- /dev/null +++ b/tests/test_files/test_db_aarch64.yml @@ -0,0 +1,714 @@ +osaca_version: 0.3.2.dev5 +micro_architecture: Thunder X2 +arch_code: tx2 +isa: AArch64 +ROB_size: 180 +retired_uOps_per_cycle: 4 +scheduler_size: 60 +hidden_loads: false +load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} +load_throughput: +- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +load_throughput_default: [[1, '34']] +store_throughput: +- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[2, '34'], [2, '5']]} +store_throughput_default: [[1, '34'], [1, '5']] +ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5'] +port_model_scheme: | + +-----------------------------------------------------------+ + | 60 entry unified scheduler | + +-----------------------------------------------------------+ + 0 | 1 | 2 | 3 | 4 | 5 | + \/ \/ \/ \/ \/ \/ + +------+ +------+ +------+ +------+ +------+ +------+ + | ALU | | ALU | | ALU/ | | LD | | LD | | ST | + +------+ +------+ | BR | +------+ +------+ +------+ + +------+ +------+ +------+ +------+ +------+ + | FP/ | | FP/ | | AGU | | AGU | + | NEON | | NEON | +------+ +------+ + +------+ +------+ + +------+ + | INT | + | MUL/ | + | DIV | + +------+ + +------+ + |CRYPTO| + +------+ +instruction_forms: +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: b.ne + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: b.gt + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: bne + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: cmp + operands: + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: cmp + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 5.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 8.5 + latency: 16.0 # 1*p01+17*p0DV1DV + port_pressure: [[1, '01'], [17.0, [0DV, 1DV]]] +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 12.0 + latency: 23.0 # 1*p01+24*p0DV1DV + port_pressure: [[1, '01'], [24.0, [0DV, 1DV]]] +- name: fmla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fmla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fmov + operands: + - {class: register, prefix: s} + - {class: immediate, imd: double} + latency: ~ # 1*p01 + port_pressure: [[1, '01']] + throughput: 0.5 +- name: fmul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 6.0 # 1*p01 + port_pressure: [[1, '01']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34'], [1, '012']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34'], [1, '012']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34']] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34'], [1, '012']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 4.0 # 2*p34 + port_pressure: [[2.0, '34'], [1, '012']] +- name: ldur # JL: assumed from ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p34 + port_pressure: [[1.0, '34']] +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p34 + port_pressure: [[1.0, '34']] +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p34 + port_pressure: [[1.0, '34']] +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p34 + port_pressure: [[1.0, '34']] +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p34 + port_pressure: [[1.0, '34']] +- name: ldr + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: ldr + operands: + - class: register + prefix: q + - class: register + prefix: q + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: ldr + operands: + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 1.0 # 1*p01 + port_pressure: [[1, '01']] +- name: mov + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + throughput: 0.5 + latency: 5.0 # 1*p01 + port_pressure: [[1, '01']] +- name: prfm + operands: + - class: prfop + type: pld + target: l1 + policy: keep + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + throughput: ~ + latency: ~ + port_pressure: [] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 2.0 + latency: 0 # 2*p34+2*p5 + port_pressure: [[2.0, '34'], [2.0, '5']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 2.0 + latency: 0 # 2*p34+2*p5+1*012 + port_pressure: [[2.0, '34'], [2.0, '5'], [1, '012']] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 2.0 + latency: 0 # 2*p34+2*p5 + port_pressure: [[2.0, '34'], [2.0, '5']] +- name: stur # JL: assumed from str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 4.0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5']] +- name: stur # JL: assumed from str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 4.0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5']] +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5']] +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5']] +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: 1 + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5']] +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0 # 1*p34+1*p5 + port_pressure: [[1.0, '34'], [1.0, '5'], [1, '012']] +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] diff --git a/tests/test_files/test_db_x86.yml b/tests/test_files/test_db_x86.yml new file mode 100644 index 0000000..5e1ffc9 --- /dev/null +++ b/tests/test_files/test_db_x86.yml @@ -0,0 +1,7286 @@ +osaca_version: 0.3.2.dev5 +micro_architecture: Cascade Lake SP +arch_code: CSX +isa: x86 +ROB_size: 224 +retired_uOps_per_cycle: 4 +scheduler_size: 97 +hidden_loads: false +load_latency: {gpr: 4.0, mm: 4.0, xmm: 4.0, ymm: 4.0, zmm: 4.0} +load_throughput: + - {base: gpr, offset: ~, index: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: gpr, offset: ~, index: gpr, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: gpr, offset: ~, index: gpr, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: gpr, offset: imd, index: gpr, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: gpr, offset: imd, index: gpr, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: gpr, offset: imd, index: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: ~, offset: imd, index: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: ~, offset: ~, index: gpr, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: ~, offset: ~, index: gpr, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: ~, offset: imd, index: gpr, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} + - {base: ~, offset: imd, index: gpr, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] +store_throughput: +- {base: '*', offset: '*', index: ~, scale: '*', port_pressure: [[2, '237'], [2, '4']]} +- {base: '*', offset: '*', index: gpr, scale: '*', port_pressure: [[1, '23'], [1, '4']]} +store_throughput_default: [[1, '23'], [1, '4']] +ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] +port_model_scheme: | + +------------------------------------------------------------------------+ + | 97 entry unified scheduler | + +------------------------------------------------------------------------+ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + \/ \/ \/ \/ \/ \/ \/ \/ + +-------+ +-------+ +-----+ +-----+ +-----+ +-------+ +--------+ +-----+ + | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU & | | AGU | + +-------+ +-------+ +-----+ +-----+ +-----+ +-------+ | Shift | +-----+ + +-------+ +-------+ +-----+ +-----+ +-------+ +--------+ + | 2ND | | Fast | | AGU | | AGU | | Fast | +--------+ + | BRANCH| | LEA | +-----+ +-----+ | LEA | | BRANCH | + +-------+ +-------+ +-------+ +--------+ + +-------+ +-------+ +-------+ + |AVX DIV| |AVX FMA| | AVX | + +-------+ +-------+ | SHUF | + +-------+ +-------+ +-------+ + |AVX FMA| |AVX MUL| +-------+ + +-------+ +-------+ |AVX-512| + +-------+ +-------+ | FMA | + |AVX MUL| |AVX ADD| +-------+ + +-------+ +-------+ +-------+ + +-------+ +-------+ |AVX-512| + |AVX ADD| |AVX ALU| | ADD | + +-------+ +-------+ +-------+ + +-------+ +-------+ +-------+ + |AVX ALU| | AVX | |AVX-512| + +-------+ | Shift | | MUL | + +-------+ +-------+ +-------+ + | AVX | +-------+ +-------+ + | Shift | | Slow | |AVX-512| + +-------+ | LEA | | ALU | + +-------+ +-------+ +-------+ + | VNNI | +-------+ + +-------+ | VNNI | + +-------+ +instruction_forms: +- name: LEA + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 1.0 # JH: measured on casclakesp2 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: LEA + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: "*" + - class: register + name: gpr + latency: 1.0 # JH: measured on casclakesp2 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: LEA + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: "*" + - class: register + name: gpr + latency: 3.0 # JH: measured on casclakesp2 + port_pressure: [[1, '1']] # according to uops.info from SKX + throughput: 1.0 # JH: measured on casclakesp2 + uops: 1 +- name: LEA + operands: + - class: memory + base: gpr + offset: imd + index: ~ + scale: 1 + - class: register + name: gpr + latency: 1.0 # JH: measured on casclakesp2 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: LEA + operands: + - class: memory + base: ~ + offset: imd + index: ~ + scale: 1 + - class: register + name: gpr + latency: 1.0 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 + uops: 1 +- name: LEA + operands: + - class: memory + base: ~ + offset: ~ + index: gpr + scale: "*" + - class: register + name: gpr + latency: 1.0 # JH: measured on casclakesp2 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: LEA + operands: + - class: memory + base: ~ + offset: imd + index: gpr + scale: "*" + - class: register + name: gpr + latency: 1.0 # JH: measured on casclakesp2 + port_pressure: [[1, '15']] # according to uops.info from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: could not measure; according to uops.info SKX + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] # JH: assumed from SKX + throughput: 0.5 # JH: could not measure; according to uops.info SKX + uops: 2 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] # JH: assumed from SKX + throughput: 1.0 # JH: measured on casclakesp2 + uops: 1 +- name: BLSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] # JH: assumed from SKX + throughput: 1.0 # JH: measured on casclakesp2 + uops: 1 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] # JH: assumedfrom SKX + throughput: 0.3333333333333333 # JH: measured on casclakesp2 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] # JH: assumedfrom SKX + throughput: 0.3333333333333333 # JH: measured on casclakesp2 + uops: 1 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] # JH: assumed from SKX + throughput: 0.3333333333333333 # JH: measured on casclakesp2 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] # JH: assumed from SKX + throughput: 0.3333333333333333 # JH: measured on casclakesp2 + uops: 1 +- name: AND # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] # JH: assumed from SKX + throughput: 0.25 # JH: measured on casclakesp2 + uops: 1 +- name: AND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] # JH: assumed from SKX + throughput: 0.25 # JH: measured on casclakesp2 + uops: 1 +- name: ANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: ADC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: ADC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] # JH: assumed from SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: addsd + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: addss + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: add + operands: + - class: immediate + imd: int + - class: register + name: gpr + throughput: 0.25 + latency: 1.0 # 1"*"p0156 + port_pressure: [[1, '0156']] +- name: add + operands: + - class: register + name: gpr + - class: register + name: gpr + throughput: 0.25 + latency: 1.0 # 1"*"p0156 + port_pressure: [[1, '0156']] +- name: addpd # JH: copied from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] # uops.info (measured) + throughput: 0.5 + uops: 1 +- name: addps # JH: measured + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] # uops.info (measured) + throughput: 0.5 + uops: 1 +- name: cmp + operands: + - class: register + name: gpr + - class: register + name: gpr + throughput: 0.25 + latency: 1.0 + port_pressure: [[1, '0156']] +- name: cmp + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: cmppd + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpeqpd # same as CMPPD xmm1, xmm2, 0 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpltpd # same as CMPPD xmm1, xmm2, 1 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmplepd # same as CMPPD xmm1, xmm2, 2 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpunordpd # same as CMPPD xmm1, xmm2, 3 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpneqpd # same as CMPPD xmm1, xmm2, 4 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpnltpd # same as CMPPD xmm1, xmm2, 5 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpnlepd # same as CMPPD xmm1, xmm2, 6 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpordpd # same as CMPPD xmm1, xmm2, 7 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpps + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpeqps # same as CMPPS xmm1, xmm2, 0 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpltps # same as CMPPS xmm1, xmm2, 1 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpleps # same as CMPPS xmm1, xmm2, 2 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpunordps # same as CMPPS xmm1, xmm2, 3 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpneqps # same as CMPPS xmm1, xmm2, 4 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpnltps # same as CMPPS xmm1, xmm2, 5 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpnleps # same as CMPPS xmm1, xmm2, 6 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: cmpordps # same as CMPPS xmm1, xmm2, 7 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4.0 # JH: measured on casclakesp2 + port_pressure: [[1, '01']] # JH: according to uops.info SKX + throughput: 0.5 # JH: measured on casclakesp2 + uops: 1 +- name: inc + operands: + - class: register + name: gpr + throughput: 0.25 + latency: 1.0 # 1"*"p0156 + port_pressure: [[1, '0156']] +- name: [jo, jno, js, jns, jp, jpe, jnp, jpo] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jc, hb, jae, jnb, jna, jbe, ja, jnbe] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [je, jz, jne, jnz, jl, jnge] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jge, jnl, jle, jng, jg, jnle] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: mulsd + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: mulss + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: PUNPCKLWD + operands: + - class: register + name: mm + - class: register + name: mm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: immediate + imd: int + latency: 5 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHF + operands: [] + latency: 7 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: RORX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SARX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHLX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHRX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: sqrtsd + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 6.0 + latency: 22.0 # 1"*"p0+6"*"p0DV + port_pressure: [[1, '0'], [6.0, [0DV]]] +- name: sqrtss + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 3.0 + latency: 16.0 # 1"*"p0+3"*"p0DV + port_pressure: [[1, '0'], [3.0, [0DV]]] +- name: subq + operands: + - class: immediate + imd: int + - class: register + name: gpr + throughput: 0.25 + latency: 1.0 # 1"*"p0156 + port_pressure: [[1, '0156']] +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: vaddpd + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '05']] +- name: vaddpd + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vaddpd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vaddsd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vaddss + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: vcvtsi2ss + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '015'], [2, '5']] + throughput: 1.0 + uops: 1 +- name: vcvtss2sd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 1.0 + uops: 1 +- name: VCVTTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: vdivsd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 4.0 + latency: 14.0 # 1"*"p0+4"*"p0DV + port_pressure: [[1, '0'], [4.0, [0DV]]] +- name: vdivss + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 3.0 + latency: 11.0 # 1"*"p0+3"*"p0DV + port_pressure: [[1, '0'], [3.0, [0DV]]] +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 15 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 24 + port_pressure: [[2, '0'], [1, '05'], [16, [0DV]]] + throughput: 16.0 + uops: 3 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 18 + port_pressure: [[2, '0'], [1, '05'], [10, [0DV]]] + throughput: 10.0 + uops: 3 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VFMADDSUB231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VHADDPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHADDPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VINSERTI128 # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTPS # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXSD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXSS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: vmulsd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vmulss + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: mulpd + operands: + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vmulpd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vmulpd + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '01']] +- name: vmulpd + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + throughput: 0.5 + latency: 4.0 # 1"*"p01 + port_pressure: [[1, '05']] +- name: VMULPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VORPD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VORPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDQ # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDQ # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPALIGNR # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPANDN # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDN # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDNQ # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDNQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDNQ # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBROADCASTB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB # JH: assumed from SKX + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW # JH: assumed from SKX + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD # JH: assumed from SKX + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ # JH: assumed from SKX + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERM2F128 # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPEXTRD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPINSRQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMAXSD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSB # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSB # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSW # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPOR # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPOR # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORD # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORQ # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORQ # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORQ # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSHUFB # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB # JH: assumed from SKX + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vpsrld # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1 +- name: VPSRLDQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLD # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPXOR # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXOR # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VRCPPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VROUNDPS # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VROUNDPS # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRSQRTPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS # JH: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSTMXCSR # JH: assumed from SKX + operands: + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 11 + port_pressure: [[1, '0'], [1, '06'], [1, '237'], [1, '4']] + throughput: 1 + uops: 4 +- name: VSTMXCSR # JH: assumed from SKX + operands: + - class: memory + base: "*" + offset: "*" + index: "gpr" + scale: "*" + latency: 11 + port_pressure: [[1, '0'], [1, '06'], [1, '23'], [1, '4']] + throughput: 1 + uops: 4 +- name: VSUBSS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBSD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBSS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBSD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSQRTSS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VUCOMISS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD # JL: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF64X2 # JL: assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPS # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPS # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 +- name: VXORPD # JH: assumed from SKX + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPD # JH: assumed from SKX + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 +- name: VZEROUPPER # JH: assumed from SKX + operands: [] + latency: 1 + port_pressure: [[1, '015'], [3, '0156']] + throughput: 1.0 + uops: 4 +- name: wait + operands: [] + latency: 1 + port_pressure: [] + throughput: 1 + uops: 0 +- name: xadd + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[3, '0156']] + throughput: 0.75 + uops: 3 +- name: xor # assumed from SKX + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: xor # assumed from SKX + operands: + - class: register + imd: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: mov + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: mov # with store, simple AGU + operands: + - class: register + name: gpr + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov # with store, complex AGU + operands: + - class: register + name: gpr + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: mov # with store, simple AGU + operands: + - class: immediate + imd: int + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov # with store, complex AGU + operands: + - class: immediate + imd: int + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movapd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movd + operands: + - class: register + name: gpr + - class: register + name: mm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: mm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: mm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movq # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: mm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movd + operands: + - class: register + name: mm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movd # with store, simple AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movd # with store, complex AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: mm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movq # with store, simple AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq # with store, complex AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movd + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movq # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movd + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movq # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovd + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovq # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovd + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovq # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movddup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movddup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovddup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovddup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovddup + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovddup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movdq2q + operands: + - class: register + name: xmm + - class: register + name: mm + latency: 1 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movdqa # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovdqa # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovdqa # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqu # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movdqu # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovdqu # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovdqu # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movhlps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovhlps + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movhpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: vmovhpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movhpd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movhpd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovhpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movhps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: vmovhps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movhps # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movhps # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovhps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movlhps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovlhps + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movlpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: vmovlpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movlpd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movlpd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovlpd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movlps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: vmovlps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movlps # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movlps # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovlps # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5'], [1, '23'], [1, ['2D', '3D']]] + throughput: 1.0 + uops: 3 +- name: movmskpd + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovmskpd + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovmskpd + operands: + - class: register + name: ymm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movmskps + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovmskps + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: vmovmskps + operands: + - class: register + name: ymm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: movntdq # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntdq # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntdq # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntdq # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntdq # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntdq # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovntdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovntdqa # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movnti # with store, simple AGU + operands: + - class: register + name: gpr + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movnti # with store, complex AGU + operands: + - class: register + name: gpr + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntpd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntpd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntpd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntpd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntpd # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntpd # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntps # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntps # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntps # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntps # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntps # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovntps # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntq # with store, simple AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movntq # with store, complex AGU + operands: + - class: register + name: mm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: mm + - class: register + name: mm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: movq2dq + operands: + - class: register + name: mm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movsd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovsd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovsd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movshdup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movshdup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovshdup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovshdup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovshdup + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovshdup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsldup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movsldup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovsldup + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovsldup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovsldup + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovsldup # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: movss # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovss # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vmovss # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsx + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: movsx # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsxd + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movsxd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsb + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: movsb # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsw + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: movsw # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsl + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: movsl # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movsq + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: movsq # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movupd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movupd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovupd # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovupd # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovupd # with store, simple AGU + operands: + - class: register + name: zmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd # with store, complex AGU + operands: + - class: register + name: zmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movups # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: movups # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovups # with store, simple AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups # with store, complex AGU + operands: + - class: register + name: xmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 + +- name: vmovups + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 + +- name: vmovups # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 + +- name: vmovups # with store, simple AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 + +- name: vmovups # with store, complex AGU + operands: + - class: register + name: ymm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: zymm + - class: register + name: zmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups # with load + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '23'], [1, ['2D', '3D']]] + throughput: 0.5 + uops: 2 +- name: vmovups # with store, simple AGU + operands: + - class: register + name: zmm + - class: memory + base: "*" + offset: "*" + index: ~ + scale: "*" + latency: 0 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups # with store, complex AGU + operands: + - class: register + name: zmm + - class: memory + base: "*" + offset: "*" + index: gpr + scale: "*" + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 diff --git a/tests/test_semantics.py b/tests/test_semantics.py index a702979..368a791 100755 --- a/tests/test_semantics.py +++ b/tests/test_semantics.py @@ -11,8 +11,7 @@ from subprocess import call import networkx as nx from osaca.parser import AttrDict, ParserAArch64v81, ParserX86ATT -from osaca.semantics import (INSTR_FLAGS, KernelDG, MachineModel, - ArchSemantics) +from osaca.semantics import INSTR_FLAGS, ArchSemantics, KernelDG, MachineModel class TestSemanticTools(unittest.TestCase): @@ -71,6 +70,120 @@ class TestSemanticTools(unittest.TestCase): except ValueError: self.fail() + def test_machine_model_various_functions(self): + # check dummy MachineModel creation + try: + MachineModel(isa='x86') + MachineModel(isa='aarch64') + except ValueError: + self.fail() + test_mm_x86 = MachineModel(path_to_yaml=self._find_file('test_db_x86.yml')) + test_mm_arm = MachineModel(path_to_yaml=self._find_file('test_db_aarch64.yml')) + + # test get_instruction without mnemonic + self.assertIsNone(test_mm_x86.get_instruction(None, [])) + self.assertIsNone(test_mm_arm.get_instruction(None, [])) + + # test dict DB creation + test_mm_x86._data['instruction_dict'] = test_mm_x86._convert_to_dict( + test_mm_x86._data['instruction_forms'] + ) + test_mm_arm._data['instruction_dict'] = test_mm_arm._convert_to_dict( + test_mm_arm._data['instruction_forms'] + ) + # test get_instruction from dict DB + self.assertIsNone(test_mm_x86.get_instruction_from_dict(None, [])) + self.assertIsNone(test_mm_arm.get_instruction_from_dict(None, [])) + self.assertIsNone(test_mm_x86.get_instruction_from_dict('NOT_IN_DB', [])) + self.assertIsNone(test_mm_arm.get_instruction_from_dict('NOT_IN_DB', [])) + name_x86_1 = 'vaddpd' + operands_x86_1 = [ + {'class': 'register', 'name': 'xmm'}, + {'class': 'register', 'name': 'xmm'}, + {'class': 'register', 'name': 'xmm'}, + ] + instr_form_x86_1 = test_mm_x86.get_instruction_from_dict(name_x86_1, operands_x86_1) + self.assertEqual(instr_form_x86_1, test_mm_x86.get_instruction(name_x86_1, operands_x86_1)) + self.assertEqual( + test_mm_x86.get_instruction_from_dict('jg', [{'class': 'identifier'}]), + test_mm_x86.get_instruction('jg', [{'class': 'identifier'}]), + ) + name_arm_1 = 'fadd' + operands_arm_1 = [ + {'class': 'register', 'prefix': 'v', 'shape': 's'}, + {'class': 'register', 'prefix': 'v', 'shape': 's'}, + {'class': 'register', 'prefix': 'v', 'shape': 's'}, + ] + instr_form_arm_1 = test_mm_arm.get_instruction_from_dict(name_arm_1, operands_arm_1) + self.assertEqual(instr_form_arm_1, test_mm_arm.get_instruction(name_arm_1, operands_arm_1)) + self.assertEqual( + test_mm_arm.get_instruction_from_dict('b.ne', [{'class': 'identifier'}]), + test_mm_arm.get_instruction('b.ne', [{'class': 'identifier'}]), + ) + + # test full instruction name + self.assertEqual( + MachineModel.get_full_instruction_name(instr_form_x86_1), + 'vaddpd register(name:xmm),register(name:xmm),register(name:xmm)', + ) + self.assertEqual( + MachineModel.get_full_instruction_name(instr_form_arm_1), + 'fadd register(prefix:v,shape:s),register(prefix:v,shape:s),' + + 'register(prefix:v,shape:s)', + ) + + # test get_store_tp + self.assertEqual( + test_mm_x86.get_store_throughput( + {'base': 'x', 'offset': None, 'index': None, 'scale': 1} + ), + [[2, '237'], [2, '4']], + ) + self.assertEqual( + test_mm_x86.get_store_throughput( + {'base': 'NOT_IN_DB', 'offset': None, 'index': 'NOT_NONE', 'scale': 1} + ), + [[1, '23'], [1, '4']], + ) + self.assertEqual( + test_mm_arm.get_store_throughput( + {'base': {'prefix': 'x'}, 'offset': None, 'index': None, 'scale': 1} + ), + [[2, '34'], [2, '5']], + ) + self.assertEqual( + test_mm_arm.get_store_throughput( + {'base': {'prefix': 'NOT_IN_DB'}, 'offset': None, 'index': None, 'scale': 1} + ), + [[1, '34'], [1, '5']], + ) + + # test get_store_lt + self.assertEqual( + test_mm_x86.get_store_latency( + {'base': 'x', 'offset': None, 'index': None, 'scale': '1'} + ), + 0, + ) + self.assertEqual( + test_mm_arm.get_store_latency( + {'base': 'x', 'offset': None, 'index': None, 'scale': '1'} + ), + 0, + ) + + # test has_hidden_load + self.assertFalse(test_mm_x86.has_hidden_loads()) + + # test adding port + test_mm_x86.add_port('dummyPort') + test_mm_arm.add_port('dummyPort') + + # test dump of DB + with open('/dev/null', 'w') as dev_null: + test_mm_x86.dump(stream=dev_null) + test_mm_arm.dump(stream=dev_null) + def test_src_dst_assignment_x86(self): for instruction_form in self.kernel_x86: with self.subTest(instruction_form=instruction_form):