From 94cb3de6a121244c8f9e7e8f173fab3630fec76e Mon Sep 17 00:00:00 2001 From: JanLJL Date: Sat, 16 Aug 2025 14:08:43 +0200 Subject: [PATCH] fix bug to support 0x.. and ..R hex values for intel syntax --- osaca/parser/parser_x86intel.py | 11 ++++++++--- tests/test_parser_x86intel.py | 18 ++++++++++++++++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/osaca/parser/parser_x86intel.py b/osaca/parser/parser_x86intel.py index 8802b59..0540782 100644 --- a/osaca/parser/parser_x86intel.py +++ b/osaca/parser/parser_x86intel.py @@ -160,12 +160,15 @@ class ParserX86Intel(ParserX86): binary_number = pp.Combine(pp.Word("01") + pp.CaselessLiteral("B")) octal_number = pp.Combine(pp.Word("01234567") + pp.CaselessLiteral("O")) decimal_number = pp.Combine(pp.Optional(pp.Literal("-")) + pp.Word(pp.nums)) - hex_number = pp.Combine(pp.Word(pp.hexnums) + pp.CaselessLiteral("H")) + hex_number_suffix = pp.Combine(pp.Word(pp.hexnums) + (pp.CaselessLiteral("H") ^ pp.CaselessLiteral("R"))) + hex_number_0x = pp.Combine( + pp.Optional(pp.Literal("-")) + pp.Literal("0x") + pp.Word(pp.hexnums)) + hex_number = (hex_number_0x ^ hex_number_suffix) float_number = pp.Combine( pp.Optional(pp.Literal("-")) + pp.Word(pp.nums) + pp.Word(".", pp.nums) ).setResultsName("value") integer_number = ( - binary_number ^ octal_number ^ decimal_number ^ hex_number + hex_number ^ binary_number ^ octal_number ^ decimal_number ).setResultsName("value") # Comment. @@ -793,8 +796,10 @@ class ParserX86Intel(ParserX86): if isinstance(imd.value, str): if "." in imd.value: return float(imd.value) + if imd.value.startswith("0x"): + return int(imd.value, 0) # Now parse depending on the base. - base = {"B": 2, "O": 8, "H": 16}.get(imd.value[-1], 10) + base = {"B": 2, "O": 8, "H": 16, "R": 16}.get(imd.value[-1], 10) value = 0 negative = imd.value[0] == "-" positive = imd.value[0] == "+" diff --git a/tests/test_parser_x86intel.py b/tests/test_parser_x86intel.py index 1918810..e96803c 100755 --- a/tests/test_parser_x86intel.py +++ b/tests/test_parser_x86intel.py @@ -103,6 +103,8 @@ class TestParserX86Intel(unittest.TestCase): instr12 = "\tvfmadd213sd xmm0, xmm1, QWORD PTR __real@bfc5555555555555" instr13 = "\tjmp\t$LN18@operator" instr14 = "vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]" + instr15 = "vextractf128 xmm1, ymm2, 0x2" + instr16 = "vmovupd xmm0, [rax+123R]" parsed_1 = self.parser.parse_instruction(instr1) parsed_2 = self.parser.parse_instruction(instr2) @@ -118,6 +120,8 @@ class TestParserX86Intel(unittest.TestCase): parsed_12 = self.parser.parse_instruction(instr12) parsed_13 = self.parser.parse_instruction(instr13) parsed_14 = self.parser.parse_instruction(instr14) + parsed_15 = self.parser.parse_instruction(instr15) + parsed_16 = self.parser.parse_instruction(instr16) self.assertEqual(parsed_1.mnemonic, "sub") self.assertEqual(parsed_1.operands[0], RegisterOperand(name="RSP")) @@ -221,6 +225,20 @@ class TestParserX86Intel(unittest.TestCase): ), ) + self.assertEqual(parsed_15.mnemonic, "vextractf128") + self.assertEqual(parsed_15.operands[0], RegisterOperand(name="XMM1")) + self.assertEqual(parsed_15.operands[1], RegisterOperand(name="YMM2")) + self.assertEqual(parsed_15.operands[2], ImmediateOperand(value=2)) + + self.assertEqual(parsed_16.mnemonic, "vmovupd") + self.assertEqual(parsed_16.operands[0], RegisterOperand(name="XMM0")) + self.assertEqual( + parsed_16.operands[1], + MemoryOperand( + base=RegisterOperand(name="RAX"), offset=ImmediateOperand(value=291) + ), + ) + def test_parse_line(self): line_comment = "; -- Begin main" line_instruction = "\tret\t0"