From a111ce7e8940ffb65033e2c0064ece4b998bd70e Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 18:34:39 +0100 Subject: [PATCH] unfified STP and LDP instructions --- osaca/data/tsv110.yml | 454 +++++++++++++++++++++++++++++------------- 1 file changed, 312 insertions(+), 142 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 853a824..1309550 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -120,23 +120,6 @@ instruction_forms: port_pressure: ~ throughput: 0.33333 uops: ~ -- name: stp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsub operands: - class: register @@ -152,23 +135,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: ldp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fmul operands: - class: register @@ -181,23 +147,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: fdiv operands: - class: register @@ -339,23 +288,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: stp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsqrt operands: - class: register @@ -383,23 +315,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: stp - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: stur operands: - class: register @@ -457,23 +372,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: stp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: fadd operands: - class: register @@ -513,40 +411,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldp - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ -- name: ldp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: cmp operands: - class: register @@ -577,6 +441,312 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'] + uops: 2 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'] + uops: 2 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 - name: ldr operands: - class: register @@ -617,7 +787,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -662,7 +832,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -691,7 +861,7 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true + pre-indexed: true post-indexed: false throughput: 0.5 latency: 4.0 @@ -797,7 +967,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] @@ -842,7 +1012,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] @@ -871,7 +1041,7 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true + pre-indexed: true post-indexed: false throughput: 0.5 latency: 0.0