From a82a0e24a342ac732e0a6973d3897f20bdb5cdba Mon Sep 17 00:00:00 2001
From: JanLJL <jan.laukemann@fau.de>
Date: Mon, 19 Apr 2021 00:34:21 +0200
Subject: [PATCH] bugfixed CLX as uarch flag

---
 osaca/osaca.py | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/osaca/osaca.py b/osaca/osaca.py
index ec10e3a..7f5a606 100755
--- a/osaca/osaca.py
+++ b/osaca/osaca.py
@@ -20,7 +20,6 @@ SUPPORTED_ARCHS = [
     "BDW",
     "SKX",
     "CSX",
-    "CLX",
     "ICL",
     "ZEN1",
     "ZEN2",
@@ -182,6 +181,9 @@ def check_arguments(args, parser):
     """
     supported_import_files = ["ibench", "asmbench"]
 
+    # manually set CLX to CSX to support both abbreviations
+    if args.arch.upper() == "CLX":
+        args.arch = "CSX"
     if args.arch is None and (args.check_db or "import_data" in args):
         parser.error(
             "DB check and data import cannot work with a default microarchitecture. "
@@ -191,9 +193,6 @@ def check_arguments(args, parser):
         parser.error(
             "Microarchitecture not supported. Please see --help for all valid architecture codes."
         )
-    # manually set CLX to CSX to support both abbreviations
-    if args.arch.upper() == "CLX":
-        args.arch = "CSX"
     if "import_data" in args and args.import_data not in supported_import_files:
         parser.error(
             "Microbenchmark not supported for data import. Please see --help for all valid "