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Format code with black and fix flake8 linting issues

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- Applied black formatting with line length 99
- Fixed flake8 linting issues (E265 block comments)
- All 115 tests still pass after formatting
- Code style is now consistent across the codebase

Changes:
- osaca/parser/base_parser.py: improved line breaks and comment formatting
- osaca/osaca.py: added missing blank line
- osaca/db_interface.py: reformatted long lines and comments
- osaca/parser/parser_RISCV.py: extensive formatting improvements
- osaca/semantics/kernel_dg.py: improved formatting and readability
- osaca/semantics/hw_model.py: fixed shebang and formatting
- osaca/semantics/marker_utils.py: removed TODO comment and formatting
This commit is contained in:
Metehan Dundar
2025-07-11 22:28:29 +02:00
parent ebf76caa18
commit a8fca2afdb
7 changed files with 58 additions and 89 deletions
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22
osaca/db_interface.py
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@@ -412,20 +412,20 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True):
suspicious_prefixes_x86 = ["vfm", "fm"]
suspicious_prefixes_arm = ["fml", "ldp", "stp", "str"]
suspicious_prefixes_riscv = [
"vse", # Vector store (register is source, memory is destination)
"vse", # Vector store (register is source, memory is destination)
"vfmacc", # Vector FMA with accumulation (first operand is both source and destination)
"vfmadd", # Vector FMA with addition (first operand is implicitly both source and destination)
"vset", # Vector configuration (complex operand pattern)
"csrs", # CSR Set (first operand is both source and destination)
"csrc", # CSR Clear (first operand is both source and destination)
"csrsi", # CSR Set Immediate (first operand is both source and destination)
"csrci", # CSR Clear Immediate (first operand is both source and destination)
"amo", # Atomic memory operations (read-modify-write to memory)
"lr", # Load-Reserved (part of atomic operations)
"sc", # Store-Conditional (part of atomic operations)
"czero", # Conditional zero instructions (Zicond extension)
"vset", # Vector configuration (complex operand pattern)
"csrs", # CSR Set (first operand is both source and destination)
"csrc", # CSR Clear (first operand is both source and destination)
"csrsi", # CSR Set Immediate (first operand is both source and destination)
"csrci", # CSR Clear Immediate (first operand is both source and destination)
"amo", # Atomic memory operations (read-modify-write to memory)
"lr", # Load-Reserved (part of atomic operations)
"sc", # Store-Conditional (part of atomic operations)
"czero", # Conditional zero instructions (Zicond extension)
]
# Default to empty list if ISA not recognized
suspicious_prefixes = []