From 2d38cac9a1fc70a9a48dbf3a36bd7a20d5507ee8 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sat, 6 Nov 2021 16:04:16 +0800 Subject: [PATCH 01/29] simple implement for TSV110 --- osaca/data/tsv110.yml | 88 +++++++++++++++++++++++++++++++++++++ osaca/osaca.py | 3 +- osaca/semantics/hw_model.py | 1 + 3 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 osaca/data/tsv110.yml diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml new file mode 100644 index 0000000..d8b18df --- /dev/null +++ b/osaca/data/tsv110.yml @@ -0,0 +1,88 @@ +osaca_version: 0.4.6 +micro_architecture: TaiShan v110 +arch_code: tsv110 +isa: AArch64 +ROB_size: 128 +retired_uOps_per_cycle: 4 +scheduler_size: "*" +hidden_loads: false +load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} +load_throughput: +- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +ports: ['0', '1', '2', '3', '4', '5', '6', '7'] +port_model_scheme: | + +--------------------------------------------------------------------------------------------+ + | - entries | + +--------------------------------------------------------------------------------------------+ + 0 |ALU 1 |AB 2 |AB 3 |MDU 4 |FSU1 5 |FSU2 6 |LdSt 7 |LdSt + \/ \/ \/ \/ \/ \/ \/ \/ + +---------+ +---------+ +---------+ +-------------+ +-------+ +------ + +-------+ +-------+ + | INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST | + +---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+ + +---------+ +---------+ +-------+ +-------+ +instruction_forms: +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 # 1*p012 + port_pressure: [[1, '012']] +- name: ldur + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p67 + port_pressure: [[1, '67']] +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p67 + port_pressure: [[1, '67']] +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 1.0 # 1*p67 + port_pressure: [[1, '67']] \ No newline at end of file diff --git a/osaca/osaca.py b/osaca/osaca.py index 44f9683..2ff83c6 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -32,6 +32,7 @@ SUPPORTED_ARCHS = [ "TX2", "N1", "A64FX", + "TSV110", "A72", ] DEFAULT_ARCHS = { @@ -96,7 +97,7 @@ def create_parser(parser=None): "--arch", type=str, help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, " - "A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", + "A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", ) parser.add_argument( "--fixed", diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index 1ee6968..c4c9d90 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -266,6 +266,7 @@ class MachineModel(object): """Return ISA for given micro-arch ``arch``.""" arch_dict = { "a64fx": "aarch64", + "tsv110": "aarch64", "a72": "aarch64", "tx2": "aarch64", "n1": "aarch64", From de0982226bea263100bedcca1fee3b29d47980ce Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Wed, 17 Nov 2021 17:49:05 +0800 Subject: [PATCH 02/29] add some instructions with ibench --- osaca/data/tsv110.yml | 751 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 730 insertions(+), 21 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index d8b18df..9fffeb2 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -4,23 +4,9 @@ arch_code: tsv110 isa: AArch64 ROB_size: 128 retired_uOps_per_cycle: 4 -scheduler_size: "*" +scheduler_size: '*' hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} -load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} ports: ['0', '1', '2', '3', '4', '5', '6', '7'] port_model_scheme: | +--------------------------------------------------------------------------------------------+ @@ -32,7 +18,21 @@ port_model_scheme: | | INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST | +---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+ +---------+ +---------+ +-------+ +-------+ -instruction_forms: +load_throughput: +- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} +- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} +instruction_forms: - name: add operands: - class: register @@ -42,7 +42,7 @@ instruction_forms: - class: register prefix: w throughput: 0.3333 - latency: 1.0 # 1*p012 + latency: 1.0 port_pressure: [[1, '012']] - name: ldur operands: @@ -56,7 +56,7 @@ instruction_forms: post-indexed: false pre-indexed: false throughput: 0.5 - latency: 4.0 # 1*p67 + latency: 4.0 port_pressure: [[1, '67']] - name: ldr operands: @@ -70,7 +70,7 @@ instruction_forms: post-indexed: false pre-indexed: false throughput: 0.5 - latency: 4.0 # 1*p67 + latency: 4.0 port_pressure: [[1, '67']] - name: str operands: @@ -84,5 +84,714 @@ instruction_forms: post-indexed: false pre-indexed: false throughput: 0.5 - latency: 1.0 # 1*p67 - port_pressure: [[1, '67']] \ No newline at end of file + latency: 1.0 + port_pressure: [[1, '67']] +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fmla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: ~ + port_pressure: ~ + throughput: 0.33333 + uops: ~ +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: ~ + index: gpr + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: frecpe + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: stur + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fmla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: ~ + throughput: 0.33333 + uops: ~ +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: gpr + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: ~ + port_pressure: ~ + throughput: 0.33333 + uops: ~ +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: frecpe + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fmul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: stur + operands: + - class: register + prefix: d + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: ~ + throughput: 0.33333 + uops: ~ +- name: mov + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: ~ + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: ~ + index: ~ + scale: 1 + pre-indexed: false + post-indexed: true + latency: ~ + port_pressure: ~ + throughput: 1.0 + uops: ~ +- name: cmp + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: fmov + operands: + - class: register + prefix: s + - class: immediate + imd: int + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: cmp + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: ~ + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: ~ + index: gpr + scale: 1 + pre-indexed: false + post-indexed: false + latency: ~ + port_pressure: ~ + throughput: ~ + uops: ~ From 1359cc92ba992a6aefa93c069acd0ab38cdf1efd Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 15:17:38 +0100 Subject: [PATCH 03/29] adjusted non-instruction_form fields --- osaca/data/tsv110.yml | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 9fffeb2..5ed8047 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -4,9 +4,13 @@ arch_code: tsv110 isa: AArch64 ROB_size: 128 retired_uOps_per_cycle: 4 -scheduler_size: '*' +scheduler_size: ~ # unknown hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} +load_throughput: [] +load_throughput_default: [[1, '67']] +store_throughput: [] +store_throughput_default: [[1, '67']] ports: ['0', '1', '2', '3', '4', '5', '6', '7'] port_model_scheme: | +--------------------------------------------------------------------------------------------+ @@ -18,20 +22,6 @@ port_model_scheme: | | INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST | +---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+ +---------+ +---------+ +-------+ +-------+ -load_throughput: -- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]} -- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]} instruction_forms: - name: add operands: From a8a6f420611111b4f37458d637c2174829818977 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 17:32:51 +0100 Subject: [PATCH 04/29] unified STORE instructions --- osaca/data/tsv110.yml | 326 ++++++++++++++++++++++++------------------ 1 file changed, 186 insertions(+), 140 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 5ed8047..4aee1e0 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -62,35 +62,6 @@ instruction_forms: throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fmla operands: - class: register @@ -181,21 +152,6 @@ instruction_forms: port_pressure: ~ throughput: ~ uops: ~ -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: add operands: - class: register @@ -208,51 +164,6 @@ instruction_forms: port_pressure: ~ throughput: 0.33333 uops: ~ -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: ~ - index: gpr - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: stp operands: - class: register @@ -266,7 +177,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: ~ uops: ~ @@ -381,7 +292,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: ~ uops: ~ @@ -410,21 +321,6 @@ instruction_forms: port_pressure: ~ throughput: 0.33333 uops: ~ -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: gpr - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: sub operands: - class: register @@ -475,21 +371,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: fadd operands: - class: register @@ -515,7 +396,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: ~ uops: ~ @@ -559,7 +440,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: ~ uops: ~ @@ -574,7 +455,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: 1.0 uops: ~ @@ -648,7 +529,7 @@ instruction_forms: scale: 1 pre-indexed: false post-indexed: false - latency: ~ + latency: 0.0 port_pressure: ~ throughput: 1.0 uops: ~ @@ -725,21 +606,6 @@ instruction_forms: port_pressure: ~ throughput: ~ uops: ~ -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: cmp operands: - class: register @@ -785,3 +651,183 @@ instruction_forms: port_pressure: ~ throughput: ~ uops: ~ +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 1 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 1 From fd628a0dde07444bec35ad53cb4373ac1574df13 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 17:48:16 +0100 Subject: [PATCH 05/29] unified LOAD instructions --- osaca/data/tsv110.yml | 276 +++++++++++++++++++++++++++++------------- 1 file changed, 191 insertions(+), 85 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 4aee1e0..853a824 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -48,20 +48,6 @@ instruction_forms: throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - name: fmla operands: - class: register @@ -92,21 +78,6 @@ instruction_forms: port_pressure: ~ throughput: ~ uops: ~ -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsqrt operands: - class: register @@ -137,21 +108,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: add operands: - class: register @@ -474,21 +430,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fmul operands: - class: register @@ -636,21 +577,186 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: ldr operands: - class: register prefix: q - class: memory base: x - offset: ~ - index: gpr - scale: 1 + offset: '*' + index: '*' + scale: '*' pre-indexed: false post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: str operands: - class: register @@ -696,6 +802,21 @@ instruction_forms: latency: 0.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 2 - name: str operands: - class: register @@ -726,21 +847,6 @@ instruction_forms: latency: 0.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 0.0 - port_pressure: [[1, '67']] - uops: 2 - name: str operands: - class: register @@ -770,7 +876,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -785,7 +891,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -815,7 +921,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -830,4 +936,4 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 From a111ce7e8940ffb65033e2c0064ece4b998bd70e Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 18:34:39 +0100 Subject: [PATCH 06/29] unfified STP and LDP instructions --- osaca/data/tsv110.yml | 454 +++++++++++++++++++++++++++++------------- 1 file changed, 312 insertions(+), 142 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 853a824..1309550 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -120,23 +120,6 @@ instruction_forms: port_pressure: ~ throughput: 0.33333 uops: ~ -- name: stp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsub operands: - class: register @@ -152,23 +135,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: ldp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fmul operands: - class: register @@ -181,23 +147,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: fdiv operands: - class: register @@ -339,23 +288,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: stp - operands: - - class: register - prefix: q - - class: register - prefix: q - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsqrt operands: - class: register @@ -383,23 +315,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: stp - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ - name: stur operands: - class: register @@ -457,23 +372,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: stp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: 1.0 - uops: ~ - name: fadd operands: - class: register @@ -513,40 +411,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldp - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: 1.0 - uops: ~ -- name: ldp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: imd - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: cmp operands: - class: register @@ -577,6 +441,312 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'] + uops: 2 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: ~ + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'] + uops: 2 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 0.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 - name: ldr operands: - class: register @@ -617,7 +787,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -662,7 +832,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] @@ -691,7 +861,7 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true + pre-indexed: true post-indexed: false throughput: 0.5 latency: 4.0 @@ -797,7 +967,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] @@ -842,7 +1012,7 @@ instruction_forms: index: '*' scale: '*' pre-indexed: false - post-indexed: true + post-indexed: true throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] @@ -871,7 +1041,7 @@ instruction_forms: offset: '*' index: '*' scale: '*' - pre-indexed: true + pre-indexed: true post-indexed: false throughput: 0.5 latency: 0.0 From b43f4374b12a35575f83f925fd58c89572195a54 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 18:39:37 +0100 Subject: [PATCH 07/29] changed data for register renaming --- osaca/data/tsv110.yml | 50 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 1309550..5add987 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -216,16 +216,46 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ +- name: mov + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 - name: mov operands: - class: register prefix: x - class: register prefix: x - latency: ~ - port_pressure: ~ - throughput: 0.33333 - uops: ~ + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: q + - class: register + prefix: q + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 - name: sub operands: - class: register @@ -403,14 +433,14 @@ instruction_forms: operands: - class: register prefix: v - shape: b + shape: '*' - class: register prefix: v - shape: b - latency: ~ - port_pressure: ~ - throughput: 0.5 - uops: ~ + shape: '*' + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 - name: cmp operands: - class: register From fb2dbfa83f2bc9d4b581d8e010a17503fadbb799 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 18:48:13 +0100 Subject: [PATCH 08/29] added branch instructions and data for ADD --- osaca/data/tsv110.yml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 5add987..830c3be 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -23,6 +23,12 @@ port_model_scheme: | +---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+ +---------+ +---------+ +-------+ +-------+ instruction_forms: +- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq] + operands: + - class: identifier + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '12']] - name: add operands: - class: register @@ -116,10 +122,10 @@ instruction_forms: prefix: x - class: immediate imd: int - latency: ~ - port_pressure: ~ + latency: 1 + port_pressure: [[1, '012']] throughput: 0.33333 - uops: ~ + uops: 1 - name: fsub operands: - class: register @@ -425,10 +431,10 @@ instruction_forms: prefix: x - class: register prefix: x - latency: ~ - port_pressure: ~ + latency: 1 + port_pressure: [[1, '012']] throughput: 0.33333 - uops: ~ + uops: 1 - name: mov operands: - class: register From be48dd6c1beb1b3166acf647b6159300cba6b7b7 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Wed, 1 Dec 2021 11:42:36 +0800 Subject: [PATCH 09/29] add latency and TP information through ibench --- osaca/data/tsv110.yml | 288 +++++++++++++++++++++++------------------- 1 file changed, 161 insertions(+), 127 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 830c3be..2ef4567 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -1,8 +1,8 @@ osaca_version: 0.4.6 -micro_architecture: TaiShan v110 +micro_architecture: TaiShan v110 # https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 arch_code: tsv110 isa: AArch64 -ROB_size: 128 +ROB_size: 128 # https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64SchedTSV110.td#L21 retired_uOps_per_cycle: 4 scheduler_size: ~ # unknown hidden_loads: false @@ -29,6 +29,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '12']] +# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) - name: add operands: - class: register @@ -40,6 +41,7 @@ instruction_forms: throughput: 0.3333 latency: 1.0 port_pressure: [[1, '012']] +# memory instructions: ldur (data from AArch64SchedTSV110.td) - name: ldur operands: - class: register @@ -54,6 +56,7 @@ instruction_forms: throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] +# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) - name: fmla operands: - class: register @@ -65,10 +68,11 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ + latency: 4.0 port_pressure: ~ throughput: 0.5 uops: ~ +# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fdiv operands: - class: register @@ -80,10 +84,11 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 26.0 + port_pressure: [[1, '45']] + throughput: 22.0 + uops: 1 +# arithmetic instructions: fsqrt (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fsqrt operands: - class: register @@ -95,10 +100,11 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: ~ + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 34.0 uops: ~ +# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fadd operands: - class: register @@ -110,10 +116,10 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ + latency: 4.0 + port_pressure: [[1, '45']] throughput: 1.0 - uops: ~ + uops: 1 - name: add operands: - class: register @@ -137,10 +143,10 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ + latency: 4.0 + port_pressure: [[1, '45']] throughput: 1.0 - uops: ~ + uops: 1 - name: fmul operands: - class: register @@ -149,10 +155,10 @@ instruction_forms: prefix: d - class: register prefix: d - latency: ~ - port_pressure: ~ + latency: 5.0 + port_pressure: [[1, '45']] throughput: 0.5 - uops: ~ + uops: 1 - name: fdiv operands: - class: register @@ -164,10 +170,10 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 40.0 + port_pressure: [[1, '45']] + throughput: 36.0 + uops: 1 - name: frecpe operands: - class: register @@ -176,10 +182,11 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ + latency: 3.0 + port_pressure: [[1, '45']] throughput: 1.0 - uops: ~ + uops: 1 +# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: subs operands: - class: register @@ -188,25 +195,27 @@ instruction_forms: prefix: x - class: immediate imd: int - latency: ~ - port_pressure: ~ + latency: 1.0 + port_pressure: [[1, '12']] throughput: 0.5 - uops: ~ + uops: 1 +# memory instructions: stur (data from AArch64SchedTSV110.td) - name: stur operands: - class: register prefix: q - class: memory base: x - offset: ~ - index: ~ - scale: 1 + offset: '*' + index: '*' + scale: '*' pre-indexed: false post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: ~ - uops: ~ + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) - name: fmla operands: - class: register @@ -218,9 +227,9 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ + latency: 5.0 port_pressure: ~ - throughput: 1.0 + throughput: 1.322 uops: ~ - name: mov operands: @@ -270,10 +279,11 @@ instruction_forms: prefix: w - class: immediate imd: int - latency: ~ - port_pressure: ~ + latency: 1.0 + port_pressure: [[1, '012']] throughput: 0.33333 - uops: ~ + uops: 1 +# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: dup operands: - class: register @@ -281,10 +291,11 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 2.0 + port_pressure: [2, '45'] + throughput: 0.667 + uops: 2 +# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: frecpe operands: - class: register @@ -293,10 +304,10 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 - name: fmul operands: - class: register @@ -308,10 +319,10 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: 0.5 - uops: ~ + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 - name: fadd operands: - class: register @@ -320,10 +331,10 @@ instruction_forms: prefix: d - class: register prefix: d - latency: ~ - port_pressure: ~ + latency: 4.0 + port_pressure: [[1, '45']] throughput: 0.5 - uops: ~ + uops: 1 - name: fsqrt operands: - class: register @@ -335,10 +346,11 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 64.0 + uops: 1 +# arithmetic instructions: adds (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: adds operands: - class: register @@ -347,25 +359,25 @@ instruction_forms: prefix: x - class: immediate imd: int - latency: ~ - port_pressure: ~ + latency: 1.0 + port_pressure: [[1, '12']] throughput: 0.5 - uops: ~ + uops: 1 - name: stur operands: - class: register prefix: d - class: memory base: x - offset: ~ - index: ~ - scale: 1 + offset: '*' + index: '*' + scale: '*' pre-indexed: false post-indexed: false - latency: 0.0 - port_pressure: ~ - throughput: 1.0 - uops: ~ + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 - name: fsub operands: - class: register @@ -377,10 +389,10 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: 0.5 - uops: ~ + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 - name: fmul operands: - class: register @@ -392,10 +404,11 @@ instruction_forms: - class: register prefix: v shape: d - latency: ~ - port_pressure: ~ + latency: 5.0 + port_pressure: [[1, '45']] throughput: 1.0 - uops: ~ + uops: 1 +# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: mul operands: - class: register @@ -404,10 +417,10 @@ instruction_forms: prefix: x - class: register prefix: x - latency: ~ - port_pressure: ~ + latency: 4.0 + port_pressure: [[1, '3']] throughput: 1.0 - uops: ~ + uops: 1 - name: fadd operands: - class: register @@ -419,10 +432,10 @@ instruction_forms: - class: register prefix: v shape: s - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 - name: add operands: - class: register @@ -447,36 +460,38 @@ instruction_forms: port_pressure: [] throughput: 0.0 uops: 0 +# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) - name: cmp operands: - class: register prefix: x - class: register prefix: x - latency: ~ - port_pressure: ~ + latency: 1.0 + port_pressure: [1, '12'] throughput: 0.5 - uops: ~ + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) - name: fmov operands: - class: register prefix: s - class: immediate imd: int - latency: ~ - port_pressure: ~ - throughput: 0.5 - uops: ~ + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 - name: cmp operands: - class: register prefix: w - class: register prefix: w - latency: ~ - port_pressure: ~ + latency: 1.0 + port_pressure: [1, '12'] throughput: 0.5 - uops: ~ + uops: 1 - name: ldp operands: - class: register @@ -494,6 +509,24 @@ instruction_forms: latency: ~ port_pressure: [[2, '67'] uops: 2 +# memory instructions: ldp (data from AArch64SchedTSV110.td) +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 8.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: ldp operands: - class: register @@ -508,7 +541,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 - name: ldp @@ -525,7 +558,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 - name: ldp @@ -542,8 +575,8 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: ~ - port_pressure: [[2, '67']] + latency: 8.0 + port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldp operands: @@ -559,7 +592,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 - name: ldp @@ -576,7 +609,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 - name: ldp @@ -593,9 +626,9 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: ~ - port_pressure: [[2, '67']] - uops: 2 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 - name: ldp operands: - class: register @@ -610,7 +643,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 - name: ldp @@ -627,9 +660,10 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: ~ + latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 +# memory instructions: stp (data from AArch64SchedTSV110.td) - name: stp operands: - class: register @@ -644,7 +678,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 0.0 + latency: 2.0 port_pressure: [[2, '67'] uops: 2 - name: stp @@ -661,9 +695,9 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: stp operands: - class: register @@ -678,9 +712,9 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: stp operands: - class: register @@ -695,8 +729,8 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67']] + latency: 2.0 + port_pressure: [[2, '67'] uops: 2 - name: stp operands: @@ -712,9 +746,9 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: stp operands: - class: register @@ -729,9 +763,9 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: stp operands: - class: register @@ -746,7 +780,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 0.0 + latency: 2.0 port_pressure: [[2, '67']] uops: 2 - name: stp @@ -763,9 +797,9 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 3.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: stp operands: - class: register @@ -780,9 +814,9 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 0.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: ldr operands: - class: register From 2059269d8a3c3852dadc216785f79074c60d46e4 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Thu, 2 Dec 2021 22:55:39 +0800 Subject: [PATCH 10/29] fix typos --- osaca/data/tsv110.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 2ef4567..822db4f 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -507,7 +507,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: ~ - port_pressure: [[2, '67'] + port_pressure: [[2, '67']] uops: 2 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp @@ -679,7 +679,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 2.0 - port_pressure: [[2, '67'] + port_pressure: [[2, '67']] uops: 2 - name: stp operands: @@ -730,7 +730,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 2.0 - port_pressure: [[2, '67'] + port_pressure: [[2, '67']] uops: 2 - name: stp operands: From a89e31350e5428c85725c3a63d8999b255ec0a8e Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 16:17:00 +0800 Subject: [PATCH 11/29] fix latency in str/ldr instructions --- osaca/data/tsv110.yml | 59 +++++++++++++++---------------------------- 1 file changed, 21 insertions(+), 38 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 822db4f..c8b168f 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -492,23 +492,6 @@ instruction_forms: port_pressure: [1, '12'] throughput: 0.5 uops: 1 -- name: ldp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 1.0 - latency: ~ - port_pressure: [[2, '67']] - uops: 2 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp operands: @@ -844,7 +827,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -859,7 +842,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -874,7 +857,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67']] uops: 2 - name: ldr @@ -889,7 +872,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -904,7 +887,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -934,7 +917,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -949,7 +932,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -979,7 +962,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldr @@ -994,7 +977,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 4.0 + latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1009,7 +992,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67']] uops: 1 - name: str @@ -1024,7 +1007,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1039,7 +1022,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1054,7 +1037,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67']] uops: 2 - name: str @@ -1069,7 +1052,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1084,7 +1067,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 0.0 + latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1099,7 +1082,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67']] uops: 1 - name: str @@ -1114,7 +1097,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1129,7 +1112,7 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 0.0 + latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1144,7 +1127,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67']] uops: 1 - name: str @@ -1159,7 +1142,7 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 0.5 - latency: 0.0 + latency: 1.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: str @@ -1174,6 +1157,6 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 0.5 - latency: 0.0 + latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 From 3b0dfc714181df59c539c2294fd6f2bc8ad1482b Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 16:33:22 +0800 Subject: [PATCH 12/29] formatted, this commit just put the same instructions together in tsv110.yaml, didn't change any numbers --- osaca/data/tsv110.yml | 1437 +++++++++++++++++++++-------------------- 1 file changed, 721 insertions(+), 716 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index c8b168f..8441557 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -41,21 +41,230 @@ instruction_forms: throughput: 0.3333 latency: 1.0 port_pressure: [[1, '012']] -# memory instructions: ldur (data from AArch64SchedTSV110.td) -- name: ldur +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench) +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench) +- name: sub operands: - class: register prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] throughput: 0.5 + uops: 1 +# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x latency: 4.0 - port_pressure: [[1, '67']] + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +# arithmetic instructions: fsub (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +# arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fmul + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 40.0 + port_pressure: [[1, '45']] + throughput: 36.0 + uops: 1 +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 26.0 + port_pressure: [[1, '45']] + throughput: 22.0 + uops: 1 # arithmetic instructions: fmla (latency and throughput from ibench, port data missed) - name: fmla operands: @@ -72,23 +281,37 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: fdiv +- name: fmla operands: - class: register prefix: v - shape: s + shape: d - class: register prefix: v - shape: s + shape: d - class: register prefix: v - shape: s - latency: 26.0 - port_pressure: [[1, '45']] - throughput: 22.0 - uops: 1 + shape: d + latency: 5.0 + port_pressure: ~ + throughput: 1.322 + uops: ~ # arithmetic instructions: fsqrt (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 64.0 + uops: 1 - name: fsqrt operands: - class: register @@ -104,76 +327,7 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 34.0 uops: ~ -# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: fadd - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: add - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: immediate - imd: int - latency: 1 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -- name: fsub - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fmul - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: register - prefix: d - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 0.5 - uops: 1 -- name: fdiv - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 40.0 - port_pressure: [[1, '45']] - throughput: 36.0 - uops: 1 +# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: frecpe operands: - class: register @@ -186,19 +340,492 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.0 uops: 1 -# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: subs +- name: frecpe + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: mov + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: q + - class: register + prefix: q + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [2, '45'] + throughput: 0.667 + uops: 2 +# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) +- name: cmp operands: - class: register prefix: x - class: register prefix: x - - class: immediate - imd: int latency: 1.0 - port_pressure: [[1, '12']] + port_pressure: [1, '12'] throughput: 0.5 uops: 1 +- name: cmp + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: fmov + operands: + - class: register + prefix: s + - class: immediate + imd: int + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# memory instructions: ldur (data from AArch64SchedTSV110.td) + - name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: str (data from AArch64SchedTSV110.td) +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: ldur (data from AArch64SchedTSV110.td) +- name: ldur + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] # memory instructions: stur (data from AArch64SchedTSV110.td) - name: stur operands: @@ -215,154 +842,6 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 -# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) -- name: fmla - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 5.0 - port_pressure: ~ - throughput: 1.322 - uops: ~ -- name: mov - operands: - - class: register - prefix: w - - class: register - prefix: w - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: d - - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: q - - class: register - prefix: q - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: sub - operands: - - class: register - prefix: w - - class: register - prefix: w - - class: immediate - imd: int - latency: 1.0 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: dup - operands: - - class: register - prefix: d - - class: register - prefix: v - shape: d - latency: 2.0 - port_pressure: [2, '45'] - throughput: 0.667 - uops: 2 -# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: frecpe - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 3.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fmul - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -- name: fadd - operands: - - class: register - prefix: d - - class: register - prefix: d - - class: register - prefix: d - latency: 4.0 - port_pressure: [[1, '45']] - throughput: 0.5 - uops: 1 -- name: fsqrt - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 22.0 - port_pressure: [[1, '45']] - throughput: 64.0 - uops: 1 -# arithmetic instructions: adds (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: adds - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: immediate - imd: int - latency: 1.0 - port_pressure: [[1, '12']] - throughput: 0.5 - uops: 1 - name: stur operands: - class: register @@ -378,120 +857,6 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 -- name: fsub - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.321 - uops: 1 -- name: fmul - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - - class: register - prefix: v - shape: d - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.0 - uops: 1 -# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: mul - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: register - prefix: x - latency: 4.0 - port_pressure: [[1, '3']] - throughput: 1.0 - uops: 1 -- name: fadd - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 5.0 - port_pressure: [[1, '45']] - throughput: 1.321 - uops: 1 -- name: add - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: register - prefix: x - latency: 1 - port_pressure: [[1, '012']] - throughput: 0.33333 - uops: 1 -- name: mov - operands: - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) -- name: cmp - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 1.0 - port_pressure: [1, '12'] - throughput: 0.5 - uops: 1 -# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) -- name: fmov - operands: - - class: register - prefix: s - - class: immediate - imd: int - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: cmp - operands: - - class: register - prefix: w - - class: register - prefix: w - latency: 1.0 - port_pressure: [1, '12'] - throughput: 0.5 - uops: 1 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp operands: @@ -800,363 +1165,3 @@ instruction_forms: latency: 2.0 port_pressure: [[2, '67'], [1, '012']] uops: 3 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - uops: 1 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 5.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: w - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: d - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 1 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 -- name: str - operands: - - class: register - prefix: q - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] - uops: 2 From 38602536011b594f61c91a11a6c9d515b0eb497e Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 16:58:30 +0800 Subject: [PATCH 13/29] double check with every data in instructions --- osaca/data/tsv110.yml | 162 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 141 insertions(+), 21 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 8441557..0994233 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -65,6 +65,18 @@ instruction_forms: port_pressure: [[1, '012']] throughput: 0.33333 uops: 1 +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 # arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench) - name: adds operands: @@ -79,6 +91,42 @@ instruction_forms: throughput: 0.5 uops: 1 # arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench) +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 - name: sub operands: - class: register @@ -160,7 +208,31 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.321 uops: 1 -# arithmetic instructions: fsub (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +# arithmetic instructions: fsub (latency and throughput from ibench and asmbench, port data from AArch64SchedTSV110.td) +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fadd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 - name: fsub operands: - class: register @@ -189,7 +261,7 @@ instruction_forms: shape: s latency: 5.0 port_pressure: [[1, '45']] - throughput: 1.321 + throughput: 0.5 uops: 1 # arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fmul @@ -232,9 +304,33 @@ instruction_forms: shape: s latency: 5.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 + uops: 1 +# arithmetic instructions: fdiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fdiv + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 6.0 + port_pressure: [[1, '4']] + throughput: 6.0 + uops: 1 +- name: fdiv + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 6.0 + port_pressure: [[1, '4']] + throughput: 6.0 uops: 1 -# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fdiv operands: - class: register @@ -246,9 +342,9 @@ instruction_forms: - class: register prefix: v shape: d - latency: 40.0 - port_pressure: [[1, '45']] - throughput: 36.0 + latency: 16.0 + port_pressure: [[1, '4']] + throughput: 12..0 uops: 1 - name: fdiv operands: @@ -261,11 +357,11 @@ instruction_forms: - class: register prefix: v shape: s - latency: 26.0 - port_pressure: [[1, '45']] - throughput: 22.0 + latency: 16.0 + port_pressure: [[1, '4']] + throughput: 12.0 uops: 1 -# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) +# arithmetic instructions: fmla (latency and throughput from ibench, uops and port data missed) - name: fmla operands: - class: register @@ -277,7 +373,7 @@ instruction_forms: - class: register prefix: v shape: s - latency: 4.0 + latency: 5.0 port_pressure: ~ throughput: 0.5 uops: ~ @@ -292,11 +388,35 @@ instruction_forms: - class: register prefix: v shape: d - latency: 5.0 + latency: 7.0 port_pressure: ~ - throughput: 1.322 + throughput: 1.0 uops: ~ -# arithmetic instructions: fsqrt (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +# arithmetic instructions: fsqrt (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fsqrt + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 9.0 + port_pressure: [[1, '5']] + throughput: 9.0 + uops: 1 +- name: fsqrt + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 9.0 + port_pressure: [[1, '5']] + throughput: 9.0 + uops: 1 - name: fsqrt operands: - class: register @@ -309,8 +429,8 @@ instruction_forms: prefix: v shape: d latency: 22.0 - port_pressure: [[1, '45']] - throughput: 64.0 + port_pressure: [[1, '5']] + throughput: 18.0 uops: 1 - name: fsqrt operands: @@ -324,9 +444,9 @@ instruction_forms: prefix: v shape: s latency: 22.0 - port_pressure: [[1, '45']] - throughput: 34.0 - uops: ~ + port_pressure: [[1, '5']] + throughput: 18.0 + uops: 1 # arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: frecpe operands: @@ -414,7 +534,7 @@ instruction_forms: prefix: v shape: d latency: 2.0 - port_pressure: [2, '45'] + port_pressure: [[1, '4'], [1, '5']] throughput: 0.667 uops: 2 # miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) From 871b79af90c237aa41c3019f0b466d7a123a4010 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 18:27:42 +0800 Subject: [PATCH 14/29] add some instructions in tsv110.yml --- osaca/data/tsv110.yml | 549 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 547 insertions(+), 2 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 0994233..6cc98ac 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -29,6 +29,182 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '12']] +# logical instructions: and (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: bic + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: bics (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: bics + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +# shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) - name: add operands: @@ -140,6 +316,18 @@ instruction_forms: throughput: 0.33333 uops: 1 # arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 - name: subs operands: - class: register @@ -165,6 +353,154 @@ instruction_forms: port_pressure: [[1, '3']] throughput: 1.0 uops: 1 +- name: mul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +# arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: mla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +# arithmetic instructions: neg (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: neg + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 # arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fadd operands: @@ -558,7 +894,216 @@ instruction_forms: port_pressure: [1, '12'] throughput: 0.5 uops: 1 -# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: zip1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: zip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: zip2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: uzip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: uzip1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: uzip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: uzip2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: scvtf (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions) +- name: scvtf + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: scvtf + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '45']] + throughput: 2.0 + uops: 1 +# miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion) - name: fmov operands: - class: register @@ -570,7 +1115,7 @@ instruction_forms: throughput: 0.0 uops: 0 # memory instructions: ldur (data from AArch64SchedTSV110.td) - - name: ldr +- name: ldr operands: - class: register prefix: w From b9c4f228b7fb1ba651602be04a41a87eb10d8968 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Wed, 15 Dec 2021 21:51:59 +0800 Subject: [PATCH 15/29] add some instructions for tsv110 --- osaca/data/tsv110.yml | 241 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 6cc98ac..12645b7 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -42,6 +42,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 - name: and operands: - class: register @@ -54,6 +66,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: ands operands: @@ -67,6 +91,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '12']] uops: 1 +- name: ands + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 - name: ands operands: - class: register @@ -79,6 +115,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '12']] uops: 1 +- name: ands + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 # logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: orr operands: @@ -92,6 +140,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: orr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 - name: orr operands: - class: register @@ -104,6 +164,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: orr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: eor operands: @@ -117,6 +189,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: eor + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 - name: eor operands: - class: register @@ -129,6 +213,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: eor + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: bic operands: @@ -253,7 +349,73 @@ instruction_forms: port_pressure: [[1, '012']] throughput: 0.33333 uops: 1 +- name: add + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '45']] +- name: add + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '45']] +- name: add + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + throughput: 0.5 + latency: 2.0 + port_pressure: [[1, '45']] # arithmetic instructions: adds (from AArch64SchedTSV110.td and ibench) +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: adds + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 - name: adds operands: - class: register @@ -266,6 +428,44 @@ instruction_forms: port_pressure: [[1, '12']] throughput: 0.5 uops: 1 +- name: adds + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench) +- name: adc + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench) +- name: adc + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 # arithmetic instructions: sub (from AArch64SchedTSV110.td and ibench) - name: sub operands: @@ -894,6 +1094,47 @@ instruction_forms: port_pressure: [1, '12'] throughput: 0.5 uops: 1 +- name: cmp + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +- name: cmp + operands: + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +# miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: dup + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: x + throughput: 0.667 + latency: 2.0 + port_pressure: [[1, '5']] +- name: dup + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: w + throughput: 0.667 + latency: 2.0 + port_pressure: [[1, '5']] # miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) - name: zip1 operands: From 45b70e0961cd8a3c3ac31b6cc954d8a5d458ef23 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sat, 18 Dec 2021 15:44:07 +0800 Subject: [PATCH 16/29] add some instructions for tsv110 --- osaca/data/tsv110.yml | 191 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 183 insertions(+), 8 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 12645b7..f37ea19 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -301,6 +301,31 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +# shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) - name: add operands: @@ -440,6 +465,21 @@ instruction_forms: port_pressure: [[1, '12']] throughput: 0.5 uops: 1 +# arithmetic instructions: addp (from AArch64SchedTSV110.td) +- name: addp + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '45']] # arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench) - name: adc operands: @@ -744,8 +784,53 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.321 uops: 1 +# arithmetic instructions: fabs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fabs + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fabs + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fabs + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fabs + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 # arithmetic instructions: fsub (latency and throughput from ibench and asmbench, port data from AArch64SchedTSV110.td) -- name: fadd +- name: fsub operands: - class: register prefix: d @@ -757,7 +842,7 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 0.5 uops: 1 -- name: fadd +- name: fsub operands: - class: register prefix: s @@ -1008,6 +1093,27 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.0 uops: 1 +# arithmetic instructions: fcmp (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fcmp + operands: + - class: register + prefix: d + - class: immediate + imd: float + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fcmp + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 # miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) - name: mov operands: @@ -1064,15 +1170,67 @@ instruction_forms: # miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: dup operands: - - class: register - prefix: d - class: register prefix: v shape: d + - class: register + prefix: x latency: 2.0 port_pressure: [[1, '4'], [1, '5']] throughput: 0.667 uops: 2 +- name: dup + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: w + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.667 + uops: 2 +# miscellaneous instructions: cmn (throughput from ibench, latency and port data from AArch64SchedTSV110.td) +- name: cmn + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: cmn + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: cmn + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: cmn + operands: + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 # miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) - name: cmp operands: @@ -1081,7 +1239,7 @@ instruction_forms: - class: register prefix: x latency: 1.0 - port_pressure: [1, '12'] + port_pressure: [[1, '12']] throughput: 0.5 uops: 1 - name: cmp @@ -1091,7 +1249,7 @@ instruction_forms: - class: register prefix: w latency: 1.0 - port_pressure: [1, '12'] + port_pressure: [[1, '12']] throughput: 0.5 uops: 1 - name: cmp @@ -1101,7 +1259,7 @@ instruction_forms: - class: immediate imd: int latency: 1.0 - port_pressure: [1, '12'] + port_pressure: [[1, '12']] throughput: 0.5 uops: 1 - name: cmp @@ -1111,7 +1269,7 @@ instruction_forms: - class: immediate imd: int latency: 1.0 - port_pressure: [1, '12'] + port_pressure: [[1, '12']] throughput: 0.5 uops: 1 # miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) @@ -1125,6 +1283,7 @@ instruction_forms: throughput: 0.667 latency: 2.0 port_pressure: [[1, '5']] + uops: 1 - name: dup operands: - class: register @@ -1135,6 +1294,22 @@ instruction_forms: throughput: 0.667 latency: 2.0 port_pressure: [[1, '5']] + uops: 1 +# miscellaneous instructions: extr (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: extr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) - name: zip1 operands: From dc2d605d6a99286769c8f23108505fd31aa0ad1b Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sat, 18 Dec 2021 17:51:41 +0800 Subject: [PATCH 17/29] add some instructions for tsv110 --- osaca/data/tsv110.yml | 341 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 330 insertions(+), 11 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index f37ea19..ce1b69e 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -264,6 +264,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: lsl + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 - name: lsl operands: - class: register @@ -276,6 +288,18 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: lsl + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: lsr operands: @@ -638,6 +662,35 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 2.5 uops: 1 +# arithmetic instructions: madd (latency and throughput, port data from AArch64SchedTSV110.td) +- name: madd + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: [[1, '3'], [1, '012']] + throughput: ~ + uops: 2 +- name: madd + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: ~ + port_pressure: [[1, '3'], [1, '012']] + throughput: ~ + uops: 2 # arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: mla operands: @@ -784,6 +837,85 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.321 uops: 1 +# arithmetic instructions: fmadd (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fmadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 0.73 + uops: 1 +- name: fmadd + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.57 + uops: 1 +# arithmetic instructions: fnmsub (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fnmsub + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 7.0 + port_pressure: [[1, '45']] + throughput: 0.73 + uops: 1 +- name: fnmsub + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.57 + uops: 1 +# arithmetic instructions: frint[a|m|p|x|z] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: frinta + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: frintm + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 # arithmetic instructions: fabs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fabs operands: @@ -884,6 +1016,51 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 0.5 uops: 1 +# arithmetic instructions: fneg (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fneg + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fneg + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fneg + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 1 + uops: 1 +- name: fneg + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 # arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fmul operands: @@ -1020,8 +1197,6 @@ instruction_forms: prefix: d - class: register prefix: d - - class: register - prefix: d latency: 9.0 port_pressure: [[1, '5']] throughput: 9.0 @@ -1032,8 +1207,6 @@ instruction_forms: prefix: s - class: register prefix: s - - class: register - prefix: s latency: 9.0 port_pressure: [[1, '5']] throughput: 9.0 @@ -1046,9 +1219,6 @@ instruction_forms: - class: register prefix: v shape: d - - class: register - prefix: v - shape: d latency: 22.0 port_pressure: [[1, '5']] throughput: 18.0 @@ -1061,9 +1231,6 @@ instruction_forms: - class: register prefix: v shape: s - - class: register - prefix: v - shape: s latency: 22.0 port_pressure: [[1, '5']] throughput: 18.0 @@ -1114,6 +1281,88 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.0 uops: 1 +- name: fcmp + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fcmpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fcmpe + operands: + - class: register + prefix: d + - class: immediate + imd: float + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fcmpe + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: fcmpe + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fcvt[as|pu｜zs|zu] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: fcvt + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 +- name: fcvtpu + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 +- name: fcvtzs + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 +- name: fcvtzu + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 # miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) - name: mov operands: @@ -1520,12 +1769,82 @@ instruction_forms: throughput: 2.0 uops: 1 # miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion) +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: s + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: w + - class: register + prefix: s + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: fmov + operands: + - class: register + prefix: d + - class: immediate + imd: float + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 - name: fmov operands: - class: register prefix: s - class: immediate - imd: int + imd: float latency: 0.0 port_pressure: [] throughput: 0.0 From e20fb2167937ca5436095bdaccba1576754908dd Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sun, 19 Dec 2021 18:13:32 +0800 Subject: [PATCH 18/29] add some instructions for tsv110, now support most of the instructions --- osaca/data/tsv110.yml | 789 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 769 insertions(+), 20 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index ce1b69e..d43850d 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -176,6 +176,46 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +# logical instructions: orn (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: orr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: orr + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + throughput: 1 + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + uops: 2 # logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: eor operands: @@ -251,6 +291,50 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '12']] uops: 1 +# logical instructions: rbit (latency and throughput, port data from AArch64SchedTSV110.td) +- name: rbit + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: rbit + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: rev[16|32] (latency and throughput, port data from AArch64SchedTSV110.td) +- name: [rev, rev16, rev32] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: [rev, rev16, rev32] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: lsl operands: @@ -350,6 +434,91 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +# shift instructions: ror (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: ror + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: ror + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# shift instructions: [s|u]shll (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [sshll, ushll] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 4.0 + throughput: 1.0 + port_pressure: [[1, '5']] + uops: 1 +- name: [sshll, ushll] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: immediate + imd: int + latency: 4.0 + throughput: 1.0 + port_pressure: [[1, '5']] + uops: 1 +# shift instructions: sshll2 (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: sshll2 + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 4.0 + throughput: 1.0 + port_pressure: [[1, '5']] + uops: 1 +- name: sshll2 + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: immediate + imd: int + latency: 4.0 + throughput: 1.0 + port_pressure: [[1, '5']] + uops: 1 # arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) - name: add operands: @@ -604,6 +773,31 @@ instruction_forms: port_pressure: [[1, '12']] throughput: 0.5 uops: 1 +# arithmetic instructions: sbc (latency and throughput, port data from AArch64SchedTSV110.td) +- name: sbc + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.5 + uops: 1 +- name: sbc + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 0.333 + port_pressure: [[1, '012']] + throughput: 0.5 + uops: 1 # arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: mul operands: @@ -632,7 +826,7 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 2.5 uops: 1 -- name: mla +- name: mul operands: - class: register prefix: v @@ -647,7 +841,7 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 2.5 uops: 1 -- name: mla +- name: mul operands: - class: register prefix: v @@ -662,6 +856,82 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 2.5 uops: 1 +# arithmetic instructions: [s|u]mulh (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [smulh, umulh] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: [s|u]mull (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [smulh, umulh] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + latency: 3.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: sdiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: sdiv + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 6.0 + port_pressure: [[1, '3']] + throughput: 5.0 + uops: 1 +- name: sdiv + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: udiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: udiv + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 6.0 + port_pressure: [[1, '3']] + throughput: 5.0 + uops: 1 +- name: udiv + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 # arithmetic instructions: madd (latency and throughput, port data from AArch64SchedTSV110.td) - name: madd operands: @@ -691,6 +961,80 @@ instruction_forms: port_pressure: [[1, '3'], [1, '012']] throughput: ~ uops: 2 +# arithmetic instructions: [smaddl|umaddl] (latency and throughput, port data from AArch64SchedTSV110.td) +- name: [smaddl,umaddl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: x + latency: 3.0 + port_pressure: [[1, '3'], [1, '012']] + throughput: 1.0 + uops: 2 +# arithmetic instructions: [smsubl|umsubl] (latency and throughput, port data from AArch64SchedTSV110.td) +- name: [smsubl, umsubl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: x + latency: 3.0 + port_pressure: [[1, '3'], [1, '012']] + throughput: 1.0 + uops: 2 +# arithmetic instructions: msub (latency and throughput, port data from AArch64SchedTSV110.td) +- name: msub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: ~ + port_pressure: [[1, '3'], [1, '012']] + throughput: ~ + uops: 2 +- name: msub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: ~ + port_pressure: [[1, '3'], [1, '012']] + throughput: ~ + uops: 2 +# arithmetic instructions: smsubl (latency and throughput, port data from AArch64SchedTSV110.td) +- name: smsubl + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: x + latency: 3.0 + port_pressure: [[1, '3'], [1, '012']] + throughput: 1.0 + uops: 2 # arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: mla operands: @@ -737,17 +1081,73 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 2.5 uops: 1 -# arithmetic instructions: neg (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +# arithmetic instructions: [s|u]max (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [smax, umax] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: [s|u]min (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [smin, umin] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: [s|u]maxv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [smaxv, umaxv] + operands: + - class: register + prefix: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: [s|u]minv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: [sminv, uminv] + operands: + - class: register + prefix: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 1 +# arithmetic instructions: neg (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: neg operands: - class: register prefix: x - class: register prefix: x - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + latency: 1.0 + port_pressure: [[1, '012']] throughput: 1.0 - uops: 2 + uops: 1 - name: neg operands: - class: register @@ -755,9 +1155,9 @@ instruction_forms: - class: register prefix: d latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '12']] throughput: 1.0 - uops: 2 + uops: 1 - name: neg operands: - class: register @@ -767,9 +1167,9 @@ instruction_forms: prefix: v shape: d latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '12']] throughput: 1.0 - uops: 2 + uops: 1 - name: neg operands: - class: register @@ -779,9 +1179,9 @@ instruction_forms: prefix: v shape: s latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '12']] throughput: 1.0 - uops: 2 + uops: 1 - name: neg operands: - class: register @@ -791,9 +1191,20 @@ instruction_forms: prefix: v shape: h latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '12']] throughput: 1.0 - uops: 2 + uops: 1 +# arithmetic instructions: negs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: neg + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 2.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 # arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fadd operands: @@ -1363,7 +1774,18 @@ instruction_forms: port_pressure: [[1, '4']] throughput: 1.0 uops: 1 -# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +# mov instructions: adrp? (latency and throughput from asmbench, from AArch64SchedTSV110.td) +- name: [adr, adrp] + operands: + - class: register + prefix: '*' + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.333 + uops: 1 +# mov instructions: mov (assumed free register renaming, register to register moves without conversion) - name: mov operands: - class: register @@ -1405,6 +1827,48 @@ instruction_forms: throughput: 0.0 uops: 0 - name: mov +# mov instructions: mvn (assumed free register renaming, register to register moves without conversion) +- name: mvn + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mvn + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mvn + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mvn + operands: + - class: register + prefix: q + - class: register + prefix: q + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mvn operands: - class: register prefix: v @@ -1416,6 +1880,48 @@ instruction_forms: port_pressure: [] throughput: 0.0 uops: 0 +# mov instructions: mov[i|k|n|z] (assumed free register renaming, register to register moves without conversion) +- name: [movi, movk, movn, movz] + operands: + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.333 + uops: 1 +- name: [movi, movk, movn, movz] + operands: + - class: register + prefix: d + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.333 + uops: 1 +- name: [movi, movk, movn, movz] + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.333 + uops: 1 +- name: [movi, movk, movn, movz] + operands: + - class: register + prefix: v + shape: '*' + - class: immediate + imd: int + latency: 3.0 + port_pressure: [[1, '4']] + throughput: 1 + uops: 1 # miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: dup operands: @@ -1559,6 +2065,36 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +# miscellaneous instructions: sbifz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sbifz + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# miscellaneous instructions: sbfz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sbfz + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) - name: zip1 operands: @@ -1743,8 +2279,8 @@ instruction_forms: port_pressure: [[1, '4'], [1, '5']] throughput: 0.5 uops: 2 -# miscellaneous instructions: scvtf (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions) -- name: scvtf +# miscellaneous instructions: [scvtf|ucvtf] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions) +- name: [scvtf, ucvtf] operands: - class: register prefix: v @@ -1756,7 +2292,7 @@ instruction_forms: port_pressure: [[1, '45']] throughput: 1.0 uops: 1 -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: v @@ -1768,6 +2304,45 @@ instruction_forms: port_pressure: [[2, '45']] throughput: 2.0 uops: 1 +# miscellaneous instructions: [s|u]xt[b|h|w] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td) +- name: [sxtb, sxth, sxtw, uxtb, uxth, uxtw] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 1.0 + uops: 1 +# miscellaneous instructions: xtn2? (throughput and latency from asmbench, port data from AArch64SchedTSV110.td) +- name: [xtn, xtn2] + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 1 +# miscellaneous instructions: [ubfiz|ubfx|ubfm] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td) +- name: [ubfiz, ubfx, ubfm] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 1.0 + uops: 1 # miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion) - name: fmov operands: @@ -1849,7 +2424,102 @@ instruction_forms: port_pressure: [] throughput: 0.0 uops: 0 -# memory instructions: ldur (data from AArch64SchedTSV110.td) +# test instructions: tst (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: tst + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: tst + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: tst + operands: + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +- name: tst + operands: + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 +# cryptography instructions: sha1[c|m|p] (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: [sha1c, sha1m, sha1p] + operands: + - class: register + prefix: q + - class: register + prefix: s + - class: register + prefix: v + shape: '*' + latency: 5.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 +# cryptography instructions: sha1h (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sha1h + operands: + - class: register + prefix: s + - class: register + prefix: s + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sha1su0 + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sha1su0 + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 2.0 + port_pressure: [[1, '4']] + throughput: 1.0 + uops: 1 +# memory instructions: ldr (data from AArch64SchedTSV110.td) - name: ldr operands: - class: register @@ -2030,7 +2700,38 @@ instruction_forms: latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 -# memory instructions: str (data from AArch64SchedTSV110.td) +# memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td) +- name: [ldar, ldarb, ldaxr] + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: [ldar, ldarb, ldaxr] + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 + # memory instructions: str (data from AArch64SchedTSV110.td) - name: str operands: - class: register @@ -2211,6 +2912,38 @@ instruction_forms: latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +# memory instructions: stlr (data from AArch64SchedTSV110.td) +- name: stlr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +# memory instructions: stlrb (data from AArch64SchedTSV110.td) +- name: stlrb + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 # memory instructions: ldur (data from AArch64SchedTSV110.td) - name: ldur operands: @@ -2257,6 +2990,22 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 +# memory instructions: stur[b|h] (data from AArch64SchedTSV110.td) +- name: [sturb, sturh] + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp operands: From 4e5b768780d2d40eb3087ee2ccebc8a77c332803 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Thu, 30 Dec 2021 21:24:41 +0800 Subject: [PATCH 19/29] fix some instr for tsv110 --- osaca/data/tsv110.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index d43850d..87c5da2 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -742,8 +742,8 @@ instruction_forms: prefix: w - class: register prefix: w - - class: immediate - imd: int + - class: register + prefix: w latency: 1.0 port_pressure: [[1, '012']] throughput: 0.33333 @@ -3010,9 +3010,9 @@ instruction_forms: - name: ldp operands: - class: register - prefix: x + prefix: w - class: register - prefix: x + prefix: w - class: memory base: x offset: '*' @@ -3021,7 +3021,7 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 8.0 + latency: 4.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 - name: ldp From 5d36b56e07f6585b5729b2404f71748193aee2d5 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 4 Jan 2022 18:45:32 +0800 Subject: [PATCH 20/29] add some instructions for tsv110 --- osaca/data/tsv110.yml | 70 +++++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 15 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 87c5da2..86aaff6 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -409,6 +409,30 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: lsr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: lsr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: asr operands: @@ -2700,6 +2724,21 @@ instruction_forms: latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +# memory instructions: ldur (data from AArch64SchedTSV110.td) +- name: ldur + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] # memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td) - name: [ldar, ldarb, ldaxr] operands: @@ -2912,6 +2951,22 @@ instruction_forms: latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +# memory instructions: stlb (data from AArch64SchedTSV110.td) +- name: strb + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 # memory instructions: stlr (data from AArch64SchedTSV110.td) - name: stlr operands: @@ -2944,21 +2999,6 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '67']] uops: 1 -# memory instructions: ldur (data from AArch64SchedTSV110.td) -- name: ldur - operands: - - class: register - prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] # memory instructions: stur (data from AArch64SchedTSV110.td) - name: stur operands: From f8c23ce43d7a63a3a87dfff067b8372db4f373f8 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 4 Jan 2022 20:59:35 +0800 Subject: [PATCH 21/29] add some instructions for tsv110 --- osaca/data/tsv110.yml | 47 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 86aaff6..0058b69 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -835,6 +835,18 @@ instruction_forms: port_pressure: [[1, '3']] throughput: 1.0 uops: 1 +- name: mul + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 - name: mul operands: - class: register @@ -894,7 +906,7 @@ instruction_forms: throughput: 1.0 uops: 1 # arithmetic instructions: [s|u]mull (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) -- name: [smulh, umulh] +- name: [smull, umull] operands: - class: register prefix: x @@ -2724,6 +2736,22 @@ instruction_forms: latency: 5.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +# memory instructions: ldrb (data from AArch64SchedTSV110.td) +- name: ldrb + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 # memory instructions: ldur (data from AArch64SchedTSV110.td) - name: ldur operands: @@ -3166,6 +3194,23 @@ instruction_forms: latency: 9.0 port_pressure: [[2, '67'], [2, '012']] uops: 4 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 - name: ldp operands: - class: register From 0e04963ace0cf80f8df18fe9d9c5d352e5a05189 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Thu, 6 Jan 2022 16:25:08 +0800 Subject: [PATCH 22/29] modify some instructions for tsv110 --- osaca/data/tsv110.yml | 157 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 151 insertions(+), 6 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 0058b69..469b420 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -458,6 +458,30 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 +- name: asr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: asr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # shift instructions: ror (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: ror operands: @@ -1182,7 +1206,17 @@ instruction_forms: prefix: x latency: 1.0 port_pressure: [[1, '012']] - throughput: 1.0 + throughput: 0.333 + uops: 1 +- name: neg + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.333 uops: 1 - name: neg operands: @@ -1192,7 +1226,7 @@ instruction_forms: prefix: d latency: 2.0 port_pressure: [[1, '12']] - throughput: 1.0 + throughput: 0.333 uops: 1 - name: neg operands: @@ -1204,7 +1238,7 @@ instruction_forms: shape: d latency: 2.0 port_pressure: [[1, '12']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: neg operands: @@ -1216,7 +1250,7 @@ instruction_forms: shape: s latency: 2.0 port_pressure: [[1, '12']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: neg operands: @@ -1228,10 +1262,10 @@ instruction_forms: shape: h latency: 2.0 port_pressure: [[1, '12']] - throughput: 1.0 + throughput: 0.5 uops: 1 # arithmetic instructions: negs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) -- name: neg +- name: negs operands: - class: register prefix: x @@ -2752,6 +2786,52 @@ instruction_forms: latency: 4.0 port_pressure: [[1, '67']] uops: 1 +- name: ldrb + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: ldrh (data from AArch64SchedTSV110.td) +- name: ldrh + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldrh + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 # memory instructions: ldur (data from AArch64SchedTSV110.td) - name: ldur operands: @@ -2767,6 +2847,20 @@ instruction_forms: throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] +- name: ldur + operands: + - class: register + prefix: x + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] # memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td) - name: [ldar, ldarb, ldaxr] operands: @@ -3297,6 +3391,57 @@ instruction_forms: latency: 2.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: w + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: stp operands: - class: register From 4aeb031240453b5ab9a8af0c554f1368ad4d0480 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Wed, 26 Jan 2022 14:24:48 +0100 Subject: [PATCH 23/29] added lane comparison for AArch64 reg operands --- osaca/semantics/hw_model.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index c4c9d90..fc80a84 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -639,6 +639,12 @@ class MachineModel(object): ): return True return False + if "lanes" in reg: + if "lanes" in i_reg and ( + reg["lanes"] == i_reg["lanes"] or self.WILDCARD in (reg["lanes"] + i_reg["lanes"]) + ): + return True + return False return True def _is_x86_reg_type(self, i_reg, reg, consider_masking=False): From c9d63f7d3c7fdccaf80b294c2575a737d51514b5 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Wed, 26 Jan 2022 14:25:01 +0100 Subject: [PATCH 24/29] adjusted DB --- osaca/data/tsv110.yml | 966 ++++++++++++++++-------------------------- 1 file changed, 367 insertions(+), 599 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 469b420..8ccf52b 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -10,7 +10,7 @@ load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} load_throughput: [] load_throughput_default: [[1, '67']] store_throughput: [] -store_throughput_default: [[1, '67']] +store_throughput_default: [[1, '7']] ports: ['0', '1', '2', '3', '4', '5', '6', '7'] port_model_scheme: | +--------------------------------------------------------------------------------------------+ @@ -719,7 +719,7 @@ instruction_forms: prefix: v shape: '*' throughput: 0.5 - latency: 5.0 + latency: 2.0 port_pressure: [[1, '45']] # arithmetic instructions: adc (from AArch64SchedTSV110.td and ibench) - name: adc @@ -832,7 +832,7 @@ instruction_forms: prefix: x latency: 1.0 port_pressure: [[1, '012']] - throughput: 0.5 + throughput: 0.33333 uops: 1 - name: sbc operands: @@ -842,9 +842,9 @@ instruction_forms: prefix: w - class: register prefix: w - latency: 0.333 + latency: 1.0 port_pressure: [[1, '012']] - throughput: 0.5 + throughput: 0.33333 uops: 1 # arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: mul @@ -867,6 +867,24 @@ instruction_forms: prefix: w - class: register prefix: w + latency: 3.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +- name: mul + operands: + - class: register + prefix: v + shape: s + lanes: 2 + - class: register + prefix: v + shape: s + lanes: 2 + - class: register + prefix: v + shape: s + lanes: 2 latency: 4.0 port_pressure: [[1, '3']] throughput: 1.0 @@ -875,46 +893,91 @@ instruction_forms: operands: - class: register prefix: v - shape: d + shape: h + lanes: 4 - class: register prefix: v - shape: d + shape: h + lanes: 4 - class: register prefix: v - shape: d - latency: 7.0 - port_pressure: [[1, '4']] - throughput: 2.5 + shape: h + lanes: 4 + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: 1 +- name: mul + operands: + - class: register + prefix: v + shape: b + lanes: 8 + - class: register + prefix: v + shape: b + lanes: 8 + - class: register + prefix: v + shape: b + lanes: 8 + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 uops: 1 - name: mul operands: - class: register prefix: v shape: s + lanes: 4 - class: register prefix: v shape: s + lanes: 4 - class: register prefix: v shape: s + lanes: 4 latency: 7.0 - port_pressure: [[1, '4']] - throughput: 2.5 - uops: 1 + port_pressure: [[2, '3']] + throughput: 2.0 + uops: 2 - name: mul operands: - class: register prefix: v shape: h + lanes: 8 - class: register prefix: v shape: h + lanes: 8 - class: register prefix: v shape: h + lanes: 8 latency: 7.0 - port_pressure: [[1, '4']] - throughput: 2.5 + port_pressure: [[2, '3']] + throughput: 2.0 + uops: 1 +- name: mul + operands: + - class: register + prefix: v + shape: b + lanes: 16 + - class: register + prefix: v + shape: b + lanes: 16 + - class: register + prefix: v + shape: b + lanes: 16 + latency: 7.0 + port_pressure: [[2, '3']] + throughput: 2.0 uops: 1 # arithmetic instructions: [s|u]mulh (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: [smulh, umulh] @@ -952,7 +1015,7 @@ instruction_forms: - class: register prefix: x latency: 6.0 - port_pressure: [[1, '3']] + port_pressure: [[5, '3']] throughput: 5.0 uops: 1 - name: sdiv @@ -963,9 +1026,9 @@ instruction_forms: prefix: w - class: register prefix: w - latency: 4.0 - port_pressure: [[1, '3']] - throughput: 1.0 + latency: 6.0 + port_pressure: [[5, '3']] + throughput: 5.0 uops: 1 # arithmetic instructions: udiv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: udiv @@ -977,7 +1040,7 @@ instruction_forms: - class: register prefix: x latency: 6.0 - port_pressure: [[1, '3']] + port_pressure: [[5, '3']] throughput: 5.0 uops: 1 - name: udiv @@ -988,9 +1051,9 @@ instruction_forms: prefix: w - class: register prefix: w - latency: 4.0 - port_pressure: [[1, '3']] - throughput: 1.0 + latency: 6.0 + port_pressure: [[5, '3']] + throughput: 5.0 uops: 1 # arithmetic instructions: madd (latency and throughput, port data from AArch64SchedTSV110.td) - name: madd @@ -1003,9 +1066,9 @@ instruction_forms: prefix: x - class: register prefix: x - latency: ~ + latency: 4.0 port_pressure: [[1, '3'], [1, '012']] - throughput: ~ + throughput: 1.0 uops: 2 - name: madd operands: @@ -1017,9 +1080,9 @@ instruction_forms: prefix: w - class: register prefix: w - latency: ~ + latency: 4.0 port_pressure: [[1, '3'], [1, '012']] - throughput: ~ + throughput: 1.0 uops: 2 # arithmetic instructions: [smaddl|umaddl] (latency and throughput, port data from AArch64SchedTSV110.td) - name: [smaddl,umaddl] @@ -1062,9 +1125,9 @@ instruction_forms: prefix: x - class: register prefix: x - latency: ~ + latency: 4.0 port_pressure: [[1, '3'], [1, '012']] - throughput: ~ + throughput: 1.0 uops: 2 - name: msub operands: @@ -1076,9 +1139,9 @@ instruction_forms: prefix: w - class: register prefix: w - latency: ~ + latency: 4.0 port_pressure: [[1, '3'], [1, '012']] - throughput: ~ + throughput: 1.0 uops: 2 # arithmetic instructions: smsubl (latency and throughput, port data from AArch64SchedTSV110.td) - name: smsubl @@ -1100,47 +1163,73 @@ instruction_forms: operands: - class: register prefix: v - shape: d + shape: s + lanes: 2 - class: register prefix: v - shape: d + shape: s + lanes: 2 - class: register prefix: v - shape: d - latency: 7.0 + shape: s + latency: 4.0 port_pressure: [[1, '4']] - throughput: 2.5 + throughput: 1.0 uops: 1 - name: mla operands: - class: register prefix: v shape: s + lanes: 4 - class: register prefix: v shape: s + lanes: 4 - class: register prefix: v shape: s + lanes: 4 latency: 7.0 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: 2 +- name: mla + operands: + - class: register + prefix: v + shape: h + lanes: 4 + - class: register + prefix: v + shape: h + lanes: 4 + - class: register + prefix: v + shape: h + lanes: 4 + latency: 4.0 port_pressure: [[1, '4']] - throughput: 2.5 + throughput: 1.0 uops: 1 - name: mla operands: - class: register prefix: v shape: h + lanes: 8 - class: register prefix: v shape: h + lanes: 8 - class: register prefix: v shape: h + lanes: 8 latency: 7.0 - port_pressure: [[1, '4']] - throughput: 2.5 - uops: 1 + port_pressure: [[2, '4']] + throughput: 2.0 + uops: 2 # arithmetic instructions: [s|u]max (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: [smax, umax] operands: @@ -1154,7 +1243,7 @@ instruction_forms: prefix: v shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[2, '45']] throughput: 0.5 uops: 1 # arithmetic instructions: [s|u]min (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) @@ -1170,7 +1259,7 @@ instruction_forms: prefix: v shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 # arithmetic instructions: [s|u]maxv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) @@ -1182,7 +1271,7 @@ instruction_forms: prefix: v shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 # arithmetic instructions: [s|u]minv (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) @@ -1194,7 +1283,7 @@ instruction_forms: prefix: v shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 # arithmetic instructions: neg (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) @@ -1225,8 +1314,8 @@ instruction_forms: - class: register prefix: d latency: 2.0 - port_pressure: [[1, '12']] - throughput: 0.333 + port_pressure: [[1, '45']] + throughput: 0.5 uops: 1 - name: neg operands: @@ -1237,7 +1326,7 @@ instruction_forms: prefix: v shape: d latency: 2.0 - port_pressure: [[1, '12']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 - name: neg @@ -1249,7 +1338,7 @@ instruction_forms: prefix: v shape: s latency: 2.0 - port_pressure: [[1, '12']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 - name: neg @@ -1261,7 +1350,7 @@ instruction_forms: prefix: v shape: h latency: 2.0 - port_pressure: [[1, '12']] + port_pressure: [[1, '45']] throughput: 0.5 uops: 1 # arithmetic instructions: negs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) @@ -1300,7 +1389,7 @@ instruction_forms: prefix: v shape: d latency: 4.0 - port_pressure: [[1, '45']] + port_pressure: [[2, '45']] throughput: 1.0 uops: 1 - name: fadd @@ -1316,7 +1405,7 @@ instruction_forms: shape: s latency: 5.0 port_pressure: [[1, '45']] - throughput: 1.321 + throughput: 0.5 uops: 1 # arithmetic instructions: fmadd (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: fmadd @@ -1331,7 +1420,7 @@ instruction_forms: prefix: d latency: 7.0 port_pressure: [[1, '45']] - throughput: 0.73 + throughput: 0.5 uops: 1 - name: fmadd operands: @@ -1345,7 +1434,7 @@ instruction_forms: prefix: s latency: 5.0 port_pressure: [[1, '45']] - throughput: 0.57 + throughput: 0.50 uops: 1 # arithmetic instructions: fnmsub (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: fnmsub @@ -1360,7 +1449,7 @@ instruction_forms: prefix: d latency: 7.0 port_pressure: [[1, '45']] - throughput: 0.73 + throughput: 0.5 uops: 1 - name: fnmsub operands: @@ -1374,7 +1463,7 @@ instruction_forms: prefix: s latency: 5.0 port_pressure: [[1, '45']] - throughput: 0.57 + throughput: 0.50 uops: 1 # arithmetic instructions: frint[a|m|p|x|z] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: frinta @@ -1479,7 +1568,7 @@ instruction_forms: prefix: v shape: d latency: 4.0 - port_pressure: [[1, '45']] + port_pressure: [[2, '45']] throughput: 1.0 uops: 1 - name: fsub @@ -1527,9 +1616,9 @@ instruction_forms: prefix: v shape: d latency: 2.0 - port_pressure: [[1, '45']] - throughput: 1 - uops: 1 + port_pressure: [[2, '45']] + throughput: 1.0 + uops: 2 - name: fneg operands: - class: register @@ -1567,7 +1656,7 @@ instruction_forms: prefix: v shape: d latency: 5.0 - port_pressure: [[1, '45']] + port_pressure: [[2, '45']] throughput: 1.0 uops: 1 - name: fmul @@ -1595,7 +1684,7 @@ instruction_forms: - class: register prefix: d latency: 6.0 - port_pressure: [[1, '4']] + port_pressure: [[6, '4'], [6, '5']] throughput: 6.0 uops: 1 - name: fdiv @@ -1607,7 +1696,7 @@ instruction_forms: - class: register prefix: s latency: 6.0 - port_pressure: [[1, '4']] + port_pressure: [[6, '4'], [6, '5']] throughput: 6.0 uops: 1 - name: fdiv @@ -1622,8 +1711,8 @@ instruction_forms: prefix: v shape: d latency: 16.0 - port_pressure: [[1, '4']] - throughput: 12..0 + port_pressure: [[12, '4'], [12, '5']] + throughput: 12.0 uops: 1 - name: fdiv operands: @@ -1637,7 +1726,7 @@ instruction_forms: prefix: v shape: s latency: 16.0 - port_pressure: [[1, '4']] + port_pressure: [[12, '4'], [12, '5']] throughput: 12.0 uops: 1 # arithmetic instructions: fmla (latency and throughput from ibench, uops and port data missed) @@ -1652,10 +1741,10 @@ instruction_forms: - class: register prefix: v shape: s - latency: 5.0 - port_pressure: ~ + latency: 4.0 + port_pressure: [[1, '45']] throughput: 0.5 - uops: ~ + uops: 1 - name: fmla operands: - class: register @@ -1667,10 +1756,10 @@ instruction_forms: - class: register prefix: v shape: d - latency: 7.0 - port_pressure: ~ + latency: 5.0 + port_pressure: [[2, '45']] throughput: 1.0 - uops: ~ + uops: 2 # arithmetic instructions: fsqrt (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: fsqrt operands: @@ -1679,7 +1768,7 @@ instruction_forms: - class: register prefix: d latency: 9.0 - port_pressure: [[1, '5']] + port_pressure: [[9, '4'], [9, '5']] throughput: 9.0 uops: 1 - name: fsqrt @@ -1689,7 +1778,7 @@ instruction_forms: - class: register prefix: s latency: 9.0 - port_pressure: [[1, '5']] + port_pressure: [[9, '4'], [9, '5']] throughput: 9.0 uops: 1 - name: fsqrt @@ -1701,7 +1790,7 @@ instruction_forms: prefix: v shape: d latency: 22.0 - port_pressure: [[1, '5']] + port_pressure: [[18, '4'], [18, '5']] throughput: 18.0 uops: 1 - name: fsqrt @@ -1713,7 +1802,7 @@ instruction_forms: prefix: v shape: s latency: 22.0 - port_pressure: [[1, '5']] + port_pressure: [[18, '4'], [18, '5']] throughput: 18.0 uops: 1 # arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) @@ -1726,7 +1815,7 @@ instruction_forms: prefix: v shape: d latency: 3.0 - port_pressure: [[1, '45']] + port_pressure: [[2, '45']] throughput: 1.0 uops: 1 - name: frecpe @@ -1738,7 +1827,7 @@ instruction_forms: prefix: v shape: s latency: 3.0 - port_pressure: [[1, '45']] + port_pressure: [[2, '45']] throughput: 1.0 uops: 1 # arithmetic instructions: fcmp (latency and throughput from ibench, port data from AArch64SchedTSV110.td) @@ -1750,7 +1839,7 @@ instruction_forms: imd: float latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: fcmp operands: @@ -1760,7 +1849,7 @@ instruction_forms: prefix: d latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: fcmp operands: @@ -1770,7 +1859,7 @@ instruction_forms: prefix: s latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 # arithmetic instructions: fcmpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fcmpe @@ -1781,7 +1870,7 @@ instruction_forms: imd: float latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: fcmpe operands: @@ -1791,7 +1880,7 @@ instruction_forms: prefix: d latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 - name: fcmpe operands: @@ -1801,7 +1890,7 @@ instruction_forms: prefix: s latency: 3.0 port_pressure: [[1, '45']] - throughput: 1.0 + throughput: 0.5 uops: 1 # arithmetic instructions: fcvt[as|pu｜zs|zu] (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: fcvt @@ -1856,89 +1945,17 @@ instruction_forms: throughput: 0.333 uops: 1 # mov instructions: mov (assumed free register renaming, register to register moves without conversion) -- name: mov +- name: [mov, mvn] operands: - class: register - prefix: w + prefix: '*' - class: register - prefix: w - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: d - - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov - operands: - - class: register - prefix: q - - class: register - prefix: q - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mov -# mov instructions: mvn (assumed free register renaming, register to register moves without conversion) -- name: mvn - operands: - - class: register - prefix: w - - class: register - prefix: w - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mvn - operands: - - class: register - prefix: x - - class: register - prefix: x - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mvn - operands: - - class: register - prefix: d - - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mvn - operands: - - class: register - prefix: q - - class: register - prefix: q - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: mvn + prefix: '*' + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: [mov, mvn] operands: - class: register prefix: v @@ -1946,10 +1963,10 @@ instruction_forms: - class: register prefix: v shape: '*' - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 + latency: 2.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 # mov instructions: mov[i|k|n|z] (assumed free register renaming, register to register moves without conversion) - name: [movi, movk, movn, movz] operands: @@ -1997,23 +2014,23 @@ instruction_forms: operands: - class: register prefix: v - shape: d + shape: "*" - class: register - prefix: x + prefix: '*' latency: 2.0 port_pressure: [[1, '4'], [1, '5']] - throughput: 0.667 + throughput: 1.0 uops: 2 - name: dup operands: - class: register - prefix: v - shape: s + prefix: '*' - class: register - prefix: w + prefix: v + shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.667 + port_pressure: [[1, '45']] + throughput: 0.5 uops: 2 # miscellaneous instructions: cmn (throughput from ibench, latency and port data from AArch64SchedTSV110.td) - name: cmn @@ -2097,29 +2114,6 @@ instruction_forms: port_pressure: [[1, '12']] throughput: 0.5 uops: 1 -# miscellaneous instructions: dup (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: dup - operands: - - class: register - prefix: v - shape: d - - class: register - prefix: x - throughput: 0.667 - latency: 2.0 - port_pressure: [[1, '5']] - uops: 1 -- name: dup - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: w - throughput: 0.667 - latency: 2.0 - port_pressure: [[1, '5']] - uops: 1 # miscellaneous instructions: extr (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) - name: extr operands: @@ -2166,214 +2160,34 @@ instruction_forms: port_pressure: [[1, '012']] uops: 1 # miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: zip1 +- name: [zip1, zip2, uzip1, uzip2] operands: - class: register prefix: v - shape: b + shape: '*' - class: register prefix: v - shape: b + shape: '*' - class: register prefix: v - shape: b + shape: '*' latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] + port_pressure: [[1, '45']] throughput: 0.5 - uops: 2 -- name: zip1 - operands: - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: zip1 - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -# miscellaneous instructions: zip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: zip2 - operands: - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: zip2 - operands: - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: zip2 - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -# miscellaneous instructions: uzip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: uzip1 - operands: - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: uzip1 - operands: - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: uzip1 - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -# miscellaneous instructions: uzip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: uzip2 - operands: - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - - class: register - prefix: v - shape: b - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: uzip2 - operands: - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - - class: register - prefix: v - shape: h - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 -- name: uzip2 - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - throughput: 0.5 - uops: 2 + uops: 1 # miscellaneous instructions: [scvtf|ucvtf] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions) - name: [scvtf, ucvtf] operands: - class: register prefix: v - shape: d + shape: '*' - class: register prefix: v - shape: d + shape: '*' latency: 3.0 - port_pressure: [[1, '45']] + port_pressure: [[1, '4'], [1, '5']] throughput: 1.0 uops: 1 -- name: [scvtf, ucvtf] - operands: - - class: register - prefix: v - shape: s - - class: register - prefix: v - shape: s - latency: 3.0 - port_pressure: [[2, '45']] - throughput: 2.0 - uops: 1 # miscellaneous instructions: [s|u]xt[b|h|w] (throughput and latency from asmbench, port data from AArch64SchedTSV110.td) - name: [sxtb, sxth, sxtw, uxtb, uxth, uxtw] operands: @@ -2383,7 +2197,7 @@ instruction_forms: prefix: '*' latency: 1.0 port_pressure: [[1, '012']] - throughput: 1.0 + throughput: 0.33333 uops: 1 # miscellaneous instructions: xtn2? (throughput and latency from asmbench, port data from AArch64SchedTSV110.td) - name: [xtn, xtn2] @@ -2411,89 +2225,29 @@ instruction_forms: imd: int latency: 1.0 port_pressure: [[1, '012']] - throughput: 1.0 + throughput: 0.33333 uops: 1 # miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion) - name: fmov operands: - class: register - prefix: d + prefix: '*' - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 + prefix: '*' + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 - name: fmov operands: - class: register - prefix: d - - class: register - prefix: x - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: x - - class: register - prefix: d - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: s - - class: register - prefix: s - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: s - - class: register - prefix: w - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: w - - class: register - prefix: s - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: d + prefix: '*' - class: immediate imd: float - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 -- name: fmov - operands: - - class: register - prefix: s - - class: immediate - imd: float - latency: 0.0 - port_pressure: [] - throughput: 0.0 - uops: 0 + latency: 1.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 # test instructions: tst (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) - name: tst operands: @@ -2557,7 +2311,7 @@ instruction_forms: - class: register prefix: s latency: 2.0 - port_pressure: [[1, '45']] + port_pressure: [[1, '4']] throughput: 1.0 uops: 1 # cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) @@ -2573,7 +2327,7 @@ instruction_forms: prefix: v shape: '*' latency: 2.0 - port_pressure: [[1, '45']] + port_pressure: [[1, '4']] throughput: 1.0 uops: 1 # cryptography instructions: sha1su0 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) @@ -2836,10 +2590,10 @@ instruction_forms: - name: ldur operands: - class: register - prefix: w + prefix: '*' - class: memory base: x - offset: imd + offset: '*' index: '*' scale: '*' post-indexed: false @@ -2850,17 +2604,31 @@ instruction_forms: - name: ldur operands: - class: register - prefix: x + prefix: '*' - class: memory base: x - offset: imd + offset: '*' index: '*' scale: '*' - post-indexed: false + post-indexed: true pre-indexed: false throughput: 0.5 latency: 4.0 - port_pressure: [[1, '67']] + port_pressure: [[1, '67'], [1, '012']] +- name: ldur + operands: + - class: register + prefix: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] # memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td) - name: [ldar, ldarb, ldaxr] operands: @@ -2904,9 +2672,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 - name: str operands: @@ -2919,9 +2687,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -2934,9 +2702,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -2949,10 +2717,10 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] - uops: 2 + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] + uops: 1 - name: str operands: - class: register @@ -2964,9 +2732,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -2979,9 +2747,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -2994,9 +2762,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 - name: str operands: @@ -3009,9 +2777,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -3024,9 +2792,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -3039,9 +2807,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 - name: str operands: @@ -3054,9 +2822,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: str operands: @@ -3069,9 +2837,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 0.5 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 # memory instructions: stlb (data from AArch64SchedTSV110.td) - name: strb @@ -3085,9 +2853,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 # memory instructions: stlr (data from AArch64SchedTSV110.td) - name: stlr @@ -3101,9 +2869,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 # memory instructions: stlrb (data from AArch64SchedTSV110.td) - name: stlrb @@ -3117,9 +2885,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 # memory instructions: stur (data from AArch64SchedTSV110.td) - name: stur @@ -3133,9 +2901,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 - name: stur operands: @@ -3148,9 +2916,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 # memory instructions: stur[b|h] (data from AArch64SchedTSV110.td) - name: [sturb, sturh] @@ -3164,9 +2932,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 0.5 - latency: 1.0 - port_pressure: [[1, '67']] + throughput: 1.0 + latency: 0 + port_pressure: [[1, '7']] uops: 1 # memory instructions: ldp (data from AArch64SchedTSV110.td) - name: ldp @@ -3182,27 +2950,27 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 1.0 + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 latency: 4.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 -- name: ldp - operands: - - class: register - prefix: x - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: true - post-indexed: false - throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 - name: ldp operands: - class: register @@ -3216,10 +2984,10 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: ldp operands: - class: register @@ -3234,8 +3002,8 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 8.0 - port_pressure: [[1, '67'], [1, '012']] + latency: 4.0 + port_pressure: [[2, '67']] uops: 2 - name: ldp operands: @@ -3251,9 +3019,9 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 4.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: ldp operands: - class: register @@ -3268,9 +3036,9 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 4.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: ldp operands: - class: register @@ -3285,9 +3053,9 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 4.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: ldp operands: - class: register @@ -3301,10 +3069,10 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 - name: ldp operands: - class: register @@ -3319,9 +3087,9 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 4.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 - name: ldp operands: - class: register @@ -3336,9 +3104,9 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 9.0 - port_pressure: [[2, '67'], [2, '012']] - uops: 4 + latency: 4.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 # memory instructions: stp (data from AArch64SchedTSV110.td) - name: stp operands: @@ -3354,9 +3122,9 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67']] - uops: 2 + latency: 0 + port_pressure: [[1, '7']] + uops: 1 - name: stp operands: - class: register @@ -3371,8 +3139,8 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: stp operands: @@ -3388,8 +3156,8 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: stp operands: @@ -3405,9 +3173,9 @@ instruction_forms: pre-indexed: false post-indexed: false throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67']] - uops: 2 + latency: 0 + port_pressure: [[1, '7']] + uops: 1 - name: stp operands: - class: register @@ -3422,8 +3190,8 @@ instruction_forms: pre-indexed: true post-indexed: false throughput: 1.0 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: stp operands: @@ -3439,8 +3207,8 @@ instruction_forms: pre-indexed: false post-indexed: true throughput: 1.0 - latency: 2.0 - port_pressure: [[1, '67'], [1, '012']] + latency: 0 + port_pressure: [[1, '7'], [1, '012']] uops: 2 - name: stp operands: @@ -3455,9 +3223,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7']] uops: 2 - name: stp operands: @@ -3472,9 +3240,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67'], [1, '012']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7'], [1, '012']] uops: 3 - name: stp operands: @@ -3489,9 +3257,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67'], [1, '012']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7'], [1, '012']] uops: 3 - name: stp operands: @@ -3506,9 +3274,9 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: false - throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7']] uops: 2 - name: stp operands: @@ -3523,9 +3291,9 @@ instruction_forms: scale: '*' pre-indexed: true post-indexed: false - throughput: 1.0 - latency: 3.0 - port_pressure: [[2, '67'], [1, '012']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7'], [1, '012']] uops: 3 - name: stp operands: @@ -3540,7 +3308,7 @@ instruction_forms: scale: '*' pre-indexed: false post-indexed: true - throughput: 1.0 - latency: 2.0 - port_pressure: [[2, '67'], [1, '012']] + throughput: 2.0 + latency: 0 + port_pressure: [[2, '7'], [1, '012']] uops: 3 From babb5e1d84b80b384177694607d369a9f2127889 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Thu, 27 Jan 2022 10:12:00 +0100 Subject: [PATCH 25/29] formatting --- osaca/semantics/marker_utils.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/osaca/semantics/marker_utils.py b/osaca/semantics/marker_utils.py index cfe0fb8..5ca09b8 100755 --- a/osaca/semantics/marker_utils.py +++ b/osaca/semantics/marker_utils.py @@ -138,7 +138,11 @@ def find_marked_section( index_start = i + 1 elif comments["end"] == line.comment: index_end = i - elif line.instruction in mov_instr and len(lines) > i + 1 and lines[i + 1].directive is not None: + elif ( + line.instruction in mov_instr + and len(lines) > i + 1 + and lines[i + 1].directive is not None + ): source = line.operands[0 if not reverse else 1] destination = line.operands[1 if not reverse else 0] # instruction pair matches, check for operands From 86b62ecb6dc52bd91b8cf41440808533e61a990f Mon Sep 17 00:00:00 2001 From: Jan <20126033+JanLJL@users.noreply.github.com> Date: Mon, 14 Feb 2022 10:42:01 +0100 Subject: [PATCH 26/29] fixed typo --- osaca/data/tsv110.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 8ccf52b..7b0d55c 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -2144,8 +2144,8 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 -# miscellaneous instructions: sbfz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) -- name: sbfz +# miscellaneous instructions: sbfiz (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: sbfiz operands: - class: register prefix: x From d51d84afccb7b53f9da7239884c347b7610fd368 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sun, 27 Feb 2022 17:19:15 +0800 Subject: [PATCH 27/29] adjust sshll instruction --- osaca/data/tsv110.yml | 30 - osaca/data/tsv110.yml.temp | 1214 ++++++++++++++++++++++++++++++++++++ 2 files changed, 1214 insertions(+), 30 deletions(-) create mode 100644 osaca/data/tsv110.yml.temp diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 8ccf52b..255dcd5 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -508,21 +508,6 @@ instruction_forms: port_pressure: [[1, '012']] uops: 1 # shift instructions: [s|u]shll (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) -- name: [sshll, ushll] - operands: - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - latency: 4.0 - throughput: 1.0 - port_pressure: [[1, '5']] - uops: 1 - name: [sshll, ushll] operands: - class: register @@ -538,21 +523,6 @@ instruction_forms: port_pressure: [[1, '5']] uops: 1 # shift instructions: sshll2 (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) -- name: sshll2 - operands: - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - - class: register - prefix: v - shape: '*' - latency: 4.0 - throughput: 1.0 - port_pressure: [[1, '5']] - uops: 1 - name: sshll2 operands: - class: register diff --git a/osaca/data/tsv110.yml.temp b/osaca/data/tsv110.yml.temp new file mode 100644 index 0000000..b424564 --- /dev/null +++ b/osaca/data/tsv110.yml.temp @@ -0,0 +1,1214 @@ +osaca_version: 0.4.6 +micro_architecture: TaiShan v110 # https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 +arch_code: tsv110 +isa: AArch64 +ROB_size: 128 # https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64SchedTSV110.td#L21 +retired_uOps_per_cycle: 4 +scheduler_size: ~ # unknown +hidden_loads: false +load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0} +load_throughput: [] +load_throughput_default: [[1, '67']] +store_throughput: [] +store_throughput_default: [[1, '67']] +ports: ['0', '1', '2', '3', '4', '5', '6', '7'] +port_model_scheme: | + +--------------------------------------------------------------------------------------------+ + | - entries | + +--------------------------------------------------------------------------------------------+ + 0 |ALU 1 |AB 2 |AB 3 |MDU 4 |FSU1 5 |FSU2 6 |LdSt 7 |LdSt + \/ \/ \/ \/ \/ \/ \/ \/ + +---------+ +---------+ +---------+ +-------------+ +-------+ +------ + +-------+ +-------+ + | INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST | + +---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+ + +---------+ +---------+ +-------+ +-------+ +instruction_forms: +- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq] + operands: + - class: identifier + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '12']] +# arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: adds (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: adds + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: ~ +# arithmetic instructions: sub (from AArch64SchedTSV110.td) +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '012']] + throughput: 0.33333 + uops: 1 +# arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: ~ +# arithmetic instructions: mul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 4.0 + port_pressure: [[1, '3']] + throughput: 1.0 + uops: ~ +# arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fadd + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +- name: fadd + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fsub (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsub + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.321 + uops: 1 +- name: fsub + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 4.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fmla (latency and throughput from ibench, port data missed) +- name: fmla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 4.0 + port_pressure: ~ + throughput: 0.5 + uops: ~ +- name: fmla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 5.0 + port_pressure: ~ + throughput: 1.322 + uops: ~ +# arithmetic instructions: fmul (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fmul + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fmul + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 0.5 + uops: 1 +- name: fmul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 5.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# arithmetic instructions: fdiv (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fdiv + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 26.0 + port_pressure: [[1, '45']] + throughput: 22.0 + uops: 1 +- name: fdiv + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 40.0 + port_pressure: [[1, '45']] + throughput: 36.0 + uops: 1 +# arithmetic instructions: fsqrt (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: fsqrt + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 34.0 + uops: ~ +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 22.0 + port_pressure: [[1, '45']] + throughput: 64.0 + uops: ~ +# arithmetic instructions: frecpe (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: frecpe + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: frecpe + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: mov + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: q + - class: register + prefix: q + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: register + prefix: v + shape: '*' + - class: register + prefix: v + shape: '*' + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# miscellaneous instructions: cmp (throughput from ibench, latency and port data from AArch64SchedTSV110.td) +- name: cmp + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +- name: cmp + operands: + - class: register + prefix: w + - class: register + prefix: w + latency: 1.0 + port_pressure: [1, '12'] + throughput: 0.5 + uops: 1 +# miscellaneous instructions: dup (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [2, '45'] + throughput: 0.667 + uops: 2 +# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +- name: fmov + operands: + - class: register + prefix: s + - class: immediate + imd: int + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +# memory instructions: ldr (data from AArch64SchedTSV110.td) +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: ldur (data from AArch64SchedTSV110.td) +- name: ldur + operands: + - class: register + prefix: w + - class: memory + base: x + offset: imd + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] +# memory instructions: str (data from AArch64SchedTSV110.td) +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: str + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 5.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +# memory instructions: stur (data from AArch64SchedTSV110.td) +- name: stur + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +- name: stur + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '67']] + uops: 1 +# memory instructions: ldp (data from AArch64SchedTSV110.td) +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 8.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 8.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 9.0 + port_pressure: [[2, '67'], [2, '012']] + uops: 4 +# memory instructions: stp (data from AArch64SchedTSV110.td) +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67'] + uops: 2 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 2.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67'] + uops: 2 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67']] + uops: 2 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 3.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 2.0 + port_pressure: [[2, '67'], [1, '012']] + uops: 3 + From 54da7568d91212f3c37acc6b139c7e2fbba6361c Mon Sep 17 00:00:00 2001 From: JanLJL Date: Thu, 17 Mar 2022 16:38:28 +0100 Subject: [PATCH 28/29] small bugfixes --- osaca/data/isa/aarch64.yml | 2 +- osaca/semantics/arch_semantics.py | 7 +------ osaca/semantics/isa_semantics.py | 15 +++------------ 3 files changed, 5 insertions(+), 19 deletions(-) diff --git a/osaca/data/isa/aarch64.yml b/osaca/data/isa/aarch64.yml index fa51d0d..85246ea 100644 --- a/osaca/data/isa/aarch64.yml +++ b/osaca/data/isa/aarch64.yml @@ -120,7 +120,7 @@ instruction_forms: post-indexed: "*" source: true destination: false - - name: [ldr, ldur] + - name: [ldr, ldur, ldrb, ldrh, ldrsb, ldrsh, ldrsw] operands: - class: register prefix: "*" diff --git a/osaca/semantics/arch_semantics.py b/osaca/semantics/arch_semantics.py index 103c71f..6940b7e 100755 --- a/osaca/semantics/arch_semantics.py +++ b/osaca/semantics/arch_semantics.py @@ -165,11 +165,7 @@ class ArchSemantics(ISASemantics): instruction_data = self._machine_model.get_instruction( instruction_form["instruction"], instruction_form["operands"] ) - if ( - not instruction_data - and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES - ): + if not instruction_data and instruction_form["instruction"][-1] in self.GAS_SUFFIXES: # check for instruction without GAS suffix instruction_data = self._machine_model.get_instruction( instruction_form["instruction"][:-1], instruction_form["operands"] @@ -200,7 +196,6 @@ class ArchSemantics(ISASemantics): ) if ( not instruction_data_reg - and self._isa == "x86" and instruction_form["instruction"][-1] in self.GAS_SUFFIXES ): # check for instruction without GAS suffix diff --git a/osaca/semantics/isa_semantics.py b/osaca/semantics/isa_semantics.py index a3161f4..fca5955 100755 --- a/osaca/semantics/isa_semantics.py +++ b/osaca/semantics/isa_semantics.py @@ -55,11 +55,7 @@ class ISASemantics(object): isa_data = self._isa_model.get_instruction( instruction_form["instruction"], instruction_form["operands"] ) - if ( - isa_data is None - and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES - ): + if isa_data is None and instruction_form["instruction"][-1] in self.GAS_SUFFIXES: # Check for instruction without GAS suffix isa_data = self._isa_model.get_instruction( instruction_form["instruction"][:-1], instruction_form["operands"] @@ -81,7 +77,6 @@ class ISASemantics(object): ) if ( isa_data_reg is None - and self._isa == "x86" and instruction_form["instruction"][-1] in self.GAS_SUFFIXES ): # Check for instruction without GAS suffix @@ -164,11 +159,7 @@ class ISASemantics(object): isa_data = self._isa_model.get_instruction( instruction_form["instruction"], instruction_form["operands"] ) - if ( - isa_data is None - and self._isa == "x86" - and instruction_form["instruction"][-1] in self.GAS_SUFFIXES - ): + if isa_data is None and instruction_form["instruction"][-1] in self.GAS_SUFFIXES: # Check for instruction without GAS suffix isa_data = self._isa_model.get_instruction( instruction_form["instruction"][:-1], instruction_form["operands"] @@ -192,7 +183,7 @@ class ISASemantics(object): for o in instruction_form.operands: if "pre_indexed" in o.get("memory", {}): # Assuming no isa_data.operation - if isa_data.get("operation", None) is not None: + if isa_data is not None and isa_data.get("operation", None) is not None: raise ValueError( "ISA information for pre-indexed instruction {!r} has operation set." "This is currently not supprted.".format(instruction_form.line) From 728bb03a93f820d07ac4cf23572cd2fbb7682ff0 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Sun, 20 Mar 2022 14:53:34 +0800 Subject: [PATCH 29/29] fix a bug about orr in tsv110 --- osaca/data/tsv110.yml | 35 +++++++++++++++++++++------------- osaca/parser/parser_AArch64.py | 3 ++- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index e4121dc..8f2d071 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -177,7 +177,7 @@ instruction_forms: port_pressure: [[1, '012']] uops: 1 # logical instructions: orn (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) -- name: orr +- name: orn operands: - class: register prefix: x @@ -189,7 +189,7 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 -- name: orr +- name: orn operands: - class: register prefix: w @@ -201,21 +201,30 @@ instruction_forms: latency: 1.0 port_pressure: [[1, '012']] uops: 1 -- name: orr +- name: orn operands: - class: register - prefix: v - shape: '*' + prefix: x - class: register - prefix: v - shape: '*' + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: orn + operands: - class: register - prefix: v - shape: '*' - throughput: 1 - latency: 2.0 - port_pressure: [[1, '4'], [1, '5']] - uops: 2 + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) - name: eor operands: diff --git a/osaca/parser/parser_AArch64.py b/osaca/parser/parser_AArch64.py index 705813c..3e80f83 100755 --- a/osaca/parser/parser_AArch64.py +++ b/osaca/parser/parser_AArch64.py @@ -104,6 +104,7 @@ class ParserAArch64(BaseParser): ^ pp.CaselessLiteral("ror") ^ pp.CaselessLiteral("sxtw") ^ pp.CaselessLiteral("uxtw") + ^ pp.CaselessLiteral("uxtb") ^ pp.CaselessLiteral("mul vl") ) arith_immediate = pp.Group( @@ -384,7 +385,7 @@ class ParserAArch64(BaseParser): base["prefix"] = "x" if index is not None and "name" in index and index["name"] == "sp": index["prefix"] = "x" - valid_shift_ops = ["lsl", "uxtw", "sxtw"] + valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"] if "index" in memory_address: if "shift" in memory_address["index"]: if memory_address["index"]["shift_op"].lower() in valid_shift_ops: